Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35619 )
Change subject: cpu/intel/common: Move intel_ht_sibling() to common folder ......................................................................
cpu/intel/common: Move intel_ht_sibling() to common folder
Make intel_ht_sibling() available on all platforms.
Will be used in MP init to only write "Core" MSRs from one thread on HyperThreading enabled platforms, to prevent raceconditions and resulting #GP if MSRs are written twice or are already locked.
Change-Id: I5d000b34ba4c6536dc866fbaf106b78e905e3e35 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/cpu/intel/common/Kconfig M src/cpu/intel/common/Makefile.inc M src/cpu/intel/common/common.h A src/cpu/intel/common/hyperthreading.c M src/cpu/intel/hyperthreading/intel_sibling.c M src/cpu/intel/model_f2x/Kconfig M src/cpu/intel/model_f2x/model_f2x_init.c M src/cpu/intel/model_f3x/Kconfig M src/cpu/intel/model_f3x/model_f3x_init.c M src/include/cpu/intel/hyperthreading.h 10 files changed, 60 insertions(+), 25 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/35619/1
diff --git a/src/cpu/intel/common/Kconfig b/src/cpu/intel/common/Kconfig index 4074d8c..4fa3aff 100644 --- a/src/cpu/intel/common/Kconfig +++ b/src/cpu/intel/common/Kconfig @@ -22,4 +22,7 @@ config CPU_INTEL_COMMON_TIMEBASE bool
+config CPU_INTEL_COMMON_HYPERTHREADING + bool + endif diff --git a/src/cpu/intel/common/Makefile.inc b/src/cpu/intel/common/Makefile.inc index c38e81c..0a84deb 100644 --- a/src/cpu/intel/common/Makefile.inc +++ b/src/cpu/intel/common/Makefile.inc @@ -1,4 +1,5 @@ ramstage-y += common_init.c +ramstage-$(CONFIG_CPU_INTEL_COMMON_HYPERTHREADING) += hyperthreading.c
ifeq ($(CONFIG_CPU_INTEL_COMMON_TIMEBASE),y) bootblock-y += fsb.c diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h index b9ac056..480dfe6 100644 --- a/src/cpu/intel/common/common.h +++ b/src/cpu/intel/common/common.h @@ -27,4 +27,9 @@ struct cppc_config; void cpu_init_cppc_config(struct cppc_config *config, u32 version);
+/* + * Returns true if it's not threat 0 on a hyperthreading enabled core. + */ +bool intel_ht_sibling(void); + #endif diff --git a/src/cpu/intel/common/hyperthreading.c b/src/cpu/intel/common/hyperthreading.c new file mode 100644 index 0000000..a1ac457 --- /dev/null +++ b/src/cpu/intel/common/hyperthreading.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/lapic.h> +#include <cpu/intel/common/common.h> +#include <arch/cpu.h> + +/* Return true if running thread does not have the smallest lapic ID + * within a CPU core. + */ +bool intel_ht_sibling(void) +{ + struct cpuid_result result; + unsigned int core_ids, apic_ids, threads; + + result = cpuid(1); + /* Is hyperthreading supported */ + if (!(result.edx & (1 << 28))) + return 0; + + apic_ids = 1; + if (cpuid_eax(0) >= 1) + apic_ids = (cpuid_ebx(1) >> 16) & 0xff; + if (apic_ids < 1) + apic_ids = 1; + + core_ids = 1; + if (cpuid_eax(0) >= 4) { + result = cpuid_ext(4, 0); + core_ids += (result.eax >> 26) & 0x3f; + } + + threads = (apic_ids / core_ids); + return !!(lapicid() & (threads-1)); +} diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index 3c3e53a..f5bcc87 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -25,30 +25,6 @@ static int first_time = 1; static int disable_siblings = !CONFIG(LOGICAL_CPUS);
-/* Return true if running thread does not have the smallest lapic ID - * within a CPU core. - */ -int intel_ht_sibling(void) -{ - unsigned int core_ids, apic_ids, threads; - - apic_ids = 1; - if (cpuid_eax(0) >= 1) - apic_ids = (cpuid_ebx(1) >> 16) & 0xff; - if (apic_ids < 1) - apic_ids = 1; - - core_ids = 1; - if (cpuid_eax(0) >= 4) { - struct cpuid_result result; - result = cpuid_ext(4, 0); - core_ids += (result.eax >> 26) & 0x3f; - } - - threads = (apic_ids / core_ids); - return !!(lapicid() & (threads-1)); -} - void intel_sibling_init(struct device *cpu) { unsigned int i, siblings; diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig index 9e70775..dcf9441 100644 --- a/src/cpu/intel/model_f2x/Kconfig +++ b/src/cpu/intel/model_f2x/Kconfig @@ -7,3 +7,5 @@ select SMP select SUPPORT_CPU_UCODE_IN_CBFS select SMM_ASEG + select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_HYPERTHREADING diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index e759a43..04710a9 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -17,6 +17,7 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/hyperthreading.h> +#include <cpu/intel/common/common.h> #include <cpu/x86/cache.h>
static void model_f2x_init(struct device *cpu) diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig index 7eaa820..9a5e2a1 100644 --- a/src/cpu/intel/model_f3x/Kconfig +++ b/src/cpu/intel/model_f3x/Kconfig @@ -6,3 +6,5 @@ select ARCH_RAMSTAGE_X86_32 select SMP select SUPPORT_CPU_UCODE_IN_CBFS + select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_HYPERTHREADING diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index d348df6..48e3872 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -17,6 +17,7 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/hyperthreading.h> +#include <cpu/intel/common/common.h> #include <cpu/x86/cache.h>
static void model_f3x_init(struct device *cpu) diff --git a/src/include/cpu/intel/hyperthreading.h b/src/include/cpu/intel/hyperthreading.h index c84a6a7..0a1461c 100644 --- a/src/include/cpu/intel/hyperthreading.h +++ b/src/include/cpu/intel/hyperthreading.h @@ -3,6 +3,5 @@
struct device; void intel_sibling_init(struct device *cpu); -int intel_ht_sibling(void);
#endif /* CPU_INTEL_HYPERTHREADING_H */
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35619 )
Change subject: cpu/intel/common: Move intel_ht_sibling() to common folder ......................................................................
Patch Set 1:
(8 comments)
https://review.coreboot.org/c/coreboot/+/35619/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35619/1//COMMIT_MSG@12 PS1, Line 12: HyperThreading Hyper-threading
https://en.wikipedia.org/wiki/Hyper-threading
https://review.coreboot.org/c/coreboot/+/35619/1//COMMIT_MSG@12 PS1, Line 12: raceconditions race conditions
https://en.wikipedia.org/wiki/Race_condition
https://review.coreboot.org/c/coreboot/+/35619/1/src/cpu/intel/common/common... File src/cpu/intel/common/common.h:
https://review.coreboot.org/c/coreboot/+/35619/1/src/cpu/intel/common/common... PS1, Line 31: hyperthreading Hyper-threading
https://review.coreboot.org/c/coreboot/+/35619/1/src/cpu/intel/common/common... PS1, Line 31: threat thread
https://review.coreboot.org/c/coreboot/+/35619/1/src/cpu/intel/common/hypert... File src/cpu/intel/common/hyperthreading.c:
https://review.coreboot.org/c/coreboot/+/35619/1/src/cpu/intel/common/hypert... PS1, Line 18: /* Return true if running thread does not have the smallest lapic ID Please use
/* * … */
https://review.coreboot.org/c/coreboot/+/35619/1/src/cpu/intel/common/hypert... PS1, Line 27: hyperthreading Hyper-threading
https://review.coreboot.org/c/coreboot/+/35619/1/src/cpu/intel/common/hypert... PS1, Line 29: 0 false
https://review.coreboot.org/c/coreboot/+/35619/1/src/cpu/intel/common/hypert... PS1, Line 44: - Please add spaces around the operator.
Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35619
to look at the new patch set (#2).
Change subject: cpu/intel/common: Move intel_ht_sibling() to common folder ......................................................................
cpu/intel/common: Move intel_ht_sibling() to common folder
Make intel_ht_sibling() available on all platforms.
Will be used in MP init to only write "Core" MSRs from one thread on HyperThreading enabled platforms, to prevent raceconditions and resulting #GP if MSRs are written twice or are already locked.
Change-Id: I5d000b34ba4c6536dc866fbaf106b78e905e3e35 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/cpu/intel/Makefile.inc M src/cpu/intel/common/Kconfig M src/cpu/intel/common/Makefile.inc M src/cpu/intel/common/common.h A src/cpu/intel/common/hyperthreading.c M src/cpu/intel/fsp_model_406dx/Makefile.inc M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/hyperthreading/intel_sibling.c M src/cpu/intel/model_1067x/Makefile.inc M src/cpu/intel/model_106cx/Makefile.inc M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/model_f2x/Kconfig M src/cpu/intel/model_f2x/model_f2x_init.c M src/cpu/intel/model_f3x/Kconfig M src/cpu/intel/model_f3x/model_f3x_init.c M src/include/cpu/intel/hyperthreading.h 17 files changed, 63 insertions(+), 31 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/35619/2
Hello Patrick Rudolph, build bot (Jenkins), David Guckian, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35619
to look at the new patch set (#3).
Change subject: cpu/intel/common: Move intel_ht_sibling() to common folder ......................................................................
cpu/intel/common: Move intel_ht_sibling() to common folder
Make intel_ht_sibling() available on all platforms.
Will be used in MP init to only write "Core" MSRs from one thread on HyperThreading enabled platforms, to prevent raceconditions and resulting #GP if MSRs are written twice or are already locked.
Change-Id: I5d000b34ba4c6536dc866fbaf106b78e905e3e35 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/cpu/intel/Makefile.inc M src/cpu/intel/common/Kconfig M src/cpu/intel/common/Makefile.inc M src/cpu/intel/common/common.h A src/cpu/intel/common/hyperthreading.c M src/cpu/intel/fsp_model_406dx/Makefile.inc M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/hyperthreading/intel_sibling.c M src/cpu/intel/model_1067x/Makefile.inc M src/cpu/intel/model_106cx/Makefile.inc M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/model_f2x/Kconfig M src/cpu/intel/model_f2x/model_f2x_init.c M src/cpu/intel/model_f3x/Kconfig M src/cpu/intel/model_f3x/model_f3x_init.c M src/include/cpu/intel/hyperthreading.h 17 files changed, 64 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/35619/3
Hello Patrick Rudolph, build bot (Jenkins), David Guckian, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35619
to look at the new patch set (#4).
Change subject: cpu/intel/common: Move intel_ht_sibling() to common folder ......................................................................
cpu/intel/common: Move intel_ht_sibling() to common folder
Make intel_ht_sibling() available on all platforms.
Will be used in MP init to only write "Core" MSRs from one thread on HyperThreading enabled platforms, to prevent race conditions and resulting #GP if MSRs are written twice or are already locked.
Change-Id: I5d000b34ba4c6536dc866fbaf106b78e905e3e35 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/cpu/intel/Makefile.inc M src/cpu/intel/common/Kconfig M src/cpu/intel/common/Makefile.inc M src/cpu/intel/common/common.h A src/cpu/intel/common/hyperthreading.c M src/cpu/intel/fsp_model_406dx/Makefile.inc M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/hyperthreading/intel_sibling.c M src/cpu/intel/model_1067x/Makefile.inc M src/cpu/intel/model_106cx/Makefile.inc M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/model_f2x/Kconfig M src/cpu/intel/model_f2x/model_f2x_init.c M src/cpu/intel/model_f3x/Kconfig M src/cpu/intel/model_f3x/model_f3x_init.c M src/include/cpu/intel/hyperthreading.h 17 files changed, 64 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/35619/4
Hello Patrick Rudolph, build bot (Jenkins), David Guckian, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35619
to look at the new patch set (#5).
Change subject: cpu/intel/common: Move intel_ht_sibling() to common folder ......................................................................
cpu/intel/common: Move intel_ht_sibling() to common folder
Make intel_ht_sibling() available on all platforms.
Will be used in MP init to only write "Core" MSRs from one thread on HyperThreading enabled platforms, to prevent race conditions and resulting #GP if MSRs are written twice or are already locked.
Change-Id: I5d000b34ba4c6536dc866fbaf106b78e905e3e35 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/cpu/intel/Makefile.inc M src/cpu/intel/common/Kconfig M src/cpu/intel/common/Makefile.inc M src/cpu/intel/common/common.h A src/cpu/intel/common/hyperthreading.c M src/cpu/intel/fsp_model_406dx/Makefile.inc M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/hyperthreading/intel_sibling.c M src/cpu/intel/model_1067x/Makefile.inc M src/cpu/intel/model_106cx/Makefile.inc M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/model_f2x/Kconfig M src/cpu/intel/model_f2x/model_f2x_init.c M src/cpu/intel/model_f3x/Kconfig M src/cpu/intel/model_f3x/model_f3x_init.c M src/include/cpu/intel/hyperthreading.h 17 files changed, 64 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/35619/5
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35619 )
Change subject: cpu/intel/common: Move intel_ht_sibling() to common folder ......................................................................
Patch Set 5:
(8 comments)
https://review.coreboot.org/c/coreboot/+/35619/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35619/1//COMMIT_MSG@12 PS1, Line 12: HyperThreading
Hyper-threading […]
Done
https://review.coreboot.org/c/coreboot/+/35619/1//COMMIT_MSG@12 PS1, Line 12: raceconditions
race conditions […]
Done
https://review.coreboot.org/c/coreboot/+/35619/1/src/cpu/intel/common/common... File src/cpu/intel/common/common.h:
https://review.coreboot.org/c/coreboot/+/35619/1/src/cpu/intel/common/common... PS1, Line 31: hyperthreading
Hyper-threading
Done
https://review.coreboot.org/c/coreboot/+/35619/1/src/cpu/intel/common/common... PS1, Line 31: threat
thread
Done
https://review.coreboot.org/c/coreboot/+/35619/1/src/cpu/intel/common/hypert... File src/cpu/intel/common/hyperthreading.c:
https://review.coreboot.org/c/coreboot/+/35619/1/src/cpu/intel/common/hypert... PS1, Line 18: /* Return true if running thread does not have the smallest lapic ID
Please use […]
Done
https://review.coreboot.org/c/coreboot/+/35619/1/src/cpu/intel/common/hypert... PS1, Line 27: hyperthreading
Hyper-threading
Done
https://review.coreboot.org/c/coreboot/+/35619/1/src/cpu/intel/common/hypert... PS1, Line 29: 0
false
Done
https://review.coreboot.org/c/coreboot/+/35619/1/src/cpu/intel/common/hypert... PS1, Line 44: -
Please add spaces around the operator.
Done
Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35619 )
Change subject: cpu/intel/common: Move intel_ht_sibling() to common folder ......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35619/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35619/5//COMMIT_MSG@7 PS5, Line 7: cpu/intel/common: Move intel_ht_sibling() to common folder does this really need to be moved? why not include ht/sibling?
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35619 )
Change subject: cpu/intel/common: Move intel_ht_sibling() to common folder ......................................................................
Patch Set 5: Code-Review+1
(3 comments)
https://review.coreboot.org/c/coreboot/+/35619/5/src/cpu/intel/common/common... File src/cpu/intel/common/common.h:
https://review.coreboot.org/c/coreboot/+/35619/5/src/cpu/intel/common/common... PS5, Line 33: bool Please include the header that defines this type.
https://review.coreboot.org/c/coreboot/+/35619/5/src/cpu/intel/common/hypert... File src/cpu/intel/common/hyperthreading.c:
https://review.coreboot.org/c/coreboot/+/35619/5/src/cpu/intel/common/hypert... PS5, Line 29: 28 Do we not have these bits defined somewhere?
https://review.coreboot.org/c/coreboot/+/35619/5/src/cpu/intel/common/hypert... PS5, Line 35: < 1 The only valid value to hit this condition. Why don't we just use == 0 ?
Hello Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, Michael Niewöhner, build bot (Jenkins), Furquan Shaikh, David Guckian, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35619
to look at the new patch set (#6).
Change subject: cpu/intel/common: Move intel_ht_sibling() to common folder ......................................................................
cpu/intel/common: Move intel_ht_sibling() to common folder
Make intel_ht_sibling() available on all platforms.
Will be used in MP init to only write "Core" MSRs from one thread on HyperThreading enabled platforms, to prevent race conditions and resulting #GP if MSRs are written twice or are already locked.
Change-Id: I5d000b34ba4c6536dc866fbaf106b78e905e3e35 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/arch/x86/include/arch/cpu.h M src/cpu/intel/Makefile.inc M src/cpu/intel/common/Kconfig M src/cpu/intel/common/Makefile.inc M src/cpu/intel/common/common.h A src/cpu/intel/common/hyperthreading.c M src/cpu/intel/fsp_model_406dx/Makefile.inc M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/hyperthreading/intel_sibling.c M src/cpu/intel/model_1067x/Makefile.inc M src/cpu/intel/model_106cx/Makefile.inc M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/model_f2x/Kconfig M src/cpu/intel/model_f2x/model_f2x_init.c M src/cpu/intel/model_f3x/Kconfig M src/cpu/intel/model_f3x/model_f3x_init.c M src/include/cpu/intel/hyperthreading.h 18 files changed, 66 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/35619/6
Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35619 )
Change subject: cpu/intel/common: Move intel_ht_sibling() to common folder ......................................................................
Patch Set 6:
(4 comments)
https://review.coreboot.org/c/coreboot/+/35619/5//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/35619/5//COMMIT_MSG@7 PS5, Line 7: cpu/intel/common: Move intel_ht_sibling() to common folder
does this really need to be moved? why not include ht/sibling?
It's only build on model_f2x and model_f3x.
https://review.coreboot.org/c/coreboot/+/35619/5/src/cpu/intel/common/common... File src/cpu/intel/common/common.h:
https://review.coreboot.org/c/coreboot/+/35619/5/src/cpu/intel/common/common... PS5, Line 33: bool
Please include the header that defines this type.
Done
https://review.coreboot.org/c/coreboot/+/35619/5/src/cpu/intel/common/hypert... File src/cpu/intel/common/hyperthreading.c:
https://review.coreboot.org/c/coreboot/+/35619/5/src/cpu/intel/common/hypert... PS5, Line 29: 28
Do we not have these bits defined somewhere?
Added definition
https://review.coreboot.org/c/coreboot/+/35619/5/src/cpu/intel/common/hypert... PS5, Line 35: < 1
The only valid value to hit this condition. […]
Done
Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35619 )
Change subject: cpu/intel/common: Move intel_ht_sibling() to common folder ......................................................................
Patch Set 6: Code-Review+2
Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35619 )
Change subject: cpu/intel/common: Move intel_ht_sibling() to common folder ......................................................................
cpu/intel/common: Move intel_ht_sibling() to common folder
Make intel_ht_sibling() available on all platforms.
Will be used in MP init to only write "Core" MSRs from one thread on HyperThreading enabled platforms, to prevent race conditions and resulting #GP if MSRs are written twice or are already locked.
Change-Id: I5d000b34ba4c6536dc866fbaf106b78e905e3e35 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/35619 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Aaron Durbin adurbin@chromium.org --- M src/arch/x86/include/arch/cpu.h M src/cpu/intel/Makefile.inc M src/cpu/intel/common/Kconfig M src/cpu/intel/common/Makefile.inc M src/cpu/intel/common/common.h A src/cpu/intel/common/hyperthreading.c M src/cpu/intel/fsp_model_406dx/Makefile.inc M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/hyperthreading/intel_sibling.c M src/cpu/intel/model_1067x/Makefile.inc M src/cpu/intel/model_106cx/Makefile.inc M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/model_f2x/Kconfig M src/cpu/intel/model_f2x/model_f2x_init.c M src/cpu/intel/model_f3x/Kconfig M src/cpu/intel/model_f3x/model_f3x_init.c M src/include/cpu/intel/hyperthreading.h 18 files changed, 66 insertions(+), 32 deletions(-)
Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index ffa532b..b824736 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -158,6 +158,7 @@
#define CPUID_FEATURE_PAE (1 << 6) #define CPUID_FEATURE_PSE36 (1 << 17) +#define CPUID_FEAURE_HTT (1 << 28)
// Intel leaf 0x4, AMD leaf 0x8000001d EAX
diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 3f89740..484e241 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -16,3 +16,5 @@ subdirs-$(CONFIG_NORTHBRIDGE_INTEL_FSP_RANGELEY) += fsp_model_406dx subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1 subdirs-$(CONFIG_CPU_INTEL_SOCKET_LGA775) += socket_LGA775 + +subdirs-y += common diff --git a/src/cpu/intel/common/Kconfig b/src/cpu/intel/common/Kconfig index 4074d8c..4fa3aff 100644 --- a/src/cpu/intel/common/Kconfig +++ b/src/cpu/intel/common/Kconfig @@ -22,4 +22,7 @@ config CPU_INTEL_COMMON_TIMEBASE bool
+config CPU_INTEL_COMMON_HYPERTHREADING + bool + endif diff --git a/src/cpu/intel/common/Makefile.inc b/src/cpu/intel/common/Makefile.inc index c38e81c..1612012 100644 --- a/src/cpu/intel/common/Makefile.inc +++ b/src/cpu/intel/common/Makefile.inc @@ -1,4 +1,5 @@ -ramstage-y += common_init.c +ramstage-$(CONFIG_CPU_INTEL_COMMON) += common_init.c +ramstage-$(CONFIG_CPU_INTEL_COMMON_HYPERTHREADING) += hyperthreading.c
ifeq ($(CONFIG_CPU_INTEL_COMMON_TIMEBASE),y) bootblock-y += fsb.c diff --git a/src/cpu/intel/common/common.h b/src/cpu/intel/common/common.h index b9ac056..f6b8e57 100644 --- a/src/cpu/intel/common/common.h +++ b/src/cpu/intel/common/common.h @@ -15,6 +15,8 @@ #ifndef _CPU_INTEL_COMMON_H #define _CPU_INTEL_COMMON_H
+#include <stdint.h> + void set_vmx_and_lock(void); void set_feature_ctrl_vmx(void); void set_feature_ctrl_lock(void); @@ -27,4 +29,9 @@ struct cppc_config; void cpu_init_cppc_config(struct cppc_config *config, u32 version);
+/* + * Returns true if it's not thread 0 on a hyperthreading enabled core. + */ +bool intel_ht_sibling(void); + #endif diff --git a/src/cpu/intel/common/hyperthreading.c b/src/cpu/intel/common/hyperthreading.c new file mode 100644 index 0000000..4caf49e --- /dev/null +++ b/src/cpu/intel/common/hyperthreading.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/lapic.h> +#include <cpu/intel/common/common.h> +#include <arch/cpu.h> + +/* + * Return true if running thread does not have the smallest lapic ID + * within a CPU core. + */ +bool intel_ht_sibling(void) +{ + struct cpuid_result result; + unsigned int core_ids, apic_ids, threads; + + /* Is Hyper-Threading supported */ + if (!(cpuid_edx(1) & CPUID_FEAURE_HTT)) + return false; + + apic_ids = 1; + if (cpuid_eax(0) >= 1) + apic_ids = (cpuid_ebx(1) >> 16) & 0xff; + if (apic_ids == 0) + apic_ids = 1; + + core_ids = 1; + if (cpuid_eax(0) >= 4) { + result = cpuid_ext(4, 0); + core_ids += (result.eax >> 26) & 0x3f; + } + + threads = (apic_ids / core_ids); + return !!(lapicid() & (threads - 1)); +} diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc index d7fb4a8..a3ebe3d 100644 --- a/src/cpu/intel/fsp_model_406dx/Makefile.inc +++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc @@ -13,7 +13,6 @@
ramstage-y += model_406dx_init.c subdirs-y += ../../x86/name -subdirs-y += ../common
subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 7661a4e..aebeed4 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -21,7 +21,6 @@ subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../turbo -subdirs-y += ../common
cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3c-*) cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-45-*) diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index 3c3e53a..f5bcc87 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -25,30 +25,6 @@ static int first_time = 1; static int disable_siblings = !CONFIG(LOGICAL_CPUS);
-/* Return true if running thread does not have the smallest lapic ID - * within a CPU core. - */ -int intel_ht_sibling(void) -{ - unsigned int core_ids, apic_ids, threads; - - apic_ids = 1; - if (cpuid_eax(0) >= 1) - apic_ids = (cpuid_ebx(1) >> 16) & 0xff; - if (apic_ids < 1) - apic_ids = 1; - - core_ids = 1; - if (cpuid_eax(0) >= 4) { - struct cpuid_result result; - result = cpuid_ext(4, 0); - core_ids += (result.eax >> 26) & 0x3f; - } - - threads = (apic_ids / core_ids); - return !!(lapicid() & (threads-1)); -} - void intel_sibling_init(struct device *cpu) { unsigned int i, siblings; diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc index 743e780..545f04d 100644 --- a/src/cpu/intel/model_1067x/Makefile.inc +++ b/src/cpu/intel/model_1067x/Makefile.inc @@ -1,7 +1,6 @@ ramstage-y += model_1067x_init.c ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c subdirs-y += ../../x86/name -subdirs-y += ../common subdirs-y += ../smm/gen1
cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-17-*) diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc index 6701e6f..6d8414e 100644 --- a/src/cpu/intel/model_106cx/Makefile.inc +++ b/src/cpu/intel/model_106cx/Makefile.inc @@ -1,6 +1,5 @@ ramstage-y += model_106cx_init.c subdirs-y += ../../x86/name -subdirs-y += ../common subdirs-y += ../smm/gen1 ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index 4f6d3c2..dde4234 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -8,7 +8,6 @@ subdirs-y += ../../intel/microcode subdirs-y += ../../x86/smm subdirs-y += ../smm/gen1 -subdirs-y += ../common
ramstage-y += acpi.c
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index d19d860..391d126 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -1,7 +1,6 @@ ramstage-y += model_206ax_init.c subdirs-y += ../../x86/name subdirs-y += ../smm/gen1 -subdirs-y += ../common
subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr diff --git a/src/cpu/intel/model_f2x/Kconfig b/src/cpu/intel/model_f2x/Kconfig index 9e70775..dcf9441 100644 --- a/src/cpu/intel/model_f2x/Kconfig +++ b/src/cpu/intel/model_f2x/Kconfig @@ -7,3 +7,5 @@ select SMP select SUPPORT_CPU_UCODE_IN_CBFS select SMM_ASEG + select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_HYPERTHREADING diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index e759a43..04710a9 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -17,6 +17,7 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/hyperthreading.h> +#include <cpu/intel/common/common.h> #include <cpu/x86/cache.h>
static void model_f2x_init(struct device *cpu) diff --git a/src/cpu/intel/model_f3x/Kconfig b/src/cpu/intel/model_f3x/Kconfig index 7eaa820..9a5e2a1 100644 --- a/src/cpu/intel/model_f3x/Kconfig +++ b/src/cpu/intel/model_f3x/Kconfig @@ -6,3 +6,5 @@ select ARCH_RAMSTAGE_X86_32 select SMP select SUPPORT_CPU_UCODE_IN_CBFS + select CPU_INTEL_COMMON + select CPU_INTEL_COMMON_HYPERTHREADING diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index d348df6..48e3872 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -17,6 +17,7 @@ #include <cpu/x86/lapic.h> #include <cpu/intel/microcode.h> #include <cpu/intel/hyperthreading.h> +#include <cpu/intel/common/common.h> #include <cpu/x86/cache.h>
static void model_f3x_init(struct device *cpu) diff --git a/src/include/cpu/intel/hyperthreading.h b/src/include/cpu/intel/hyperthreading.h index c84a6a7..0a1461c 100644 --- a/src/include/cpu/intel/hyperthreading.h +++ b/src/include/cpu/intel/hyperthreading.h @@ -3,6 +3,5 @@
struct device; void intel_sibling_init(struct device *cpu); -int intel_ht_sibling(void);
#endif /* CPU_INTEL_HYPERTHREADING_H */
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