coreboot-gerrit September 2019

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Change in coreboot[master]: soc/intel/common/block/cse: Add boot partition related APIs
by Sridhar Siricilla (Code Review) 17 Sep '19

17 Sep '19

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35402 ) Change subject: soc/intel/common/block/cse: Add boot partition related APIs ...................................................................... Patch Set 6: (4 comments) This change is ready for review. https://review.coreboot.org/c/coreboot/+/35402/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/35402/3//COMMIT_MSG@11 PS3, Line 11: within CSE region, and their version and partition status. : SET_BOOT_PARTITION_INFO - Sets the next boot partition to boot for CSE > line between paragraphs will make it more readable. Done https://review.coreboot.org/c/coreboot/+/35402/3/src/soc/intel/common/block… File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/35402/3/src/soc/intel/common/block… PS3, Line 189: uint8_t current_bp; > add description Done https://review.coreboot.org/c/coreboot/+/35402/3/src/soc/intel/common/block… PS3, Line 198: uint8_t flags; > add description Done https://review.coreboot.org/c/coreboot/+/35402/2/src/soc/intel/common/block… File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/35402/2/src/soc/intel/common/block… PS2, Line 153: BP_STATUS_HOST_REQUEST_FOR_PARTITION_SWITCH = 3, > please, no space before tabs Done -- To view, visit https://review.coreboot.org/c/coreboot/+/35402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa62409c0616d5913d21374a8a6804f82258eb4f Gerrit-Change-Number: 35402 Gerrit-PatchSet: 6 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 17 Sep 2019 13:05:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mainboard/lenovo/t410: Add new port
by Patrick Rudolph (Code Review) 17 Sep '19

17 Sep '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/11791 ) Change subject: mainboard/lenovo/t410: Add new port ...................................................................... Patch Set 20: (1 comment) https://review.coreboot.org/c/coreboot/+/11791/17/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/romstage.c: https://review.coreboot.org/c/coreboot/+/11791/17/src/mainboard/lenovo/t410… PS17, Line 74: static const u32 rcba_dump3[] = { : /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000, : /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000, : /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 3340 */ 0x000fffff, 0x00000000, 0x00000000, 0x00000000, : /* 3350 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 3360 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 3370 */ 0x00000000, 0x00000000, 0x7f8fdfff, 0x00000000, : /* 3380 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 3390 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 33a0 */ 0x00003900, 0x00000000, 0x00000000, 0x00000000, : /* 33b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 33c0 */ 0x00010000, 0x00000000, 0x00000000, 0x0001004b, : /* 33d0 */ 0x06000008, 0x00010000, 0x00000000, 0x00000000, : /* 33e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 33f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 3400 */ 0x0000001c, 0x00000080, 0x00000000, 0x00000000, : /* 3410 */ 0x00000c61, 0x00000000, 0x16e41fe1, 0xbf4f001f, : /* 3420 */ 0x00000000, 0x00060010, 0x0000000d, 0x00000000, : /* 3430 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 3440 */ 0xdeaddeed, 0x00000000, 0x00000000, 0x00000000, : /* 3450 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 3460 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 3470 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 3480 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 3490 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 34a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 34b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 34c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 34d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 34e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 34f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 3500 */ 0x2000055f, 0x2000055f, 0x2000074b, 0x2000014b, : /* 3510 */ 0x2000014b, 0x2000074b, 0x2000074b, 0x2000074b, : /* 3520 */ 0x2000055f, 0x2000055f, 0x2000074b, 0x2000074b, : /* 3530 */ 0x20000557, 0x2000055f, 0x00000000, 0x00000000, : /* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 3560 */ 0x00000001, 0x000026a3, 0x00040002, 0x01000052, : /* 3570 */ 0x02000772, 0x16000f8f, 0x1800ff4f, 0x0001d630, : /* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 3590 */ 0x00000003, 0x00000000, 0x00000000, 0x00000000, : /* 35a0 */ 0xfc000201, 0x3c000201, 0x00000000, 0x00000000, : /* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 3600 */ 0x0a001f00, 0x00000000, 0x00000000, 0x00000001, : /* 3610 */ 0x00010000, 0x00000000, 0x00000000, 0x00000000, : /* 3620 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 3630 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 3640 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 3650 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 3660 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 3670 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 3680 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 3690 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 36a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 36b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 36c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 36d0 */ 0x00000000, 0x089c0018, 0x00000000, 0x00000000, : /* 36e0 */ 0x11111111, 0x00000000, 0x00000000, 0x00000000, : /* 36f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : /* 3700 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, : }; > This should come from inteltool RCBA dump on vendor firmware. […] Nicolas who did the original port dumped them from the vendor firmware. -- To view, visit https://review.coreboot.org/c/coreboot/+/11791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Gerrit-Change-Number: 11791 Gerrit-PatchSet: 20 Gerrit-Owner: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Eloy Degen Gerrit-CC: Matt Parnell <mparnell(a)gmail.com> Gerrit-CC: Okashi Odayakana <okashi(a)okashi.me> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Comment-Date: Tue, 17 Sep 2019 12:17:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: superio/common: Fix types in printf
by Patrick Georgi (Code Review) 17 Sep '19

17 Sep '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35433 ) Change subject: superio/common: Fix types in printf ...................................................................... superio/common: Fix types in printf Found by Coverity Scan #1405310 Change-Id: I53146e7fc402500effc63ce276ecfce4d72a4f7f Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/superio/common/ssdt.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/35433/1 diff --git a/src/superio/common/ssdt.c b/src/superio/common/ssdt.c index 035f06a..a919aa5 100644 --- a/src/superio/common/ssdt.c +++ b/src/superio/common/ssdt.c @@ -127,11 +127,11 @@ if (!res || !res->base || !res->size) continue; - snprintf(name, sizeof(name), "IO%XB", i); + snprintf(name, sizeof(name), "IO%zXB", i); name[4] = '\0'; acpigen_write_name_integer(name, res->base); - snprintf(name, sizeof(name), "IO%XS", i); + snprintf(name, sizeof(name), "IO%zXS", i); name[4] = '\0'; acpigen_write_name_integer(name, res->size); } -- To view, visit https://review.coreboot.org/c/coreboot/+/35433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I53146e7fc402500effc63ce276ecfce4d72a4f7f Gerrit-Change-Number: 35433 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/kahlee: Add SMBIOS type for QCA6174A on Liara board
by Amanda Hwang (Code Review) 17 Sep '19

17 Sep '19

Amanda Hwang has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30150 ) Change subject: mb/google/kahlee: Add SMBIOS type for QCA6174A on Liara board ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/30150 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d1f84898bb4130b55508cc29fa2412ec8bad658 Gerrit-Change-Number: 30150 Gerrit-PatchSet: 8 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Kurtz <djkurtz(a)google.com> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-CC: Idwer Vollering <vidwer(a)gmail.com> Gerrit-CC: Ivy Jian <ivy_jian(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller
by Bill XIE (Code Review) 17 Sep '19

17 Sep '19

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31631 Change subject: mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller ...................................................................... mb/lenovo/t430s: Open PCIe port #5 for Thunderbolt controller Some T430s variants has a Thunderbolt controller wired to PCIe port #5, so it had better be left on for T430s. (T431s do not have that) The controller hotplugs itself to the chipset when a downstream device is hotplugged into it, so the hotplug capability should be enabled on PCIe port #5. Change-Id: I61f41db100f398069e50e2da8a378b3a8d1c84bf Signed-off-by: Bill XIE <persmule(a)gmail.com> --- M src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/31631/1 diff --git a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb index ff30702..ee94979 100644 --- a/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb +++ b/src/mainboard/lenovo/t430s/variants/t430s/overridetree.cb @@ -1,6 +1,11 @@ chip northbridge/intel/sandybridge device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH + # Enable hotplug on Port 5 for Thunderbolt controller + register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 1, 0, 0, 0 }" + device pci 1c.4 on + subsystemid 0x17aa 0x21fb + end # PCIe Port #5 Thunderbolt controller device pci 1f.0 on chip ec/lenovo/h8 register "has_bdc_detection" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/31631 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61f41db100f398069e50e2da8a378b3a8d1c84bf Gerrit-Change-Number: 31631 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/model_2065x: Don't redefine CPU_ADDR_BITS
by Arthur Heymans (Code Review) 17 Sep '19

17 Sep '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35436 ) Change subject: cpu/intel/model_2065x: Don't redefine CPU_ADDR_BITS ...................................................................... cpu/intel/model_2065x: Don't redefine CPU_ADDR_BITS This Kconfig symbol is set at a default of 36 in cpu/x86 and is now only used in the romcc bootblock to set up caching to upgrade the microcode. It's not mainboard specific. Change-Id: I29d3a8308025e586a823603f8d6edafd30cb9d95 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x201/Kconfig M src/mainboard/packardbell/ms2290/Kconfig 2 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/35436/1 diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index 0f8c4d4..905d81d 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -43,10 +43,6 @@ int default 4 -config CPU_ADDR_BITS - int - default 36 - # Without the Intel ME's EFFS partition some PCIe devices (like the USB and SATA # controllers) don't work as expected config ME_CLEANER_ARGS diff --git a/src/mainboard/packardbell/ms2290/Kconfig b/src/mainboard/packardbell/ms2290/Kconfig index 932d6b8..a104fec 100644 --- a/src/mainboard/packardbell/ms2290/Kconfig +++ b/src/mainboard/packardbell/ms2290/Kconfig @@ -42,8 +42,4 @@ int default 4 -config CPU_ADDR_BITS - int - default 36 - endif -- To view, visit https://review.coreboot.org/c/coreboot/+/35436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29d3a8308025e586a823603f8d6edafd30cb9d95 Gerrit-Change-Number: 35436 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/nehalem: Move MMCONF_BASE_ADDRESS to a common place
by Arthur Heymans (Code Review) 17 Sep '19

17 Sep '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35435 ) Change subject: nb/nehalem: Move MMCONF_BASE_ADDRESS to a common place ...................................................................... nb/nehalem: Move MMCONF_BASE_ADDRESS to a common place Change-Id: I872959c4a38e28c29220b81c9fe029e7fc553ccf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x201/Kconfig M src/mainboard/packardbell/ms2290/Kconfig M src/northbridge/intel/nehalem/Kconfig 3 files changed, 4 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/35435/1 diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index 69e2038..0f8c4d4 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -31,10 +31,6 @@ string default "ThinkPad X201" -config MMCONF_BASE_ADDRESS - hex - default 0xe0000000 - config USBDEBUG_HCD_INDEX int default 2 diff --git a/src/mainboard/packardbell/ms2290/Kconfig b/src/mainboard/packardbell/ms2290/Kconfig index 6315591..932d6b8 100644 --- a/src/mainboard/packardbell/ms2290/Kconfig +++ b/src/mainboard/packardbell/ms2290/Kconfig @@ -30,10 +30,6 @@ string default "Packard Bell" -config MMCONF_BASE_ADDRESS - hex - default 0xe0000000 - config USBDEBUG_HCD_INDEX int default 2 diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 9c74ef6..f500d63 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -52,4 +52,8 @@ hex default 0x10000 +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/35435 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I872959c4a38e28c29220b81c9fe029e7fc553ccf Gerrit-Change-Number: 35435 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP] security/vboot: Fix regression with VBOOT_STARTS_IN_ROMSTAGE
by Kyösti Mälkki (Code Review) 17 Sep '19

17 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35408 ) Change subject: [WIP] security/vboot: Fix regression with VBOOT_STARTS_IN_ROMSTAGE ...................................................................... [WIP] security/vboot: Fix regression with VBOOT_STARTS_IN_ROMSTAGE Fix regression after commit 21160a7 Add definition for ENV_ROMSTAGE_OR_BEFORE to <rules.h> Builds with VBOOT_STARTS_IN_ROMSTAGE=y would evaluate ENV_ROMSTAGE_OR_BEFORE incorrectly for verstage-class. Follow-up changes for CBMEM console and timestamps, where defined(__PRE_RAM__) tests are replaced, are likely to have caused regressions such that VBOOT console and timestamps are missing. Change-Id: Idc274409c495efea95eeecd0538b2f8b847970ad Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/include/rules.h 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/35408/1 diff --git a/src/include/rules.h b/src/include/rules.h index dc4210a..a9569c1 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -267,7 +267,8 @@ #endif #define ENV_ROMSTAGE_OR_BEFORE \ - (ENV_DECOMPRESSOR || ENV_BOOTBLOCK || ENV_VERSTAGE || ENV_ROMSTAGE) + (ENV_DECOMPRESSOR || ENV_BOOTBLOCK || ENV_ROMSTAGE || \ + (ENV_VERSTAGE && !CONFIG(VBOOT_STARTS_IN_ROMSTAGE))) #if CONFIG(ARCH_X86) /* Indicates memory layout is determined with arch/x86/car.ld. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/35408 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc274409c495efea95eeecd0538b2f8b847970ad Gerrit-Change-Number: 35408 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP] binaryPI: Drop PSP Secure OS from build
by Kyösti Mälkki (Code Review) 17 Sep '19

17 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31075 Change subject: [WIP] binaryPI: Drop PSP Secure OS from build ...................................................................... [WIP] binaryPI: Drop PSP Secure OS from build For pcengines/apu2 variants we do not even send DRAM ready message to PSP. Possibly some GFX/DRM depends of running PSP but these devices are headless. And we don't support fTPM inside PSP either. Reduces blob footprint in SPI from 466 KiB to 234KiB. Change-Id: I803722171cba9b3601fb0b4a2c0e984566f435ab Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/amd/pi/hudson/Makefile.inc 1 file changed, 7 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/31075/1 diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index e990f9d..81fe7ff 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -85,13 +85,12 @@ FIRMWARE_TYPE= PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspBootLoader.Bypass.sbin -PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecovery.sbin -PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs.sbin -PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/trustlets.bin -TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/Trustlet.tkn.cert +#PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATE)/PspRecovery.sbin +#PSPSCUREOS_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureOs.sbin +#PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATE)/trustlets.bin +#TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/Trustlet.tkn.cert endif - ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) FIRMWARE_LOCATE=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) FIRMWARE_TYPE=CZ @@ -104,12 +103,12 @@ SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware2_prod_CZ.sbin endif -PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key -PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin +#PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATE)/RtmPubSigned$(FIRMWARE_TYPE).key +#PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATE)/PspNvram$(FIRMWARE_TYPE).bin SMUFWM_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE).sbin SMUFWM_FN_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuFirmware$(FIRMWARE_TYPE)_FN.sbin SMUSCS_FILE=$(top)/$(FIRMWARE_LOCATE)/SmuScs$(FIRMWARE_TYPE).bin -PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TYPE).Key +#PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATE)/PspSecureDebug$(FIRMWARE_TYPE).Key endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I803722171cba9b3601fb0b4a2c0e984566f435ab Gerrit-Change-Number: 31075 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP] binaryPI: Move Hudson firmware higher in CBFS
by Kyösti Mälkki (Code Review) 17 Sep '19

17 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31074 Change subject: [WIP] binaryPI: Move Hudson firmware higher in CBFS ...................................................................... [WIP] binaryPI: Move Hudson firmware higher in CBFS Move it above 'AGESA' to increase the maximum continuous free space in CBFS from 5.3 MiB to 5.8 MiB. Also fixes build for cases where CBFS_SIZE < ROM_SIZE, thus allowing FMAP regions. NOTE: Due to off-by-one error in binaryPI, offset 0xFFFA0000 that amdfwtool advertises fails for xHCI firmware loading. Change-Id: Ic78520f4248f0943769e66a8825911c0ddcc368c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/amd/pi/hudson/Makefile.inc 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/31074/1 diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 22e38c7..e990f9d 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -72,7 +72,11 @@ # # EC ROM should be 64K aligned. +ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) HUDSON_FWM_POSITION=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 0x20000 1) +else +HUDSON_FWM_POSITION=0xfff20000 +endif ifeq ($(CONFIG_HUDSON_PSP), y) @@ -191,6 +195,7 @@ $(OPT_2SMUFIRMWARE2_FN_FILE) \ $(OPT_2SMUSCS_FILE) \ --flashsize $(CONFIG_ROM_SIZE) \ + --location $(HUDSON_FWM_POSITION) \ --output $@ ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) -- To view, visit https://review.coreboot.org/c/coreboot/+/31074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic78520f4248f0943769e66a8825911c0ddcc368c Gerrit-Change-Number: 31074 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2019