coreboot-gerrit September 2019

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Change in coreboot[master]: device: Use scan_static_bus() over scan_lpc_bus()
by Patrick Rudolph (Code Review) 18 Sep '19

18 Sep '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29474 ) Change subject: device: Use scan_static_bus() over scan_lpc_bus() ...................................................................... Patch Set 7: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/29474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0eb005e41b9168fffc344ee8e666d43b605a30ba Gerrit-Change-Number: 29474 Gerrit-PatchSet: 7 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 18 Sep 2019 17:06:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/hatch/variants/helios: Add DPTF control for ambient sensor
by Sumeet R Pawnikar (Code Review) 18 Sep '19

18 Sep '19

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35447 ) Change subject: mb/google/hatch/variants/helios: Add DPTF control for ambient sensor ...................................................................... mb/google/hatch/variants/helios: Add DPTF control for ambient sensor Add DPTF based thermal contorl for ambient sensor for CML based Helios system. Also, update other sensor names information. BUG=139335207 BRANCH=None TEST=Build and Boot on Helios board. Change-Id: I322d53536fbdf6db70f5a24afb322d9f206eaeac Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl 1 file changed, 22 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/35447/1 diff --git a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl index 9aa3928..e3159c8 100644 --- a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl @@ -22,7 +22,7 @@ #define DPTF_CPU_ACTIVE_AC4 75 #define DPTF_TSR0_SENSOR_ID 0 -#define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" +#define DPTF_TSR0_SENSOR_NAME "Battery Charger" #define DPTF_TSR0_PASSIVE 65 #define DPTF_TSR0_CRITICAL 75 #define DPTF_TSR0_ACTIVE_AC0 50 @@ -33,7 +33,7 @@ #define DPTF_TSR0_ACTIVE_AC5 38 #define DPTF_TSR1_SENSOR_ID 1 -#define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" +#define DPTF_TSR1_SENSOR_NAME "5V Regulator" #define DPTF_TSR1_PASSIVE 45 #define DPTF_TSR1_CRITICAL 65 #define DPTF_TSR1_ACTIVE_AC0 50 @@ -43,6 +43,17 @@ #define DPTF_TSR1_ACTIVE_AC4 40 #define DPTF_TSR1_ACTIVE_AC5 38 +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "Ambient" +#define DPTF_TSR2_PASSIVE 50 +#define DPTF_TSR2_CRITICAL 65 +#define DPTF_TSR2_ACTIVE_AC0 50 +#define DPTF_TSR2_ACTIVE_AC1 47 +#define DPTF_TSR2_ACTIVE_AC2 45 +#define DPTF_TSR2_ACTIVE_AC3 42 +#define DPTF_TSR2_ACTIVE_AC4 40 +#define DPTF_TSR2_ACTIVE_AC5 38 + #define DPTF_ENABLE_CHARGER #define DPTF_ENABLE_FAN_CONTROL @@ -92,6 +103,10 @@ Package () { \_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 30, 0, 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 90, 69, 56, 46, 36, 30, 0, + 0, 0, 0 } }) @@ -99,11 +114,14 @@ /* CPU Throttle Effect on CPU */ Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 60, 0, 0, 0, 0 }, - /* CPU Throttle Effect on Ambient (TSR0) */ + /* CPU Throttle Effect on TSR0 */ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 60, 0, 0, 0, 0 }, - /* Charger Throttle Effect on Charger (TSR1) */ + /* Charger Throttle Effect on TSR1 */ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 60, 0, 0, 0, 0 }, + + /* CPU Throttle Effect on TSR2 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 60, 0, 0, 0, 0 }, }) Name (MPPC, Package () -- To view, visit https://review.coreboot.org/c/coreboot/+/35447 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I322d53536fbdf6db70f5a24afb322d9f206eaeac Gerrit-Change-Number: 35447 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch/variants/helios: Update DPTF parameters
by Sumeet R Pawnikar (Code Review) 18 Sep '19

18 Sep '19

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35446 ) Change subject: mb/google/hatch/variants/helios: Update DPTF parameters ...................................................................... mb/google/hatch/variants/helios: Update DPTF parameters Update DPTF thermal temperature threshold values for CML based Helios system. BUG=141087272 BRANCH=None TEST=Build and Boot on Helios board. Change-Id: I5c8502f8c9e6121c18024d2a8d5a4f7680797b8d Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl 1 file changed, 20 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/35446/1 diff --git a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl index 30dcf13..9aa3928 100644 --- a/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/helios/include/variant/acpi/dptf.asl @@ -15,21 +15,33 @@ #define DPTF_CPU_PASSIVE 95 #define DPTF_CPU_CRITICAL 105 -#define DPTF_CPU_ACTIVE_AC0 55 -#define DPTF_CPU_ACTIVE_AC1 50 -#define DPTF_CPU_ACTIVE_AC2 45 -#define DPTF_CPU_ACTIVE_AC3 30 -#define DPTF_CPU_ACTIVE_AC4 20 +#define DPTF_CPU_ACTIVE_AC0 87 +#define DPTF_CPU_ACTIVE_AC1 85 +#define DPTF_CPU_ACTIVE_AC2 83 +#define DPTF_CPU_ACTIVE_AC3 80 +#define DPTF_CPU_ACTIVE_AC4 75 #define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "Thermal Sensor 1" -#define DPTF_TSR0_PASSIVE 0 -#define DPTF_TSR0_CRITICAL 0 +#define DPTF_TSR0_PASSIVE 65 +#define DPTF_TSR0_CRITICAL 75 +#define DPTF_TSR0_ACTIVE_AC0 50 +#define DPTF_TSR0_ACTIVE_AC1 47 +#define DPTF_TSR0_ACTIVE_AC2 45 +#define DPTF_TSR0_ACTIVE_AC3 42 +#define DPTF_TSR0_ACTIVE_AC4 40 +#define DPTF_TSR0_ACTIVE_AC5 38 #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "Thermal Sensor 2" #define DPTF_TSR1_PASSIVE 45 -#define DPTF_TSR1_CRITICAL 0 +#define DPTF_TSR1_CRITICAL 65 +#define DPTF_TSR1_ACTIVE_AC0 50 +#define DPTF_TSR1_ACTIVE_AC1 47 +#define DPTF_TSR1_ACTIVE_AC2 45 +#define DPTF_TSR1_ACTIVE_AC3 42 +#define DPTF_TSR1_ACTIVE_AC4 40 +#define DPTF_TSR1_ACTIVE_AC5 38 #define DPTF_ENABLE_CHARGER #define DPTF_ENABLE_FAN_CONTROL -- To view, visit https://review.coreboot.org/c/coreboot/+/35446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c8502f8c9e6121c18024d2a8d5a4f7680797b8d Gerrit-Change-Number: 35446 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/via/nano: Enable TSC_MONOTONIC_TIMER
by Patrick Georgi (Code Review) 18 Sep '19

18 Sep '19

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/34203 ) Change subject: cpu/via/nano: Enable TSC_MONOTONIC_TIMER ...................................................................... cpu/via/nano: Enable TSC_MONOTONIC_TIMER Change-Id: Iea51a480fd7c696a6bbccc0b668acdbff6abffb7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34203 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/via/nano/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/cpu/via/nano/Kconfig b/src/cpu/via/nano/Kconfig index 93845d1..4b96c7c 100644 --- a/src/cpu/via/nano/Kconfig +++ b/src/cpu/via/nano/Kconfig @@ -24,7 +24,7 @@ select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select UDELAY_TSC - select NO_MONOTONIC_TIMER + select TSC_MONOTONIC_TIMER select MMX select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS -- To view, visit https://review.coreboot.org/c/coreboot/+/34203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea51a480fd7c696a6bbccc0b668acdbff6abffb7 Gerrit-Change-Number: 34203 Gerrit-PatchSet: 8 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: cpu/qemu-x86: Enable TSC_MONOTONIC_TIMER
by Patrick Georgi (Code Review) 18 Sep '19

18 Sep '19

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/34202 ) Change subject: cpu/qemu-x86: Enable TSC_MONOTONIC_TIMER ...................................................................... cpu/qemu-x86: Enable TSC_MONOTONIC_TIMER Change-Id: I72afb0c0d34157d1d2d9fe4ae6704cd2502f724d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34202 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/qemu-x86/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index c73ed38..a6c9b74 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -19,6 +19,6 @@ select ARCH_RAMSTAGE_X86_32 select SMP select UDELAY_TSC - select NO_MONOTONIC_TIMER + select TSC_MONOTONIC_TIMER select C_ENVIRONMENT_BOOTBLOCK select SMM_ASEG -- To view, visit https://review.coreboot.org/c/coreboot/+/34202 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72afb0c0d34157d1d2d9fe4ae6704cd2502f724d Gerrit-Change-Number: 34202 Gerrit-PatchSet: 8 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: x86emu: Drop UDELAY_LAPIC dependency
by Kyösti Mälkki (Code Review) 18 Sep '19

18 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34201 ) Change subject: x86emu: Drop UDELAY_LAPIC dependency ...................................................................... x86emu: Drop UDELAY_LAPIC dependency It won't build though, since current_time_from() has been removed. Change-Id: I2f7788f626c0504e6354a08b7986e4d18be140a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/34201/1 diff --git a/src/Kconfig b/src/Kconfig index b64fdca..ec0f35b 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -976,7 +976,7 @@ config X86EMU_DEBUG_TIMINGS bool "Output timing information" default n - depends on X86EMU_DEBUG && UDELAY_LAPIC && HAVE_MONOTONIC_TIMER + depends on X86EMU_DEBUG && HAVE_MONOTONIC_TIMER help Print timing information needed by i915tool. -- To view, visit https://review.coreboot.org/c/coreboot/+/34201 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f7788f626c0504e6354a08b7986e4d18be140a5 Gerrit-Change-Number: 34201 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/supermicro/x11ssh: drop plus sign/text in name
by Angel Pons (Code Review) 18 Sep '19

18 Sep '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35445 ) Change subject: mb/supermicro/x11ssh: drop plus sign/text in name ...................................................................... mb/supermicro/x11ssh: drop plus sign/text in name There is no board named X11SSH+-TF. Change-Id: Ide01a8d59c09747dfe7d59fd9e17bd5194fb14e4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/supermicro/x11ssh/Kconfig M src/mainboard/supermicro/x11ssh/Kconfig.name 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/35445/1 diff --git a/src/mainboard/supermicro/x11ssh/Kconfig b/src/mainboard/supermicro/x11ssh/Kconfig index 4f18a80..e6f342d 100644 --- a/src/mainboard/supermicro/x11ssh/Kconfig +++ b/src/mainboard/supermicro/x11ssh/Kconfig @@ -46,7 +46,7 @@ config VARIANT_DIR string - default "tf" if BOARD_SUPERMICRO_X11SSH_PLUS_TF + default "tf" if BOARD_SUPERMICRO_X11SSH_TF config DEVICETREE string @@ -54,7 +54,7 @@ config MAINBOARD_PART_NUMBER string - default "X11SSH-TF" if BOARD_SUPERMICRO_X11SSH_PLUS_TF + default "X11SSH-TF" if BOARD_SUPERMICRO_X11SSH_TF config MAX_CPUS int diff --git a/src/mainboard/supermicro/x11ssh/Kconfig.name b/src/mainboard/supermicro/x11ssh/Kconfig.name index a9b351b..43d0517 100644 --- a/src/mainboard/supermicro/x11ssh/Kconfig.name +++ b/src/mainboard/supermicro/x11ssh/Kconfig.name @@ -1,3 +1,3 @@ -config BOARD_SUPERMICRO_X11SSH_PLUS_TF - bool "X11SSH+-TF" +config BOARD_SUPERMICRO_X11SSH_TF + bool "X11SSH-TF" select BOARD_SUPERMICRO_BASEBOARD_X11SSH -- To view, visit https://review.coreboot.org/c/coreboot/+/35445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide01a8d59c09747dfe7d59fd9e17bd5194fb14e4 Gerrit-Change-Number: 35445 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload: Use interrupt transfers for USB hubs
by Patrick Georgi (Code Review) 18 Sep '19

18 Sep '19

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/18499 ) Change subject: libpayload: Use interrupt transfers for USB hubs ...................................................................... libpayload: Use interrupt transfers for USB hubs In interactive payloads, the USB stack's poll procedure is implicitly called from the UI loop. Since all USB control transfers are handled synchronously, polling hubs with these slows the UI significantly down. So switch to interrupt transfers that are done asynchronously and only perform control transfers when the hub reported a status change. We use the interrupt endpoint's max packet size instead of the theo- retical transfer length of `(bNrPorts + 1) / 8` as Linux' code mentions hubs that return too much data. Change-Id: I5af02d63e4b8e1451b160b77f3611b93658a7a48 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/18499 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M payloads/libpayload/drivers/usb/usbhub.c 1 file changed, 148 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/payloads/libpayload/drivers/usb/usbhub.c b/payloads/libpayload/drivers/usb/usbhub.c index 78643c0..87c5816 100644 --- a/payloads/libpayload/drivers/usb/usbhub.c +++ b/payloads/libpayload/drivers/usb/usbhub.c @@ -35,15 +35,39 @@ /* assume that host_to_device is overwritten if necessary */ #define DR_PORT gen_bmRequestType(host_to_device, class_type, other_recp) /* status (and status change) bits */ -#define PORT_CONNECTION 0x1 -#define PORT_ENABLE 0x2 -#define PORT_RESET 0x10 +#define PORT_CONNECTION 0x01 +#define PORT_ENABLE 0x02 +#define PORT_SUSPEND 0x04 +#define PORT_OVER_CURRENT 0x08 +#define PORT_RESET 0x10 +#define BH_PORT_RESET 0x20 +#define PORT_LINK_STATE 0x40 +#define PORT_CONFIG_ERROR 0x80 /* feature selectors (for setting / clearing features) */ -#define SEL_PORT_RESET 0x4 -#define SEL_PORT_POWER 0x8 -#define SEL_C_PORT_CONNECTION 0x10 +#define SEL_PORT_RESET 0x04 +#define SEL_PORT_POWER 0x08 +#define SEL_C_PORT_CONNECTION 0x10 +#define SEL_C_PORT_ENABLE 0x11 +#define SEL_C_PORT_SUSPEND 0x12 +#define SEL_C_PORT_OVER_CURRENT 0x13 +#define SEL_C_PORT_RESET 0x14 +#define SEL_C_PORT_LINK_STATE 0x19 +#define SEL_C_PORT_CONFIG_ERROR 0x1a +#define SEL_C_BH_PORT_RESET 0x1d /* request type (USB 3.0 hubs only) */ -#define SET_HUB_DEPTH 12 +#define SET_HUB_DEPTH 12 + +static endpoint_t * +usb_hub_interrupt_ep(usbdev_t *const dev) +{ + int i; + for (i = 0; i < dev->num_endp; ++i) { + if (dev->endpoints[i].type == INTERRUPT && + dev->endpoints[i].direction == IN) + return &dev->endpoints[i]; + } + return NULL; +} static int usb_hub_port_status_changed(usbdev_t *const dev, const int port) @@ -169,13 +193,99 @@ return; if (buf[1] & PORT_CONNECTION) clear_feature(dev, port, SEL_C_PORT_CONNECTION, DR_PORT); - if (buf[0] & PORT_CONNECTION) + if (buf[0] & PORT_CONNECTION) { + usb_debug("usbhub: Port coldplug at %d\n", port); generic_hub_scanport(dev, port); + } +} + +static int +usb_hub_handle_port_change(usbdev_t *const dev, const int port) +{ + static const struct { + unsigned short change_bit; + unsigned short clear_sel; + } change_bits[] = { + { PORT_CONNECTION, SEL_C_PORT_CONNECTION }, + { PORT_ENABLE, SEL_C_PORT_ENABLE }, + { PORT_SUSPEND, SEL_C_PORT_SUSPEND }, + { PORT_OVER_CURRENT, SEL_C_PORT_OVER_CURRENT }, + { PORT_RESET, SEL_C_PORT_RESET }, + { BH_PORT_RESET, SEL_C_BH_PORT_RESET }, + { PORT_LINK_STATE, SEL_C_PORT_LINK_STATE }, + { PORT_CONFIG_ERROR, SEL_C_PORT_CONFIG_ERROR }, + }; + int ret = 0; + unsigned int i; + unsigned short checked_bits = 0; + unsigned short buf[2] = { 0, 0 }; + + ret = get_status(dev, port, DR_PORT, sizeof(buf), buf); + if (ret < 0) + return ret; + + /* + * Second word holds the change bits. The interrupt transfer shows + * a logical or of these bits, so we have to clear them all. + */ + for (i = 0; i < ARRAY_SIZE(change_bits); ++i) { + if (buf[1] & change_bits[i].change_bit) + clear_feature(dev, port, change_bits[i].clear_sel, DR_PORT); + checked_bits |= change_bits[i].change_bit; + } + if (buf[1] & ~checked_bits) + usb_debug("usbhub: Spurious change bit at port %d\n", port); + + /* Now, handle connection changes. */ + if (buf[1] & PORT_CONNECTION) { + usb_debug("usbhub: Port change at %d\n", port); + ret = generic_hub_scanport(dev, port); + } + return ret; +} + +static void +usb_hub_poll(usbdev_t *const dev) +{ + unsigned int port, i; + u8 buf[32] = { 0 }; + const u8 *ibuf; + + /* First, gather all change bits from finished interrupt transfers. */ + const size_t port_bytes = MIN(ARRAY_SIZE(buf), + div_round_up(GEN_HUB(dev)->num_ports + 1, 8)); + while ((ibuf = dev->controller->poll_intr_queue(GEN_HUB(dev)->data))) { + for (i = 0; i < port_bytes; ++i) + buf[i] |= ibuf[i]; + } + + for (port = 1; port <= GEN_HUB(dev)->num_ports; ++port) { + /* ports start at bit1; bit0 is hub status change */ + if (buf[port / 8] & (1 << (port % 8))) { + if (usb_hub_handle_port_change(dev, port) < 0) + return; + } + } +} + +static void +usb_hub_destroy(usbdev_t *const dev) +{ + endpoint_t *const intr_ep = usb_hub_interrupt_ep(dev); + dev->controller->destroy_intr_queue(intr_ep, GEN_HUB(dev)->data); + generic_hub_destroy(dev); } void usb_hub_init(usbdev_t *const dev) { + endpoint_t *const intr_ep = usb_hub_interrupt_ep(dev); + if (!intr_ep) { + usb_debug("usbhub: ERROR: No interrupt-in endpoint found\n"); + return; + } + + /* Get number of ports from hub decriptor */ int type = is_usb_speed_ss(dev->speed) ? 0x2a : 0x29; /* similar enough */ hub_descriptor_t desc; /* won't fit the whole thing, we don't care */ if (get_descriptor(dev, gen_bmRequestType(device_to_host, class_type, @@ -187,10 +297,38 @@ if (is_usb_speed_ss(dev->speed)) usb_hub_set_hub_depth(dev); - if (generic_hub_init(dev, desc.bNbrPorts, &usb_hub_ops) < 0) + + /* + * Register interrupt transfer: + * one bit per port + one bit for the hub, + * 20 transfers in the queue, like our HID driver, + * one transfer per 256ms + */ + void *const intrq = dev->controller->create_intr_queue( + intr_ep, intr_ep->maxpacketsize, 20, 256); + if (!intrq) { + usb_detach_device(dev->controller, dev->address); return; + } + + /* + * Limit the number of ports by the max packet size of + * the interrupt endpoint. This shouldn't be necessary + * but prevents a potential overflow in usb_hub_poll(). + */ + const unsigned int num_ports = + MIN(desc.bNbrPorts, intr_ep->maxpacketsize * 8 - 1); + if (generic_hub_init(dev, num_ports, &usb_hub_ops)) { + dev->controller->destroy_intr_queue(intr_ep, intrq); + usb_detach_device(dev->controller, dev->address); + return; + } int port; - for (port = 1; port <= GEN_HUB(dev)->num_ports; ++port) + for (port = 1; port <= num_ports; ++port) usb_hub_port_initialize(dev, port); + + GEN_HUB(dev)->data = intrq; + dev->poll = usb_hub_poll; + dev->destroy = usb_hub_destroy; } -- To view, visit https://review.coreboot.org/c/coreboot/+/18499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5af02d63e4b8e1451b160b77f3611b93658a7a48 Gerrit-Change-Number: 18499 Gerrit-PatchSet: 6 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/octopus/variants/garg: add LTE sku to config power sequence
by Kevin Chiu (Code Review) 18 Sep '19

18 Sep '19

Kevin Chiu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35442 ) Change subject: mb/google/octopus/variants/garg: add LTE sku to config power sequence ...................................................................... mb/google/octopus/variants/garg: add LTE sku to config power sequence Add SKU#18 to config power sequence below: GPIOs related to power sequnce are GPIO_67 - EN_PP3300 GPIO_117 - FULL_CARD_POWER_ON_OFF GPIO_161 - PLT_RST_LTE_L 1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161 2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67 3. Power reset: - keep GPIO_67 and GPIO_117 high and - pull down GPIO_161 for 30ms then release it. BUG=b:134854577,b:137033609 BRANCH=octopus TEST=build Change-Id: I58e07518f6daaf608684c9fa1b1c88fc592ea117 Signed-off-by: Kevin Chiu <Kevin.Chiu(a)quantatw.com> --- M src/mainboard/google/octopus/variants/garg/variant.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/35442/1 diff --git a/src/mainboard/google/octopus/variants/garg/variant.c b/src/mainboard/google/octopus/variants/garg/variant.c index 2754e64..942ea5f 100644 --- a/src/mainboard/google/octopus/variants/garg/variant.c +++ b/src/mainboard/google/octopus/variants/garg/variant.c @@ -25,6 +25,8 @@ SKU_1_2A2C = 1, SKU_9_HDMI = 9, SKU_17_LTE = 17, + SKU_18_LTE_TS = 18, + SKU_37_2A2C_360 = 37, }; struct gpio_with_delay { @@ -78,6 +80,7 @@ switch (get_board_sku()) { case SKU_17_LTE: + case SKU_18_LTE_TS: power_off_lte_module(slp_typ); return; default: -- To view, visit https://review.coreboot.org/c/coreboot/+/35442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58e07518f6daaf608684c9fa1b1c88fc592ea117 Gerrit-Change-Number: 35442 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: mb/google/drallion: Add SPD files for drallion
by Amanda Hwang (Code Review) 18 Sep '19

18 Sep '19

Amanda Hwang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35346 ) Change subject: mb/google/drallion: Add SPD files for drallion ...................................................................... mb/google/drallion: Add SPD files for drallion This change adds seven SPD files for drallion BUG=b:139397313 TEST=Compile successfully Change-Id: I2f7e75fdbca4183bcd730e40fef4bfe280ab900b Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> --- A src/mainboard/google/drallion/spd/hynix_dimm_H5AN8G6NCJR-VKC.spd.hex A src/mainboard/google/drallion/spd/hynix_dimm_H5ANAG6NCMR-VKC.spd.hex A src/mainboard/google/drallion/spd/micron_dimm_MT40A1G16KNR-075E.spd.hex A src/mainboard/google/drallion/spd/micron_dimm_MT40A512M16LY-075E.spd.hex A src/mainboard/google/drallion/spd/micron_dimm_MT40A512M16TB-062EJ.spd.hex A src/mainboard/google/drallion/spd/samsung_dimm_K4A8G165WC-BCTD.spd.hex A src/mainboard/google/drallion/spd/samsung_dimm_K4AAG165WB-MCTD.spd.hex M src/mainboard/google/drallion/variants/drallion/Makefile.inc M src/mainboard/google/drallion/variants/drallion/memory.c 9 files changed, 240 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/35346/1 diff --git a/src/mainboard/google/drallion/spd/hynix_dimm_H5AN8G6NCJR-VKC.spd.hex b/src/mainboard/google/drallion/spd/hynix_dimm_H5AN8G6NCJR-VKC.spd.hex new file mode 100644 index 0000000..5050647 --- /dev/null +++ b/src/mainboard/google/drallion/spd/hynix_dimm_H5AN8G6NCJR-VKC.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 87 2E +0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 E2 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 AD 01 00 00 00 00 00 00 48 4D 41 38 35 31 53 +36 43 4A 52 36 4E 2D 56 4B 20 20 20 20 00 80 AD +FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/drallion/spd/hynix_dimm_H5ANAG6NCMR-VKC.spd.hex b/src/mainboard/google/drallion/spd/hynix_dimm_H5ANAG6NCMR-VKC.spd.hex new file mode 100644 index 0000000..1145389 --- /dev/null +++ b/src/mainboard/google/drallion/spd/hynix_dimm_H5ANAG6NCMR-VKC.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 85 21 91 08 00 60 00 03 01 03 00 00 +00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 A8 18 28 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0C 2B 2D 04 +16 35 23 0D 00 00 2C 0B 03 24 35 0C 03 2D 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 43 CE +0F 11 20 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 EF 55 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 AD 01 00 00 00 00 00 00 48 4D 41 41 31 47 53 +36 43 4D 52 38 4E 2D 56 4B 20 20 20 20 00 80 AD +FF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/drallion/spd/micron_dimm_MT40A1G16KNR-075E.spd.hex b/src/mainboard/google/drallion/spd/micron_dimm_MT40A1G16KNR-075E.spd.hex new file mode 100644 index 0000000..adc788f --- /dev/null +++ b/src/mainboard/google/drallion/spd/micron_dimm_MT40A1G16KNR-075E.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 85 21 00 08 00 60 00 03 01 03 00 00 +00 00 06 0D F8 FF 01 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 A8 18 28 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 60 8D +0F 01 1F 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 7D 21 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 2C 00 00 00 00 00 00 00 34 41 54 53 31 47 36 +34 48 5A 2D 32 47 36 45 31 20 20 20 20 31 80 2C +45 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/drallion/spd/micron_dimm_MT40A512M16LY-075E.spd.hex b/src/mainboard/google/drallion/spd/micron_dimm_MT40A512M16LY-075E.spd.hex new file mode 100644 index 0000000..410cac0 --- /dev/null +++ b/src/mainboard/google/drallion/spd/micron_dimm_MT40A512M16LY-075E.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 06 0D F8 FF 01 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 60 5B +0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 E2 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 2C 00 00 00 00 00 00 00 34 41 54 46 35 31 32 +36 34 48 5A 2D 32 47 36 45 31 20 20 20 31 80 2C +45 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/drallion/spd/micron_dimm_MT40A512M16TB-062EJ.spd.hex b/src/mainboard/google/drallion/spd/micron_dimm_MT40A512M16TB-062EJ.spd.hex new file mode 100644 index 0000000..1baacbc --- /dev/null +++ b/src/mainboard/google/drallion/spd/micron_dimm_MT40A512M16TB-062EJ.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 05 0D F8 FF 2B 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 30 53 +0F 01 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 C0 E2 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 2C 00 00 00 00 00 00 00 34 41 54 46 35 31 32 +36 34 48 5A 2D 33 47 32 4A 31 20 20 20 31 80 2C +4A 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/drallion/spd/samsung_dimm_K4A8G165WC-BCTD.spd.hex b/src/mainboard/google/drallion/spd/samsung_dimm_K4A8G165WC-BCTD.spd.hex new file mode 100644 index 0000000..3e84f21 --- /dev/null +++ b/src/mainboard/google/drallion/spd/samsung_dimm_K4A8G165WC-BCTD.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 45 21 00 08 00 60 00 03 02 03 00 00 +00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 00 87 2E +0F 11 02 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 DB 08 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 CE 00 00 00 00 00 00 00 4D 34 37 31 41 35 32 +34 34 43 42 30 2D 43 54 44 20 20 20 20 00 80 CE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/drallion/spd/samsung_dimm_K4AAG165WB-MCTD.spd.hex b/src/mainboard/google/drallion/spd/samsung_dimm_K4AAG165WB-MCTD.spd.hex new file mode 100644 index 0000000..da1e198 --- /dev/null +++ b/src/mainboard/google/drallion/spd/samsung_dimm_K4AAG165WB-MCTD.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 85 21 00 08 00 60 00 03 01 03 00 00 +00 00 06 0D F8 3F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 A8 18 28 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0C 2B 2D 04 +16 35 23 0D 00 00 2C 0B 03 24 35 0C 03 2D 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C 00 00 00 00 00 E7 00 D0 4E +0F 11 20 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 EF 55 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 CE 00 00 00 00 00 00 00 4D 34 37 31 41 31 4B +34 33 42 42 31 2D 43 54 44 20 20 20 20 00 80 CE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/drallion/variants/drallion/Makefile.inc b/src/mainboard/google/drallion/variants/drallion/Makefile.inc index 8e070d2..942d00b 100644 --- a/src/mainboard/google/drallion/variants/drallion/Makefile.inc +++ b/src/mainboard/google/drallion/variants/drallion/Makefile.inc @@ -15,6 +15,13 @@ ## GPP_F12-F16 indicates mem_id to match specific spd file SPD_SOURCES = empty_ddr4 # 0b00000 +SPD_SOURCES += micron_dimm_MT40A512M16LY-075E # 0b10100 +SPD_SOURCES += micron_dimm_MT40A512M16TB-062EJ # 0b11100 +SPD_SOURCES += micron_dimm_MT40A1G16KNR-075E # 0b10010 +SPD_SOURCES += hynix_dimm_H5AN8G6NCJR-VKC # 0b10001 +SPD_SOURCES += hynix_dimm_H5ANAG6NCMR-VKC # 0b11001 +SPD_SOURCES += samsung_dimm_K4A8G165WC-BCTD # 0b10011 +SPD_SOURCES += samsung_dimm_K4AAG165WB-MCTD # 0b11011 bootblock-y += gpio.c ramstage-y += gpio.c diff --git a/src/mainboard/google/drallion/variants/drallion/memory.c b/src/mainboard/google/drallion/variants/drallion/memory.c index e1755b4..67f4e56 100644 --- a/src/mainboard/google/drallion/variants/drallion/memory.c +++ b/src/mainboard/google/drallion/variants/drallion/memory.c @@ -17,6 +17,14 @@ #include <gpio.h> #include <variant/gpio.h> +/* Use spd_index array to save mem_id */ +static const int spd_index[32] = { + 0,0,0,0,0,0,0,0, + 0,0,0,0,0,0,0,0, + 4,3,6,1,0,0,0,0, + 5,0,7,2,0,0,0,0, + }; + int variant_memory_sku(void) { gpio_t spd_gpios[] = { @@ -27,5 +35,5 @@ GPIO_MEM_CONFIG_4, }; - return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); + return spd_index[gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios))]; } -- To view, visit https://review.coreboot.org/c/coreboot/+/35346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2f7e75fdbca4183bcd730e40fef4bfe280ab900b Gerrit-Change-Number: 35346 Gerrit-PatchSet: 1 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit September 2019