coreboot-gerrit September 2019

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Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Rizwan Qureshi (Code Review) 19 Sep '19

19 Sep '19

Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... Patch Set 48: (2 comments) https://review.coreboot.org/c/coreboot/+/27369/47/Documentation/soc/intel/u… File Documentation/soc/intel/ucode_update/microcode_update_model.md: https://review.coreboot.org/c/coreboot/+/27369/47/Documentation/soc/intel/u… PS47, Line 1: # Microcode update mechanism for devices in field > The limitations should also be documented. […] Agreed, have added a comment in the commit message and also captured a "Note" in documentation. https://review.coreboot.org/c/coreboot/+/27369/47/src/soc/intel/common/base… File src/soc/intel/common/basecode/fw_update/ucode_update.c: https://review.coreboot.org/c/coreboot/+/27369/47/src/soc/intel/common/base… PS47, Line 144: intel_microcode_find > This will result in a pointer to the microcode needed for the particular CPU you are using. […] Agreed, have added a comment in the commit message and also captured it documentation. -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 48 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Comment-Date: Thu, 19 Sep 2019 18:41:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Rizwan Qureshi (Code Review) 19 Sep '19

19 Sep '19

Hello Patrick Rudolph, Aaron Durbin, dhaval v sharma, Subrata Banik, Patrick Rudolph, Paul Menzel, Duncan Laurie, build bot (Jenkins), Patrick Georgi, Furquan Shaikh, Varshit B Pandya, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/27369 to look at the new patch set (#48). Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... soc/intel/basecode: Add support for updating ucode loaded via FIT Intel’s FIT (Firmware Interface Table) based MCU (microcode/pcode patch) loading mechanism patches the microcode before CPU reset. In the current Chromebooks field updatable FW has to be first verified by vboot. Since the MCU is loaded before reset vboot cannot verify the same and hence we end up restricting FIT based MCU update only from RO. This patch implements a scheme which will allow chromebooks to update MCU in the field. Create 2 bootblocks (use INTEL_ADD_TOP_SWAP_BOOTBLOCK) each containing their own FIT table. First bootblock FIT has pointers to MCUs (in microcode_blob.bin) which resides in RO section. This is will be used in the recovery scenario. Second bootblock (Normal mode) is identical to the first one except the FIT. Insert an additional pointer to a MCU that will reside in a staging area. Use the CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG config to insert the address of the staging area into FIT. Top swap control bit in RTC BUC register (0x3414) is used to switch between the two bootblocks. Reserve a region in the FMAP which is equal to or greater than the MCU size specified in the BWG for a particular SoC (e.g., for Skylake/Kaby Lake it is 192K). This is a RW region just like the RW_MRC_CACHE. MCU from RW-A/RW-B will be copied to this region during boot. Protect this staging area with a FPR. Basic update flow: In non-recovery mode, Once a slot has been selected and loaded, check if the current slot MCU and RW staging MCU are same. If not, update the staging area with the MCU found in the current slot and reset the system. Also, make sure that the top-swap is enabled in normal/developer mode and disabled in recovery mode. In order to enable the update feature: * The mainboard chromeos.fmd should include a new region for staging MCU e.g, RW_UCODE_STAGED. * Select config TOP_SWAP_BASED_VBOOT_UCODE_UPDATE. * Implement a call to check_and_update_ucode() and handle the failure appropriately. Add documentation to describing the MCU update procedure. TODO: Since this update mechanism is dealing mostly with a single MCU it is best suited for systems where the CPU is soldered down and not replaceable (socketed). Extend the update mechanism to systems where the CPU is replaceable, by including multiple MCU for different CPUs. TEST=Create an FW image for soraka and flash, create a chromeos-firmwareupdate shellball with a newer MCU and perform an update. Make sue that the currently loaded microcode version matches the one in firmwareupdate. Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: dhaval v sharma <dhaval.v.sharma(a)intel.com> Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> --- M Documentation/soc/intel/index.md A Documentation/soc/intel/ucode_update/flash_layout.svg A Documentation/soc/intel/ucode_update/microcode_update_model.md A src/soc/intel/common/basecode/fw_update/Kconfig A src/soc/intel/common/basecode/fw_update/Makefile.inc A src/soc/intel/common/basecode/fw_update/ucode_update.c A src/soc/intel/common/basecode/include/intelbasecode/ucode_update.h 7 files changed, 648 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/27369/48 -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 48 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/drallion: Add memory init setup for drallion
by Thejaswani Putta (Code Review) 19 Sep '19

19 Sep '19

Thejaswani Putta has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35141 ) Change subject: mb/google/drallion: Add memory init setup for drallion ...................................................................... mb/google/drallion: Add memory init setup for drallion This implementation adds below support 1. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config Signed-off-by: Thejaswani Putta <thejaswani.putta(a)intel.com> Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/drallion/gpio.c M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 4 files changed, 43 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/1 diff --git a/src/mainboard/google/drallion/romstage.c b/src/mainboard/google/drallion/romstage.c index 20eee7f..fc5c7bd 100644 --- a/src/mainboard/google/drallion/romstage.c +++ b/src/mainboard/google/drallion/romstage.c @@ -57,6 +57,11 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { + const struct spd_info spd = { + .spd_by_index = true, + .spd_spec.spd_index = variant_memory_sku(), + }; + wilco_ec_romstage_init(); cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index ff0240c..c20c6ff 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -234,6 +234,11 @@ /* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), /* SIO_SLP_WLAN# */ /* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), /* SIO_SLP_S5# */ /* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), /* PM_LANPHY_EN */ +/* PCH_MEM_STRAP0 */ PAD_CFG_GPI(GPP_F12, NONE, PLTRST), +/* PCH_MEM_STRAP1 */ PAD_CFG_GPI(GPP_F13, NONE, PLTRST), +/* PCH_MEM_STRAP2 */ PAD_CFG_GPI(GPP_F14, NONE, PLTRST), +/* PCH_MEM_STRAP3 */ PAD_CFG_GPI(GPP_F15, NONE, PLTRST), +/* PCH_MEM_STRAP4 */ PAD_CFG_GPI(GPP_F16, NONE, PLTRST), }; /* Early pad configuration in bootblock */ diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h index ca54580..51287d4 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h @@ -25,4 +25,7 @@ /* Return memory SKU for the variant */ int variant_memory_sku(void); -#endif +/* Return board specific memory configuration */ +const struct cnl_mb_cfg *variant_memory_params(void); + +#endif /* VARIANT_H */ diff --git a/src/mainboard/google/drallion/variants/drallion/memory.c b/src/mainboard/google/drallion/variants/drallion/memory.c index 2a1d8d9..25cab04 100644 --- a/src/mainboard/google/drallion/variants/drallion/memory.c +++ b/src/mainboard/google/drallion/variants/drallion/memory.c @@ -17,6 +17,35 @@ #include <gpio.h> #include <variant/gpio.h> +static const struct cnl_mb_cfg baseboard_memcfg = { + /* + * The dqs_map arrays map the ddr4 pins to the SoC pins + * for both channels. + * + * the index = pin number on ddr4 part + * the value = pin number on SoC + */ + .dqs_map[DDR_CH0] = { 0, 1, 4, 5, 2, 3, 6, 7 }, + .dqs_map[DDR_CH1] = { 0, 1, 4, 5, 2, 3, 6, 7 }, + + /* Baseboard uses 120, 81 and 100 rcomp resistors */ + .rcomp_resistor = { 120, 81, 100 }, + + /* Baseboard Rcomp target values */ + .rcomp_targets = { 100, 40, 20, 20, 26 }, + + /* Set CaVref config to 2 */ + .vref_ca_config = 2, + + /* Enable Early Command Training */ + .ect = 1, +}; + +const struct cnl_mb_cfg *__weak variant_memory_params(void) +{ + return &baseboard_memcfg; +} + int variant_memory_sku(void) { gpio_t spd_gpios[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/35141 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 Gerrit-Change-Number: 35141 Gerrit-PatchSet: 1 Gerrit-Owner: Thejaswani Putta <thejaswani.putta(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: device/i2c_bus: Add i2c_dev_read_at16()
by Nico Huber (Code Review) 19 Sep '19

19 Sep '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29478 ) Change subject: device/i2c_bus: Add i2c_dev_read_at16() ...................................................................... Patch Set 9: (2 comments) https://review.coreboot.org/c/coreboot/+/29478/8//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/29478/8//COMMIT_MSG@10 PS8, Line 10: chip (for larger EEPROM parts). > not true (anymore?) Done https://review.coreboot.org/c/coreboot/+/29478/8/src/include/device/i2c_bus… File src/include/device/i2c_bus.h: https://review.coreboot.org/c/coreboot/+/29478/8/src/include/device/i2c_bus… PS8, Line 99: uint8_t *buf, size_t len, uint16_t off); > Not sure how it happened, but this signature, the function name and the […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/29478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7516f3e5d9aca362c2b340aa5627d91510c09412 Gerrit-Change-Number: 29478 Gerrit-PatchSet: 9 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 19 Sep 2019 14:23:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: device/i2c_bus: Add i2c_dev_read_at16()
by build bot (Jenkins) (Code Review) 19 Sep '19

19 Sep '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29478 ) Change subject: device/i2c_bus: Add i2c_dev_read_at16() ...................................................................... Patch Set 9: (1 comment) https://review.coreboot.org/c/coreboot/+/29478/9/src/include/device/i2c_bus… File src/include/device/i2c_bus.h: https://review.coreboot.org/c/coreboot/+/29478/9/src/include/device/i2c_bus… PS9, Line 98: int i2c_dev_read_at16(struct device *, uint8_t *buf, size_t len, uint16_t off); function definition argument 'struct device *' should also have an identifier name -- To view, visit https://review.coreboot.org/c/coreboot/+/29478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7516f3e5d9aca362c2b340aa5627d91510c09412 Gerrit-Change-Number: 29478 Gerrit-PatchSet: 9 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 19 Sep 2019 14:22:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: device/i2c_bus: Add i2c_dev_read_at16()
by Nico Huber (Code Review) 19 Sep '19

19 Sep '19

Hello Kyösti Mälkki, Arthur Heymans, Paul Menzel, Thomas Heijligen, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29478 to look at the new patch set (#9). Change subject: device/i2c_bus: Add i2c_dev_read_at16() ...................................................................... device/i2c_bus: Add i2c_dev_read_at16() i2c_dev_read_at16() sends a 16-bit offset to the I2C chip (for larger EEPROM parts), then reads bytes up to a given length into a buffer. Change-Id: I7516f3e5d9aca362c2b340aa5627d91510c09412 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/device/i2c_bus.c M src/include/device/i2c_bus.h 2 files changed, 45 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/29478/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/29478 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7516f3e5d9aca362c2b340aa5627d91510c09412 Gerrit-Change-Number: 29478 Gerrit-PatchSet: 9 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Revert "soc/intel/cannonlake: Add option to select FSP_CAR"
by Nico Huber (Code Review) 19 Sep '19

19 Sep '19

Hello Kyösti Mälkki, Werner Zeh, David Hendricks, Aaron Durbin, Angel Pons, Arthur Heymans, Patrick Rudolph, Stefan Reinauer, Philip Prindeville, Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34282 to review the following change. Change subject: Revert "soc/intel/cannonlake: Add option to select FSP_CAR" ...................................................................... Revert "soc/intel/cannonlake: Add option to select FSP_CAR" This reverts commit 9e3ba212f34c6d9f2eb7dac8e4651f8ce12ab0c0. It rudely changed the default CAR implementation from open-source to the proprietary FSP-T. That it was reviewed by Google and contains a safeguard so that it doesn't affect Google reeks of corporate arrogance. My attempts to find a civilized solution failed, because the author is blocking any progress. Change-Id: Ief7b85a9988d1a3f4a4639e9fd304959295958bd --- M src/soc/intel/cannonlake/Kconfig 1 file changed, 2 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/34282/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index fed7f02..f30ff11 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -68,6 +68,7 @@ select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE + select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC @@ -86,6 +87,7 @@ select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT @@ -267,33 +269,6 @@ This will enable a workaround in ASL _PS3 and _PS0 methods to force SD_PWR_ENABLE to stay low in D3. -choice - prompt "Cache-as-ram implementation" - default USE_CANNONLAKE_CAR_NEM_ENHANCED if MAINBOARD_HAS_CHROMEOS - default USE_CANNONLAKE_FSP_CAR - help - This option allows you to select how cache-as-ram (CAR) is set up. - -config USE_CANNONLAKE_CAR_NEM_ENHANCED - bool "Enhanced Non-evict mode" - select SOC_INTEL_COMMON_BLOCK_CAR - select INTEL_CAR_NEM_ENHANCED - help - A current limitation of NEM (Non-Evict mode) is that code and data - sizes are derived from the requirement to not write out any modified - cache line. With NEM, if there is no physical memory behind the - cached area, the modified data will be lost and NEM results will be - inconsistent. ENHANCED NEM guarantees that modified data is always - kept in cache while clean data is replaced. - -config USE_CANNONLAKE_FSP_CAR - bool "Use FSP CAR" - select FSP_CAR - help - Use FSP APIs to initialize and tear down the Cache-As-Ram. - -endchoice - config FSP_HEADER_PATH string "Location of FSP headers" default "3rdparty/fsp/CoffeeLakeFspBinPkg/Include/" if SOC_INTEL_COFFEELAKE || SOC_INTEL_WHISKEYLAKE -- To view, visit https://review.coreboot.org/c/coreboot/+/34282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief7b85a9988d1a3f4a4639e9fd304959295958bd Gerrit-Change-Number: 34282 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philip Prindeville <philipp(a)redfish-solutions.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/glados: Fix false coverity alarms
by Nico Huber (Code Review) 19 Sep '19

19 Sep '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32741 Change subject: mb/google/glados: Fix false coverity alarms ...................................................................... mb/google/glados: Fix false coverity alarms Coverity doesn't like the filling of adjacent arrays with a single memcpy(). The structure of the FSP headers doesn't allow us to loop over them either. As simply replicating the memcpy() calls doesn't make the code any more readable, use the new memcpy_elen() and memcpy_dlen() macros. CID=1401338..1401340, 1401342..1401343 Change-Id: Ie1419381f812b0ba0563163139a8cf0d0599e492 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/google/glados/variants/asuka/variant.c M src/mainboard/google/glados/variants/caroline/variant.c M src/mainboard/google/glados/variants/cave/variant.c M src/mainboard/google/glados/variants/chell/variant.c M src/mainboard/google/glados/variants/glados/variant.c M src/mainboard/google/glados/variants/lars/variant.c M src/mainboard/google/glados/variants/sentry/variant.c 7 files changed, 50 insertions(+), 64 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/32741/1 diff --git a/src/mainboard/google/glados/variants/asuka/variant.c b/src/mainboard/google/glados/variants/asuka/variant.c index 4c77897..1800470a 100644 --- a/src/mainboard/google/glados/variants/asuka/variant.c +++ b/src/mainboard/google/glados/variants/asuka/variant.c @@ -15,9 +15,9 @@ */ #include <stdint.h> -#include <string.h> #include <baseboard/variant.h> #include <fsp/soc_binding.h> +#include <lib.h> void variant_memory_init_params( MEMORY_INIT_UPD *const memory_params, const int spd_index) @@ -39,14 +39,12 @@ /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(memory_params->DqByteMapCh0, dq_map, - sizeof(memory_params->DqByteMapCh0) * 2); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, - sizeof(memory_params->DqsMapCpu2DramCh0) * 2); - memcpy(memory_params->RcompResistor, RcompResistor, - sizeof(memory_params->RcompResistor)); - memcpy(memory_params->RcompTarget, RcompTarget, - sizeof(memory_params->RcompTarget)); + memcpy_elen(memory_params->DqByteMapCh0, dq_map[0]); + memcpy_elen(memory_params->DqByteMapCh1, dq_map[1]); + memcpy_elen(memory_params->DqsMapCpu2DramCh0, dqs_map[0]); + memcpy_elen(memory_params->DqsMapCpu2DramCh1, dqs_map[1]); + memcpy_elen(memory_params->RcompResistor, RcompResistor); + memcpy_elen(memory_params->RcompTarget, RcompTarget); } int is_dual_channel(const int spd_index) diff --git a/src/mainboard/google/glados/variants/caroline/variant.c b/src/mainboard/google/glados/variants/caroline/variant.c index d61a538..0fa7ee4 100644 --- a/src/mainboard/google/glados/variants/caroline/variant.c +++ b/src/mainboard/google/glados/variants/caroline/variant.c @@ -17,8 +17,8 @@ #include <baseboard/variant.h> #include <fsp/soc_binding.h> #include <gpio.h> +#include <lib.h> #include <stdint.h> -#include <string.h> #include <variant/gpio.h> void variant_memory_init_params( @@ -41,14 +41,12 @@ /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(memory_params->DqByteMapCh0, dq_map, - sizeof(memory_params->DqByteMapCh0) * 2); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, - sizeof(memory_params->DqsMapCpu2DramCh0) * 2); - memcpy(memory_params->RcompResistor, RcompResistor, - sizeof(memory_params->RcompResistor)); - memcpy(memory_params->RcompTarget, RcompTarget, - sizeof(memory_params->RcompTarget)); + memcpy_elen(memory_params->DqByteMapCh0, dq_map[0]); + memcpy_elen(memory_params->DqByteMapCh1, dq_map[1]); + memcpy_elen(memory_params->DqsMapCpu2DramCh0, dqs_map[0]); + memcpy_elen(memory_params->DqsMapCpu2DramCh1, dqs_map[1]); + memcpy_elen(memory_params->RcompResistor, RcompResistor); + memcpy_elen(memory_params->RcompTarget, RcompTarget); memory_params->DdrFreqLimit = 1600; } diff --git a/src/mainboard/google/glados/variants/cave/variant.c b/src/mainboard/google/glados/variants/cave/variant.c index fc27fb4..4c0f8fa 100644 --- a/src/mainboard/google/glados/variants/cave/variant.c +++ b/src/mainboard/google/glados/variants/cave/variant.c @@ -17,8 +17,8 @@ #include <baseboard/variant.h> #include <fsp/soc_binding.h> #include <gpio.h> +#include <lib.h> #include <stdint.h> -#include <string.h> #include <variant/gpio.h> void variant_memory_init_params( @@ -41,14 +41,12 @@ /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(memory_params->DqByteMapCh0, dq_map, - sizeof(memory_params->DqByteMapCh0) * 2); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, - sizeof(memory_params->DqsMapCpu2DramCh0) * 2); - memcpy(memory_params->RcompResistor, RcompResistor, - sizeof(memory_params->RcompResistor)); - memcpy(memory_params->RcompTarget, RcompTarget, - sizeof(memory_params->RcompTarget)); + memcpy_elen(memory_params->DqByteMapCh0, dq_map[0]); + memcpy_elen(memory_params->DqByteMapCh1, dq_map[1]); + memcpy_elen(memory_params->DqsMapCpu2DramCh0, dqs_map[0]); + memcpy_elen(memory_params->DqsMapCpu2DramCh1, dqs_map[1]); + memcpy_elen(memory_params->RcompResistor, RcompResistor); + memcpy_elen(memory_params->RcompTarget, RcompTarget); } void mainboard_gpio_smi_sleep(void) diff --git a/src/mainboard/google/glados/variants/chell/variant.c b/src/mainboard/google/glados/variants/chell/variant.c index 2d1b363..7b29137 100644 --- a/src/mainboard/google/glados/variants/chell/variant.c +++ b/src/mainboard/google/glados/variants/chell/variant.c @@ -17,8 +17,8 @@ #include <baseboard/variant.h> #include <fsp/soc_binding.h> #include <gpio.h> +#include <lib.h> #include <stdint.h> -#include <string.h> #include <variant/gpio.h> void variant_memory_init_params( @@ -41,14 +41,12 @@ /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(memory_params->DqByteMapCh0, dq_map, - sizeof(memory_params->DqByteMapCh0) * 2); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, - sizeof(memory_params->DqsMapCpu2DramCh0) * 2); - memcpy(memory_params->RcompResistor, RcompResistor, - sizeof(memory_params->RcompResistor)); - memcpy(memory_params->RcompTarget, RcompTarget, - sizeof(memory_params->RcompTarget)); + memcpy_elen(memory_params->DqByteMapCh0, dq_map[0]); + memcpy_elen(memory_params->DqByteMapCh1, dq_map[1]); + memcpy_elen(memory_params->DqsMapCpu2DramCh0, dqs_map[0]); + memcpy_elen(memory_params->DqsMapCpu2DramCh1, dqs_map[1]); + memcpy_elen(memory_params->RcompResistor, RcompResistor); + memcpy_elen(memory_params->RcompTarget, RcompTarget); } void mainboard_gpio_smi_sleep(void) diff --git a/src/mainboard/google/glados/variants/glados/variant.c b/src/mainboard/google/glados/variants/glados/variant.c index fc27fb4..4c0f8fa 100644 --- a/src/mainboard/google/glados/variants/glados/variant.c +++ b/src/mainboard/google/glados/variants/glados/variant.c @@ -17,8 +17,8 @@ #include <baseboard/variant.h> #include <fsp/soc_binding.h> #include <gpio.h> +#include <lib.h> #include <stdint.h> -#include <string.h> #include <variant/gpio.h> void variant_memory_init_params( @@ -41,14 +41,12 @@ /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(memory_params->DqByteMapCh0, dq_map, - sizeof(memory_params->DqByteMapCh0) * 2); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, - sizeof(memory_params->DqsMapCpu2DramCh0) * 2); - memcpy(memory_params->RcompResistor, RcompResistor, - sizeof(memory_params->RcompResistor)); - memcpy(memory_params->RcompTarget, RcompTarget, - sizeof(memory_params->RcompTarget)); + memcpy_elen(memory_params->DqByteMapCh0, dq_map[0]); + memcpy_elen(memory_params->DqByteMapCh1, dq_map[1]); + memcpy_elen(memory_params->DqsMapCpu2DramCh0, dqs_map[0]); + memcpy_elen(memory_params->DqsMapCpu2DramCh1, dqs_map[1]); + memcpy_elen(memory_params->RcompResistor, RcompResistor); + memcpy_elen(memory_params->RcompTarget, RcompTarget); } void mainboard_gpio_smi_sleep(void) diff --git a/src/mainboard/google/glados/variants/lars/variant.c b/src/mainboard/google/glados/variants/lars/variant.c index cff0096..e3edd29 100644 --- a/src/mainboard/google/glados/variants/lars/variant.c +++ b/src/mainboard/google/glados/variants/lars/variant.c @@ -15,9 +15,9 @@ */ #include <stdint.h> -#include <string.h> #include <baseboard/variant.h> #include <fsp/soc_binding.h> +#include <lib.h> #define K4E6E304EB_MEM_ID 0x5 @@ -29,7 +29,7 @@ #define MEM_SINGLE_CHANC 0xc void variant_memory_init_params( - MEMORY_INIT_UPD *const params, const int spd_index) + MEMORY_INIT_UPD *const memory_params, const int spd_index) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -58,14 +58,12 @@ if (spd_index == K4E6E304EB_MEM_ID) targeted_rcomp = StrengthendRcompTarget; - memcpy(params->DqByteMapCh0, dq_map, - sizeof(params->DqByteMapCh0) * 2); - memcpy(params->DqsMapCpu2DramCh0, dqs_map, - sizeof(params->DqsMapCpu2DramCh0) * 2); - memcpy(params->RcompResistor, RcompResistor, - sizeof(params->RcompResistor)); - memcpy(params->RcompTarget, targeted_rcomp, - sizeof(params->RcompTarget)); + memcpy_elen(memory_params->DqByteMapCh0, dq_map[0]); + memcpy_elen(memory_params->DqByteMapCh1, dq_map[1]); + memcpy_elen(memory_params->DqsMapCpu2DramCh0, dqs_map[0]); + memcpy_elen(memory_params->DqsMapCpu2DramCh1, dqs_map[1]); + memcpy_elen(memory_params->RcompResistor, RcompResistor); + memcpy_dlen(memory_params->RcompTarget, targeted_rcomp); } int is_dual_channel(const int spd_index) diff --git a/src/mainboard/google/glados/variants/sentry/variant.c b/src/mainboard/google/glados/variants/sentry/variant.c index 4c7fa23..e73aa3c 100644 --- a/src/mainboard/google/glados/variants/sentry/variant.c +++ b/src/mainboard/google/glados/variants/sentry/variant.c @@ -15,9 +15,9 @@ */ #include <stdint.h> -#include <string.h> #include <baseboard/variant.h> #include <fsp/soc_binding.h> +#include <lib.h> #define K4E6E304EE_MEM_ID 0x3 @@ -51,12 +51,10 @@ if (spd_index == K4E6E304EE_MEM_ID) targeted_rcomp = StrengthendRcompTarget; - memcpy(memory_params->DqByteMapCh0, dq_map, - sizeof(memory_params->DqByteMapCh0) * 2); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, - sizeof(memory_params->DqsMapCpu2DramCh0) * 2); - memcpy(memory_params->RcompResistor, RcompResistor, - sizeof(memory_params->RcompResistor)); - memcpy(memory_params->RcompTarget, targeted_rcomp, - sizeof(memory_params->RcompTarget)); + memcpy_elen(memory_params->DqByteMapCh0, dq_map[0]); + memcpy_elen(memory_params->DqByteMapCh1, dq_map[1]); + memcpy_elen(memory_params->DqsMapCpu2DramCh0, dqs_map[0]); + memcpy_elen(memory_params->DqsMapCpu2DramCh1, dqs_map[1]); + memcpy_elen(memory_params->RcompResistor, RcompResistor); + memcpy_dlen(memory_params->RcompTarget, targeted_rcomp); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32741 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie1419381f812b0ba0563163139a8cf0d0599e492 Gerrit-Change-Number: 32741 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/intel/{kunimitsu,saddlebrook}: Fix false coverity alarms
by Nico Huber (Code Review) 19 Sep '19

19 Sep '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32742 Change subject: mb/intel/{kunimitsu,saddlebrook}: Fix false coverity alarms ...................................................................... mb/intel/{kunimitsu,saddlebrook}: Fix false coverity alarms Coverity doesn't like the filling of adjacent arrays with a single memcpy(). The structure of the FSP headers doesn't allow us to loop over them either. In case of Kunimitsu we also can't have a better typed solution because of the FSP1.1/FSP2.0 dual port. Just replicating the functions per channel is probably the best we can do. CID=1401341, 1401344 Change-Id: I36a141bc00664ccd29d625ac88e76073086a5074 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/mainboard/intel/kunimitsu/romstage.c M src/mainboard/intel/kunimitsu/romstage_fsp20.c M src/mainboard/intel/kunimitsu/spd/spd.h M src/mainboard/intel/kunimitsu/spd/spd_util.c M src/mainboard/intel/saddlebrook/romstage.c M src/mainboard/intel/saddlebrook/spd/spd.h M src/mainboard/intel/saddlebrook/spd/spd_util.c 7 files changed, 60 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32742/1 diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c index f25f88b..1a474da 100644 --- a/src/mainboard/intel/kunimitsu/romstage.c +++ b/src/mainboard/intel/kunimitsu/romstage.c @@ -30,8 +30,10 @@ MEMORY_INIT_UPD *memory_params) { spd_memory_init_params(memory_params); - mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0); - mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0); + mainboard_fill_dq_map_data0(&memory_params->DqByteMapCh0); + mainboard_fill_dq_map_data1(&memory_params->DqByteMapCh1); + mainboard_fill_dqs_map_data0(&memory_params->DqsMapCpu2DramCh0); + mainboard_fill_dqs_map_data1(&memory_params->DqsMapCpu2DramCh1); mainboard_fill_rcomp_res_data(&memory_params->RcompResistor); mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget); memory_params->MemorySpdDataLen = SPD_LEN; diff --git a/src/mainboard/intel/kunimitsu/romstage_fsp20.c b/src/mainboard/intel/kunimitsu/romstage_fsp20.c index ee1ddd5..10992f0 100644 --- a/src/mainboard/intel/kunimitsu/romstage_fsp20.c +++ b/src/mainboard/intel/kunimitsu/romstage_fsp20.c @@ -26,8 +26,10 @@ FSP_M_CONFIG *mem_cfg; mem_cfg = &mupd->FspmConfig; - mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); - mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_dq_map_data0(&mem_cfg->DqByteMapCh0); + mainboard_fill_dq_map_data1(&mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_data0(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_dqs_map_data1(&mem_cfg->DqsMapCpu2DramCh1); mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); diff --git a/src/mainboard/intel/kunimitsu/spd/spd.h b/src/mainboard/intel/kunimitsu/spd/spd.h index 22d371f..e8b42ee 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd.h +++ b/src/mainboard/intel/kunimitsu/spd/spd.h @@ -55,8 +55,10 @@ return (gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios))); } void spd_memory_init_params(MEMORY_INIT_UPD *memory_params); -void mainboard_fill_dq_map_data(void *dq_map_ptr); -void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_dq_map_data0(void *dq_map_ptr); +void mainboard_fill_dq_map_data1(void *dq_map_ptr); +void mainboard_fill_dqs_map_data0(void *dqs_map_ptr); +void mainboard_fill_dqs_map_data1(void *dqs_map_ptr); void mainboard_fill_rcomp_res_data(void *rcomp_ptr); void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); uintptr_t mainboard_get_spd_data(void); diff --git a/src/mainboard/intel/kunimitsu/spd/spd_util.c b/src/mainboard/intel/kunimitsu/spd/spd_util.c index b173628..6dcc92d 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd_util.c +++ b/src/mainboard/intel/kunimitsu/spd/spd_util.c @@ -20,23 +20,33 @@ #include "boardid.h" #include "spd.h" -void mainboard_fill_dq_map_data(void *dq_map_ptr) +void mainboard_fill_dq_map_data0(void *dq_map_ptr) { /* DQ byte map */ - const u8 dq_map[2][12] = { - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, - 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, - 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + const u8 dq_map[12] = { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }; memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); } -void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +void mainboard_fill_dq_map_data1(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[12] = { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dqs_map_data0(void *dqs_map_ptr) { /* DQS CPU<>DRAM map */ - const u8 dqs_map[2][8] = { - { 0, 1, 3, 2, 6, 5, 4, 7 }, - { 2, 3, 0, 1, 6, 7, 4, 5 } }; + const u8 dqs_map[8] = { 0, 1, 3, 2, 6, 5, 4, 7 }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +void mainboard_fill_dqs_map_data1(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[8] = { 2, 3, 0, 1, 6, 7, 4, 5 }; memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); } diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c index 48d39db..7b2687f 100644 --- a/src/mainboard/intel/saddlebrook/romstage.c +++ b/src/mainboard/intel/saddlebrook/romstage.c @@ -63,8 +63,10 @@ * should be set in the FSP flash image and should not need to be * changed. */ - mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0); - mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0); + mainboard_fill_dq_map_data0(&memory_params->DqByteMapCh0); + mainboard_fill_dq_map_data1(&memory_params->DqByteMapCh1); + mainboard_fill_dqs_map_data0(&memory_params->DqsMapCpu2DramCh0); + mainboard_fill_dqs_map_data1(&memory_params->DqsMapCpu2DramCh1); mainboard_fill_rcomp_res_data(&memory_params->RcompResistor); mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget); diff --git a/src/mainboard/intel/saddlebrook/spd/spd.h b/src/mainboard/intel/saddlebrook/spd/spd.h index a5f1af3..47587ed 100644 --- a/src/mainboard/intel/saddlebrook/spd/spd.h +++ b/src/mainboard/intel/saddlebrook/spd/spd.h @@ -19,8 +19,10 @@ #define RCOMP_TARGET_PARAMS 0x5 -void mainboard_fill_dq_map_data(void *dq_map_ptr); -void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_dq_map_data0(void *dq_map_ptr); +void mainboard_fill_dq_map_data1(void *dq_map_ptr); +void mainboard_fill_dqs_map_data0(void *dqs_map_ptr); +void mainboard_fill_dqs_map_data1(void *dqs_map_ptr); void mainboard_fill_rcomp_res_data(void *rcomp_ptr); void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); diff --git a/src/mainboard/intel/saddlebrook/spd/spd_util.c b/src/mainboard/intel/saddlebrook/spd/spd_util.c index 5055d9a..7f27c31 100644 --- a/src/mainboard/intel/saddlebrook/spd/spd_util.c +++ b/src/mainboard/intel/saddlebrook/spd/spd_util.c @@ -17,23 +17,33 @@ #include <string.h> #include "spd.h" -void mainboard_fill_dq_map_data(void *dq_map_ptr) +void mainboard_fill_dq_map_data0(void *dq_map_ptr) { /* DQ byte map */ - const u8 dq_map[2][12] = { - { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, - 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, - { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, - 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + const u8 dq_map[12] = { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }; memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); } -void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +void mainboard_fill_dq_map_data1(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[12] = { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dqs_map_data0(void *dqs_map_ptr) { /* DQS CPU<>DRAM map */ - const u8 dqs_map[2][8] = { - { 0, 1, 3, 2, 4, 5, 6, 7 }, - { 1, 0, 4, 5, 2, 3, 6, 7 } }; + const u8 dqs_map[8] = { 0, 1, 3, 2, 4, 5, 6, 7 }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +void mainboard_fill_dqs_map_data1(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[8] = { 1, 0, 4, 5, 2, 3, 6, 7 }; memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36a141bc00664ccd29d625ac88e76073086a5074 Gerrit-Change-Number: 32742 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: x86/smbios: Untangle system and board tables
by Nico Huber (Code Review) 19 Sep '19

19 Sep '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29477 ) Change subject: x86/smbios: Untangle system and board tables ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/c/coreboot/+/29477/8/src/drivers/i2c/at24rf08c/… File src/drivers/i2c/at24rf08c/Kconfig: https://review.coreboot.org/c/coreboot/+/29477/8/src/drivers/i2c/at24rf08c/… PS8, Line 1: DRIVERS_I2C_AT24RF08C > Seems unneeded and incomplete (I never updated the […] Hah, turned out that it is needed after all. Without this change, SMBIOS_PROVIDED_BY_MOBO can't be selected by other boards because it depends on VENDOR_LENOVO. -- To view, visit https://review.coreboot.org/c/coreboot/+/29477 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c9c95a1307529c3137647a161a698a4c3daa0ae Gerrit-Change-Number: 29477 Gerrit-PatchSet: 10 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Thu, 19 Sep 2019 12:04:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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coreboot-gerrit September 2019