coreboot-gerrit September 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: util/lint: make clang-format non-fatal
by Angel Pons (Code Review) 19 Sep '19

19 Sep '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35176 ) Change subject: util/lint: make clang-format non-fatal ...................................................................... util/lint: make clang-format non-fatal The current clang-format configuration is completely broken. It forces one to change the code style of patches before pushing them, only to find out that checkpatch now complains about it. This means newcomers get scared away, and developers only get angered and frustrated about it, and end up working around clang-format's requirements anyway. For now, make clang-format's complaints non-fatal, reducing them to text noise. However, since clang-format is currently unusable, reverting it out would be preferred. Change-Id: Iffa8934efa1c27c04e10545f66d8f9976e74c367 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/skylake/chip_fsp20.c M util/lint/check-style M util/lint/lint-stable-022-clang-format 3 files changed, 3 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/35176/1 diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 064f71e..bfd9480 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -127,8 +127,7 @@ * Found the first enabled device in * a given dev number. */ - printk(BIOS_INFO, "PCI func %d was swapped" - " to func 0.\n", i); + printk(BIOS_INFO, "PCI func %d was swapped to func 0.\n", i); func0->path.pci.devfn = dev->path.pci.devfn; dev->path.pci.devfn = devfn0; break; diff --git a/util/lint/check-style b/util/lint/check-style index 2237ed6..a0679d8 100755 --- a/util/lint/check-style +++ b/util/lint/check-style @@ -140,4 +140,4 @@ printf "Aborting commit. Apply changes and commit again or skip checking with" printf " --no-verify (not recommended).\n" -exit 1 +exit 0 diff --git a/util/lint/lint-stable-022-clang-format b/util/lint/lint-stable-022-clang-format index bd662e4..48f51a8 100755 --- a/util/lint/lint-stable-022-clang-format +++ b/util/lint/lint-stable-022-clang-format @@ -33,6 +33,6 @@ if [ "$(git diff --no-prefix HEAD~..HEAD -- $files_to_check | clang-format-diff)" != "" ]; then echo "Coding style mismatch. The following patch fixes it:" git diff --no-prefix HEAD~..HEAD -- $files_to_check | clang-format-diff - exit 1 + exit 0 fi fi -- To view, visit https://review.coreboot.org/c/coreboot/+/35176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffa8934efa1c27c04e10545f66d8f9976e74c367 Gerrit-Change-Number: 35176 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard/lenovo/t410: Add new port
by Arthur Heymans (Code Review) 19 Sep '19

19 Sep '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/11791 ) Change subject: mainboard/lenovo/t410: Add new port ...................................................................... Patch Set 21: (4 comments) A few nits, but looks good. https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/Kconfig: https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410… PS21, Line 63: default 4 > I think this should be 8 Clarckfield CPU's (quadcore) are supported by the current code. It could be a just a matter of adding the CPUID to the ramstage cpu code, or it could be the raminit does not work on it... No wrongdoing in putting 8 here though. https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/romstage.c: https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410… PS21, Line 54: : pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); : pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); : pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x1c1681); : pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, (0x68 & ~3) | 0x00040001); Any idea if you need those during romstage as there is ramstage code to set those up based on dt (could be placed in romstage like on bd82x6x) https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410… File src/mainboard/lenovo/t410/vboot-rwa.fmd: https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410… PS21, Line 10: 0x16ffc0 I think you can drop this. It should fill the remaining space. https://review.coreboot.org/c/coreboot/+/11791/21/src/mainboard/lenovo/t410… PS21, Line 27: 0xff000 same -- To view, visit https://review.coreboot.org/c/coreboot/+/11791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Gerrit-Change-Number: 11791 Gerrit-PatchSet: 21 Gerrit-Owner: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eloy Degen Gerrit-CC: Matt Parnell <mparnell(a)gmail.com> Gerrit-CC: Okashi Odayakana <okashi(a)okashi.me> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Comment-Date: Thu, 19 Sep 2019 09:57:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Arthur Heymans (Code Review) 19 Sep '19

19 Sep '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... Patch Set 47: (2 comments) https://review.coreboot.org/c/coreboot/+/27369/47/Documentation/soc/intel/u… File Documentation/soc/intel/ucode_update/microcode_update_model.md: https://review.coreboot.org/c/coreboot/+/27369/47/Documentation/soc/intel/u… PS47, Line 1: # Microcode update mechanism for devices in field The limitations should also be documented. Care should be taken on systems with socketed CPU's as replacing the CPU might end up with a non-booting system (if it needs a different MCU). https://review.coreboot.org/c/coreboot/+/27369/47/src/soc/intel/common/base… File src/soc/intel/common/basecode/fw_update/ucode_update.c: https://review.coreboot.org/c/coreboot/+/27369/47/src/soc/intel/common/base… PS47, Line 144: intel_microcode_find This will result in a pointer to the microcode needed for the particular CPU you are using. This will cause problems on systems that have a socketed CPU as you may end up needing a different microcode when swapping CPU's. The proper solution is to have multiple MCU FIT entries point a fixed offsets in that MCU update FMAP, while make sure there is enough place between them (since the sizes of the MCU are variable) -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 47 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Comment-Date: Thu, 19 Sep 2019 09:40:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/ibexpeak: Add define for PRSTS register
by Angel Pons (Code Review) 19 Sep '19

19 Sep '19

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35453 ) Change subject: sb/intel/ibexpeak: Add define for PRSTS register ...................................................................... sb/intel/ibexpeak: Add define for PRSTS register Change-Id: Ia9a6b0c7f2a07796f850acd2349067ba5e5eb735 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/pch.h 2 files changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/35453/1 diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index a6bbe64..3e1f4a4 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -266,10 +266,11 @@ outl(reg32, pmbase + 0x04); /* Clear magic status bits to prevent unexpected wake */ - reg32 = RCBA32(0x3310); - reg32 |= (1 << 4)|(1 << 5)|(1 << 0); - RCBA32(0x3310) = reg32; + reg32 = RCBA32(PRSTS); + reg32 |= (1 << 5) | (1 << 4) | (1 << 0); + RCBA32(PRSTS) = reg32; + /* FIXME: Does this even exist? */ reg32 = RCBA32(0x3f02); reg32 &= ~0xf; RCBA32(0x3f02) = reg32; diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index ee0f9ad..e7cc9d2 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -352,6 +352,8 @@ #define SOFT_RESET_CTRL 0x38f4 #define SOFT_RESET_DATA 0x38f8 +#define PRSTS 0x3310 + #define DIR_ROUTE(x,a,b,c,d) \ RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \ ((b) << DIR_IBR) | ((a) << DIR_IAR)) -- To view, visit https://review.coreboot.org/c/coreboot/+/35453 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9a6b0c7f2a07796f850acd2349067ba5e5eb735 Gerrit-Change-Number: 35453 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: hatch: automate creating a new variant in coreboot
by Paul Fagerburg (Code Review) 19 Sep '19

19 Sep '19

Paul Fagerburg has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35239 ) Change subject: hatch: automate creating a new variant in coreboot ...................................................................... hatch: automate creating a new variant in coreboot To create a new variant of the hatch baseboard, we need to add the variant's GBB_HWID and other information to Kconfig and Kconfig.name, and set up a skeletal build based on the hatch baseboard. BUG=b:140261109 BRANCH=none TEST=``./create_coreboot_variant.sh sushi && git show`` Kconfig will have three new lines for the SUSHI variant, and Kconfig.name will have an entirely new section. New files created are: variants/sushi/Makefile.inc variants/sushi/overridetree.cb variants/sushi/include/ec.h variants/sushi/include/gpio.h variants/sushi/include/variant/acpi/dptf.asl Also run the script with an existing board name to verify that you can't create a variant that already exists. Change-Id: I1a5b9c8735faafebb2e4e384cb3346867d64c556 Signed-off-by: Paul Fagerburg <pfagerburg(a)chromium.org> --- A src/mainboard/google/hatch/scripts/create_coreboot_variant.sh A src/mainboard/google/hatch/scripts/kconfig.py 2 files changed, 303 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/35239/1 diff --git a/src/mainboard/google/hatch/scripts/create_coreboot_variant.sh b/src/mainboard/google/hatch/scripts/create_coreboot_variant.sh new file mode 100755 index 0000000..d172045 --- /dev/null +++ b/src/mainboard/google/hatch/scripts/create_coreboot_variant.sh @@ -0,0 +1,150 @@ +#!/bin/bash +name=`git config --global --get user.name` +email=`git config --global --get user.email` + +if [ "$#" -ne 1 ]; then + echo "Usage: $0 variant_name" + echo "e.g. $0 kohaku" + echo "Adds a new variant of Hatch to Kconfig and Kconfig.name, creates the" + echo "skeleton files for acpi, ec, and gpio, copies the makefile for" + echo "SPD sources, and sets up a basic overridetree" + exit 1 +fi + +base="hatch" +variant="$1" +# We will use all uppercase and all lowercase versions of these names +# ${var,,} converts to all lowercase, ${var^^} is all uppercase + +# All of the necessary files are in the parent directory from this script +pushd "${BASH_SOURCE%/*}/.." + +# Make sure the variant doesn't already exist +if [ -e variants/${variant,,} ]; then + echo "variants/${variant,,} aleady exists; have you already created this variant?" + popd + exit 2 +fi + +# Start a branch +repo start ${variant,,} + +mkdir -p variants/${variant,,}/include/variant/acpi + +echo <<EOF >variants/${variant,,}/include/variant/acpi/dptf.asl +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/dptf.asl> +EOF +git add variants/${variant,,}/include/variant/acpi/dptf.asl + +echo <<EOF >variants/${variant,,}/include/variant/ec.h +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_EC_H +#define VARIANT_EC_H + +#include <baseboard/ec.h> + +#endif +EOF +git add variants/${variant,,}/include/variant/ec.h + +echo <<EOF >variants/${variant,,}/include/variant/gpio.h +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <baseboard/gpio.h> + +#endif +EOF +git add variants/${variant,,}/include/variant/gpio.h + +echo <<EOF >variants/${variant,,}/include/variant/Makefile.inc +## This file is part of the coreboot project. +## +## Copyright 2019 Google LLC +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +SPD_SOURCES = 4G_2400 # 0b000 +SPD_SOURCES += empty_ddr4 # 0b001 +SPD_SOURCES += 8G_2400 # 0b010 +SPD_SOURCES += 8G_2666 # 0b011 +SPD_SOURCES += 16G_2400 # 0b100 +SPD_SOURCES += 16G_2666 # 0b101 +EOF +git add variants/${variant,,}/include/variant/Makefile.inc + +cp variants/${base,,}/overridetree.cb variants/${variant,,} +git add variants/${variant,,}/overridetree.cb + +scripts/kconfig.py --name ${variant} + +mv Kconfig.new Kconfig +mv Kconfig.name.new Kconfig.name + +git add KConfig KConfig.name + +# Now commit the files +git commit -m "${base,,}: Create ${variant,,} variant + +BUG=none +TEST=util/abuild/abuild -p none -t google/${base,,} -x -a +make sure the build includes GOOGLE_{variant^^} + +Signed-off-by: ${name} <${email}>" + +popd + +echo "Please check all the files (git show), make any changes you want," +echo "and then push to coreboot HEAD:refs/for/master" diff --git a/src/mainboard/google/hatch/scripts/kconfig.py b/src/mainboard/google/hatch/scripts/kconfig.py new file mode 100644 index 0000000..5a10a7e --- /dev/null +++ b/src/mainboard/google/hatch/scripts/kconfig.py @@ -0,0 +1,153 @@ +#!/usr/bin/python3 +"""Add a new variant to the EC Kconfig for the baseboard + +To start a new variant of an existing baseboard, we need to add +the variant into the Kconfig and Kconfig.name EC files for the +baseboard. In Kconfig, we have three sections that need additional +entries, GBB_HWID, MAINBOARD_PART_NUMBER, and VARIANT_DIR. + +In GBB_HWID, we need to add a HWID that includes a numeric suffix. +The numeric suffix is the CRC-32 of the all-caps ASCII name, +modulo 10000. +For example, if the board name is "Fizz", we calculate the CRC of +"FIZZ TEST", which is 0x598C492D. In decimal, the value is 1502365997, +modulo 10000 is 5997. So the HWID string is "FIZZ TEST 5997" +In the past, we have used an online CRC-32 calculator such as +https://www.lammertbies.nl/comm/info/crc-calculation.html, and then +used the calculator app to convert to decimal and take the last +4 digits. + +The MAINBOARD_PART_NUMBER and VARIANT_DIR are simpler, just using +various capitalizations of the variant name to create the strings. + +Kconfig.name adds an entire section for the new variant, and all +of these use various capitalizations of the variant name. The strings +in this section are SOC-specific, so we'll need versions for each +SOC that we support. + +Copyright 2019 The Chromium OS Authors. All rights reserved. +Use of this source code is governed by a BSD-style license that can be +found in the LICENSE file. +""" + +import argparse +import zlib + + + +def main(): + parser = argparse.ArgumentParser( + description="Add strings to coreboot Kconfig for a new board variant") + parser.add_argument('--name', type=str, required=True, + help='Name of the board variant') + args = parser.parse_args() + + add_to_Kconfig(args.name) + add_to_Kconfig_name(args.name) + + +def get_gbb_hwid(variant_name): + """Create the GBB_HWID for a variant + + variant_name The name of the board variant, e.g. 'kindred' + + Returns: + GBB_HWID string for the board variant, e.g. 'KOHAKU TEST 1953' + + Note that the case of the variant name does not matter; it gets + converted to all uppercase as part of this function.""" + hwid = variant_name + ' test' + upperhwid = hwid.upper() + suffix = zlib.crc32(upperhwid.encode('UTF-8')) % 10000 + gbb_hwid = upperhwid + ' ' + str(suffix).zfill(4) + return gbb_hwid + + + +def add_to_Kconfig(variant_name): + """Add options for the variant to the Kconfig + + Open the Kconfig file and read it line-by-line. When we detect that we're + in one of the sections of interest, wait until we get a blank line + (signalling the end of that section), and then add our new line before + the blank line. The updated lines are written out to Kconfig.new in the + same directory as Kconfig. + + variant_name The name of the board variant, e.g. 'kindred'""" + # These are the part of the strings that we'll add to the sections + BOARD = 'BOARD_GOOGLE_' + variant_name.upper() + gbb_hwid = get_gbb_hwid(variant_name) + lowercase = variant_name.lower() + capitalized = lowercase.capitalize() + + # These flags track whether we're in a section where we need to add an option + in_gbb_hwid = False + in_mainboard_part_number = False + in_variant_dir = False + + inputname = 'Kconfig' + outputname = 'Kconfig.new' + with open(outputname, 'w') as outfile: + with open(inputname, 'r') as infile: + for rawline in infile: + line = rawline.rstrip('\r\n') + + # Are we in one of the sections of interest? + if line == 'config GBB_HWID': + in_gbb_hwid = True + if line == 'config MAINBOARD_PART_NUMBER': + in_mainboard_part_number = True + if line == 'config VARIANT_DIR': + in_variant_dir = True + + # Are we at the end of a section, and if so, is it one of the + # sections of interest? + if line == '': + if in_gbb_hwid: + print('\tdefault "' + gbb_hwid + '" if ' + BOARD, file=outfile) + in_gbb_hwid = False + if in_mainboard_part_number: + print('\tdefault "' + capitalized + '" if ' + BOARD, file=outfile) + in_mainboard_part_number = False + if in_variant_dir: + print('\tdefault "' + lowercase + '" if ' + BOARD, file=outfile) + in_variant_dir = False + + print(line, file=outfile) + + + +def add_to_Kconfig_name(variant_name): + """Add a config section for the variant to the Kconfig.name + + Kconfig.name is easier to modify than Kconfig; it only has a block at + the end with the new variant's details. + + config BOARD_GOOGLE_${VARIANT} + + variant_name The name of the board variant, e.g. 'kindred'""" + # Board name for the config section + uppercase = variant_name.upper() + BOARD = 'BOARD_GOOGLE_' + uppercase + capitalized = variant_name.lower().capitalize() + + inputname = 'Kconfig.name' + outputname = 'Kconfig.name.new' + with open(outputname, 'w') as outfile: + with open(inputname, 'r') as infile: + # Copy all input lines to output + for rawline in infile: + line = rawline.rstrip('\r\n') + print(line, file=outfile) + + # Now add the new section + print('\nconfig ' + BOARD, file=outfile) + print('\tbool "-> ' + capitalized + '"', file=outfile) + print('\tselect BOARD_GOOGLE_BASEBOARD_HATCH', file=outfile) + print('\tselect BOARD_ROMSIZE_KB_16384', file=outfile) + print('\tselect SOC_INTEL_COMETLAKE', file=outfile) + + + +if __name__ == '__main__': + main() -- To view, visit https://review.coreboot.org/c/coreboot/+/35239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a5b9c8735faafebb2e4e384cb3346867d64c556 Gerrit-Change-Number: 35239 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/drallion: add sku id base on sensor detection
by EricR Lai (Code Review) 19 Sep '19

19 Sep '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35366 ) Change subject: mb/google/drallion: add sku id base on sensor detection ...................................................................... mb/google/drallion: add sku id base on sensor detection Implementing logic base on sensor detection to determine SKU id. BUG=b:140472369 Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I5e71ae6b97378b78055735bbf4b6b55ffe38b978 --- M src/mainboard/google/drallion/Makefile.inc M src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc R src/mainboard/google/drallion/variants/arcada_cml/sku.c M src/mainboard/google/drallion/variants/drallion/Makefile.inc M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h A src/mainboard/google/drallion/variants/drallion/sku.c M src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc C src/mainboard/google/drallion/variants/sarien_cml/sku.c 8 files changed, 52 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/35366/1 diff --git a/src/mainboard/google/drallion/Makefile.inc b/src/mainboard/google/drallion/Makefile.inc index e7c90bb..fff99d4 100644 --- a/src/mainboard/google/drallion/Makefile.inc +++ b/src/mainboard/google/drallion/Makefile.inc @@ -16,7 +16,6 @@ bootblock-y += bootblock.c ramstage-y += ramstage.c -ramstage-y += sku.c romstage-y += romstage.c diff --git a/src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc b/src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc index 1cc010c..b979be1 100644 --- a/src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc +++ b/src/mainboard/google/drallion/variants/arcada_cml/Makefile.inc @@ -20,3 +20,5 @@ ramstage-y += gpio.c romstage-y += gpio.c verstage-y += gpio.c + +ramstage-y += sku.c diff --git a/src/mainboard/google/drallion/sku.c b/src/mainboard/google/drallion/variants/arcada_cml/sku.c similarity index 100% rename from src/mainboard/google/drallion/sku.c rename to src/mainboard/google/drallion/variants/arcada_cml/sku.c diff --git a/src/mainboard/google/drallion/variants/drallion/Makefile.inc b/src/mainboard/google/drallion/variants/drallion/Makefile.inc index 8e070d2..648fa50 100644 --- a/src/mainboard/google/drallion/variants/drallion/Makefile.inc +++ b/src/mainboard/google/drallion/variants/drallion/Makefile.inc @@ -22,3 +22,5 @@ verstage-y += gpio.c romstage-y += memory.c + +ramstage-y += sku.c diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h index ca54580..a69b17d 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h @@ -17,10 +17,21 @@ #define VARIANT_H /* Need to update for Drallion with right SKU IDs*/ -#define VARIANT_SKU_ID 2 -#define VARIANT_SKU_NAME "sku2" -#define VARIANT_SKU_ID_SIGNED_EC 4 -#define VARIANT_SKU_NAME_SIGNED_EC "sku4" +typedef struct { + int id; + const char *name; +} sku_info; + +const static sku_info skus[] = { + // Drallion 360 + { .id = 1, .name = "sku1" }, + // Drallion + { .id = 2, .name = "sku2" }, + // Drallion 360 signed + { .id = 3, .name = "sku3" }, + // Drallion signed + { .id = 4, .name = "sku4" }, +}; /* Return memory SKU for the variant */ int variant_memory_sku(void); diff --git a/src/mainboard/google/drallion/variants/drallion/sku.c b/src/mainboard/google/drallion/variants/drallion/sku.c new file mode 100644 index 0000000..94acad4 --- /dev/null +++ b/src/mainboard/google/drallion/variants/drallion/sku.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <ec/google/wilco/commands.h> +#include <smbios.h> +#include <variant/variant.h> +#include <gpio.h> +#include <variant/gpio.h> + +uint32_t sku_id(void) +{ + return skus[(gpio_get(GPP_H5) | (wilco_ec_signed_fw() << 1))].id; +} + +const char *smbios_system_sku(void) +{ + return skus[(gpio_get(GPP_H5) | (wilco_ec_signed_fw() << 1))].name; +} diff --git a/src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc b/src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc index 1cc010c..b979be1 100644 --- a/src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc +++ b/src/mainboard/google/drallion/variants/sarien_cml/Makefile.inc @@ -20,3 +20,5 @@ ramstage-y += gpio.c romstage-y += gpio.c verstage-y += gpio.c + +ramstage-y += sku.c diff --git a/src/mainboard/google/drallion/sku.c b/src/mainboard/google/drallion/variants/sarien_cml/sku.c similarity index 100% copy from src/mainboard/google/drallion/sku.c copy to src/mainboard/google/drallion/variants/sarien_cml/sku.c -- To view, visit https://review.coreboot.org/c/coreboot/+/35366 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e71ae6b97378b78055735bbf4b6b55ffe38b978 Gerrit-Change-Number: 35366 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

5 12

Change in ...coreboot[master]: cpu/intel/common: Build FSB detection unconditionally
by Kyösti Mälkki (Code Review) 19 Sep '19

19 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31341 Change subject: cpu/intel/common: Build FSB detection unconditionally ...................................................................... cpu/intel/common: Build FSB detection unconditionally Change-Id: I37a34651d9e7d823ad5689d30739294358a97e31 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/common/Makefile.inc 1 file changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/31341/1 diff --git a/src/cpu/intel/common/Makefile.inc b/src/cpu/intel/common/Makefile.inc index b67ca85..ef6c0a4 100644 --- a/src/cpu/intel/common/Makefile.inc +++ b/src/cpu/intel/common/Makefile.inc @@ -1,5 +1,8 @@ ramstage-y += common_init.c -romstage-$(CONFIG_UDELAY_LAPIC) += fsb.c -ramstage-$(CONFIG_UDELAY_LAPIC) += fsb.c -postcar-$(CONFIG_UDELAY_LAPIC) += fsb.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += fsb.c + +bootblock-y += fsb.c +verstage-y += fsb.c +romstage-y += fsb.c +postcar-y += fsb.c +ramstage-y += fsb.c +smm-y += fsb.c -- To view, visit https://review.coreboot.org/c/coreboot/+/31341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37a34651d9e7d823ad5689d30739294358a97e31 Gerrit-Change-Number: 31341 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

5 5

Change in coreboot[master]: cpu,mb,soc: Init missing lb_serial struct fields
by Jacob Garber (Code Review) 19 Sep '19

19 Sep '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34548 ) Change subject: cpu,mb,soc: Init missing lb_serial struct fields ...................................................................... cpu,mb,soc: Init missing lb_serial struct fields Initialize the input_hertz and uart_pci_addr fields of the lb_serial struct to prevent later undefined reads in lb_add_serial(). This was done for exynos5420 in commit ff94e00362 (soc/samsung/exynos5420/uart.c: Init new serial struct variables), and this patch finishes the rest. Change-Id: I733bc8185e2f2d28a9823495b53d6b09dce4deb1 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Found-by: Coverity CID 1354778 --- M src/cpu/ti/am335x/uart.c M src/mainboard/emulation/qemu-power8/uart.c M src/soc/imgtec/pistachio/uart.c M src/soc/mediatek/common/uart.c M src/soc/nvidia/tegra124/uart.c M src/soc/nvidia/tegra210/uart.c M src/soc/qualcomm/ipq40xx/uart.c M src/soc/qualcomm/qcs405/uart.c M src/soc/samsung/exynos5250/uart.c 9 files changed, 25 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/34548/1 diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index 4e9d012..657404c 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -190,8 +190,10 @@ serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = get_uart_baudrate(); serial.regwidth = 2; - lb_add_serial(&serial, data); + serial.input_hertz = uart_platform_refclk(); + serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; + lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } #endif diff --git a/src/mainboard/emulation/qemu-power8/uart.c b/src/mainboard/emulation/qemu-power8/uart.c index 9548b7c..a917421 100644 --- a/src/mainboard/emulation/qemu-power8/uart.c +++ b/src/mainboard/emulation/qemu-power8/uart.c @@ -50,6 +50,9 @@ serial.baseaddr = 0; serial.baud = 115200; serial.regwidth = 1; + serial.input_hertz = uart_platform_refclk(); + serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; + lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } diff --git a/src/soc/imgtec/pistachio/uart.c b/src/soc/imgtec/pistachio/uart.c index a39f2ec..380292f 100644 --- a/src/soc/imgtec/pistachio/uart.c +++ b/src/soc/imgtec/pistachio/uart.c @@ -151,8 +151,10 @@ serial.baseaddr = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; serial.baud = get_uart_baudrate(); serial.regwidth = 1 << UART_SHIFT; - lb_add_serial(&serial, data); + serial.input_hertz = uart_platform_refclk(); + serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; + lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } #endif diff --git a/src/soc/mediatek/common/uart.c b/src/soc/mediatek/common/uart.c index 8905c55..c53909d 100644 --- a/src/soc/mediatek/common/uart.c +++ b/src/soc/mediatek/common/uart.c @@ -181,8 +181,10 @@ serial.input_hertz = UART_HZ; serial.baud = get_uart_baudrate(); serial.regwidth = 4; - lb_add_serial(&serial, data); + serial.input_hertz = uart_platform_refclk(); + serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; + lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } #endif diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c index c9514ac..697c90d 100644 --- a/src/soc/nvidia/tegra124/uart.c +++ b/src/soc/nvidia/tegra124/uart.c @@ -136,8 +136,10 @@ serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = get_uart_baudrate(); serial.regwidth = 4; - lb_add_serial(&serial, data); + serial.input_hertz = uart_platform_refclk(); + serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; + lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } #endif diff --git a/src/soc/nvidia/tegra210/uart.c b/src/soc/nvidia/tegra210/uart.c index a91818c..0de85cb 100644 --- a/src/soc/nvidia/tegra210/uart.c +++ b/src/soc/nvidia/tegra210/uart.c @@ -123,8 +123,10 @@ serial.baseaddr = CONFIG_CONSOLE_SERIAL_TEGRA210_UART_ADDRESS; serial.baud = get_uart_baudrate(); serial.regwidth = 4; - lb_add_serial(&serial, data); + serial.input_hertz = uart_platform_refclk(); + serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; + lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } #endif diff --git a/src/soc/qualcomm/ipq40xx/uart.c b/src/soc/qualcomm/ipq40xx/uart.c index eb3731b..77e0480 100644 --- a/src/soc/qualcomm/ipq40xx/uart.c +++ b/src/soc/qualcomm/ipq40xx/uart.c @@ -293,6 +293,8 @@ serial.baseaddr = (uint32_t)UART1_DM_BASE; serial.baud = get_uart_baudrate(); serial.regwidth = 1; + serial.input_hertz = uart_platform_refclk(); + serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/soc/qualcomm/qcs405/uart.c b/src/soc/qualcomm/qcs405/uart.c index 4a43312..8278db2 100644 --- a/src/soc/qualcomm/qcs405/uart.c +++ b/src/soc/qualcomm/qcs405/uart.c @@ -296,6 +296,8 @@ serial.baseaddr = (uint64_t)UART2_DM_BASE; serial.baud = get_uart_baudrate(); serial.regwidth = 1; + serial.input_hertz = uart_platform_refclk(); + serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/soc/samsung/exynos5250/uart.c b/src/soc/samsung/exynos5250/uart.c index 1b8e785..9654033 100644 --- a/src/soc/samsung/exynos5250/uart.c +++ b/src/soc/samsung/exynos5250/uart.c @@ -193,8 +193,10 @@ serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = get_uart_baudrate(); serial.regwidth = 4; - lb_add_serial(&serial, data); + serial.input_hertz = uart_platform_refclk(); + serial.uart_pci_addr = CONFIG_UART_PCI_ADDR; + lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/34548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I733bc8185e2f2d28a9823495b53d6b09dce4deb1 Gerrit-Change-Number: 34548 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

4 14

Change in coreboot[master]: mb/google/poppy/variants/rammus: Add workaround for touchscreen FW re...
by Frank Chu (Code Review) 19 Sep '19

19 Sep '19

Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35308 ) Change subject: mb/google/poppy/variants/rammus: Add workaround for touchscreen FW recovery ...................................................................... Patch Set 2: change delay to 1.5s -- To view, visit https://review.coreboot.org/c/coreboot/+/35308 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iccbc3da55c41b93c9c7faada532a1d849eab2a86 Gerrit-Change-Number: 35308 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Matthew Blecker <matthewb(a)chromium.org> Gerrit-Comment-Date: Thu, 19 Sep 2019 08:54:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Rizwan Qureshi (Code Review) 19 Sep '19

19 Sep '19

Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... Patch Set 47: (5 comments) https://review.coreboot.org/c/coreboot/+/27369/46//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/27369/46//COMMIT_MSG@36 PS46, Line 36: current slot MCU and RW staging MCU are same. If so, update the staging area > why do you need to update the staging area if it's the same microcode? Done https://review.coreboot.org/c/coreboot/+/27369/46//COMMIT_MSG@39 PS46, Line 39: Also, make sure that the top is enabled in normal/developer mode and disabled > top swap? Done https://review.coreboot.org/c/coreboot/+/27369/46/src/soc/intel/common/base… File src/soc/intel/common/basecode/fw_update/ucode_update.c: https://review.coreboot.org/c/coreboot/+/27369/46/src/soc/intel/common/base… PS46, Line 33: __weak void ucode_update_reboot(void) > I don't see the need for weak here provide an option for the caller to define their own reset function, if they want to do any housekeeping. If not defined this will do a board reset. https://review.coreboot.org/c/coreboot/+/27369/46/src/soc/intel/common/base… PS46, Line 143: /* Get slot MCU */ > why is it called slot? […] CBFS makes sense. https://review.coreboot.org/c/coreboot/+/27369/46/src/soc/intel/common/base… PS46, Line 160: /* Compare */ > that's clear by memcmp. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 47 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Comment-Date: Thu, 19 Sep 2019 08:51:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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coreboot-gerrit September 2019