Hello Yu-Ping Wu, Julius Werner, You-Cheng Syu, Hung-Te Lin, SJ Huang, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34990
to look at the new patch set (#29).
Change subject: mediatek/mt8183: Use different DRAM frequencies for eMCP DDR
......................................................................
mediatek/mt8183: Use different DRAM frequencies for eMCP DDR
Devices using eMCP may run at a high DRAM frequency (e.g., 3600Mbps)
while those with discrete DRAM can only run at 3200Mbps. This patch
enables 3600Mbps for eMCP DDR for better system performance.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly and stress test passes on Kukui
Change-Id: Iab6a9c2c390feeb9497b051a255b29566909e656
Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com>
---
M src/soc/mediatek/mt8183/emi.c
M src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h
2 files changed, 24 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/34990/29
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Gerrit-Change-Number: 34990
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Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35402 )
Change subject: soc/intel/common/block/cse: Add boot partition related APIs
......................................................................
Patch Set 6:
(5 comments)
https://review.coreboot.org/c/coreboot/+/35402/6/src/soc/intel/common/block…
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/35402/6/src/soc/intel/common/block…
PS6, Line 92: #define BUP_COMMON_GET_BOOT_PARTITION_INFO_CMD_REQ 0x1C
: #define BUP_COMMON_SET_BOOT_PARTITION_CMD_REQ 0x1D
can we move these commands IDs and ones above into a separate header file and refer it from there? Not sure if the list would keep growing with more CLs.
https://review.coreboot.org/c/coreboot/+/35402/6/src/soc/intel/common/block…
PS6, Line 731: int
unsigned int?
https://review.coreboot.org/c/coreboot/+/35402/6/src/soc/intel/common/block…
PS6, Line 760: int
same.
https://review.coreboot.org/c/coreboot/+/35402/6/src/soc/intel/common/block…
File src/soc/intel/common/block/include/intelblocks/cse.h:
https://review.coreboot.org/c/coreboot/+/35402/6/src/soc/intel/common/block…
PS6, Line 143: #define RO_BP1 0
: #define RW_BP2 1
: #define RW_BP3 2
can we have it as enum as well would help it bundle under Boot partition context or add comment here , as to what it implies to.
https://review.coreboot.org/c/coreboot/+/35402/6/src/soc/intel/common/block…
PS6, Line 150: BP_STATUS_SUCCESS = 0,
: BP_STATUS_GENERAL_FAILURE = 1,
: BP_STATUS_PARTITION_NOT_PRESENT = 2,
: BP_STATUS_HOST_REQUEST_FOR_PARTITION_SWITCH = 3,
consistent spacing?
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Gerrit-Change-Number: 35402
Gerrit-PatchSet: 6
Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
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Gerrit-Comment-Date: Fri, 20 Sep 2019 05:04:56 +0000
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Gerrit-MessageType: comment
Hello Patrick Rudolph, Philipp Deppenwiese, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35321
to look at the new patch set (#4).
Change subject: soc/fsp_broadwell_de: Add devhide functionality
......................................................................
soc/fsp_broadwell_de: Add devhide functionality
Add function to hide IIO PCIe root ports.
TEST=On OCP Monolake, hide built-in NIC PCIe root port [0.2.2 and 0.2.3]
and make sure OS does not detect built-in NIC.
Change-Id: I2fcac5b7d9a7a52a2801c010bfccf247f2a44581
Signed-off-by: Andrey Petrov <anpetrov(a)fb.com>
---
M src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h
M src/soc/intel/fsp_broadwell_de/include/soc/ubox.h
M src/soc/intel/fsp_broadwell_de/southcluster.c
3 files changed, 62 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/35321/4
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Gerrit-Change-Number: 35321
Gerrit-PatchSet: 4
Gerrit-Owner: Andrey Petrov <anpetrov(a)fb.com>
Gerrit-Reviewer: Andrey Petrov <anpetrov(a)fb.com>
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Andrey Petrov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35322 )
Change subject: mainboard/ocp/monolake: Hide internal NIC
......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/c/coreboot/+/35322/1/src/mainboard/ocp/monolake…
File src/mainboard/ocp/monolake/romstage.c:
https://review.coreboot.org/c/coreboot/+/35322/1/src/mainboard/ocp/monolake…
PS1, Line 64: // Hide built-in NIC.
> that should be part of the soc code and read the devicetree. […]
Ack
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Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-MessageType: comment
Hello Patrick Rudolph, Philipp Deppenwiese, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35322
to look at the new patch set (#3).
Change subject: mainboard/ocp/monolake: Hide internal NIC
......................................................................
mainboard/ocp/monolake: Hide internal NIC
Disable root port IOU0 to which built-in NIC is attached.
TEST=on OCP monolake, hide built-in NIC and make sure OS does not report
built-in NIC
Change-Id: I2384e7dd073355f0ced2902ac2d8418996b1c5aa
Signed-off-by: Andrey Petrov <anpetrov(a)fb.com>
---
M src/mainboard/ocp/monolake/devicetree.cb
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/35322/3
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Gerrit-MessageType: newpatchset
Hello Patrick Rudolph, Philipp Deppenwiese, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/35321
to look at the new patch set (#3).
Change subject: soc/fsp_broadwell_de: Add devhide functionality
......................................................................
soc/fsp_broadwell_de: Add devhide functionality
Add function to hide IIO PCIe root ports.
TEST=On OCP Monolake, hide built-in NIC PCIe root port [0.2.2 and 0.2.3] and
make sure OS does not detect built-in NIC.
Change-Id: I2fcac5b7d9a7a52a2801c010bfccf247f2a44581
Signed-off-by: Andrey Petrov <anpetrov(a)fb.com>
---
M src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h
M src/soc/intel/fsp_broadwell_de/include/soc/ubox.h
M src/soc/intel/fsp_broadwell_de/southcluster.c
3 files changed, 60 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/35321/3
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