coreboot-gerrit September 2019

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Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Rizwan Qureshi (Code Review) 19 Sep '19

19 Sep '19

Hello Patrick Rudolph, Aaron Durbin, dhaval v sharma, Subrata Banik, Patrick Rudolph, Paul Menzel, Duncan Laurie, build bot (Jenkins), Patrick Georgi, Furquan Shaikh, Varshit B Pandya, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/27369 to look at the new patch set (#47). Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... soc/intel/basecode: Add support for updating ucode loaded via FIT Intel’s FIT (Firmware Interface Table) based MCU (microcode/pcode patch) loading mechanism patches the microcode before CPU reset. In the current Chromebooks field updatable FW has to be first verified by vboot. Since the MCU is loaded before reset vboot cannot verify the same and hence we end up restricting FIT based MCU update only from RO. This patch implements a scheme which will allow chromebooks to update MCU in the field. Create 2 bootblocks (use INTEL_ADD_TOP_SWAP_BOOTBLOCK) each containing their own FIT table. First bootblock FIT has pointers to MCUs (in microcode_blob.bin) which resides in RO section. This is will be used in the recovery scenario. Second bootblock (Normal mode) is identical to the first one except the FIT. Insert an additional pointer to a MCU that will reside in a staging area. Use the CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG config to insert the address of the staging area into FIT. Top swap control bit in RTC BUC register (0x3414) is used to switch between the two bootblocks. Reserve a region in the FMAP which is equal to or greater than the MCU size specified in the BWG for a particular SoC (e.g., for Skylake/Kaby Lake it is 192K). This is a RW region just like the RW_MRC_CACHE. MCU from RW-A/RW-B will be copied to this region during boot. Protect this staging area with a FPR. Basic update flow: In non-recovery mode, Once a slot has been selected and loaded, check if the current slot MCU and RW staging MCU are same. If not, update the staging area with the MCU found in the current slot and reset the system. Also, make sure that the top-swap is enabled in normal/developer mode and disabled in recovery mode. In order to enable the update feature: * The mainboard chromeos.fmd should include a new region for staging MCU e.g, RW_UCODE_STAGED. * Select config TOP_SWAP_BASED_VBOOT_UCODE_UPDATE. * Implement a call to check_and_update_ucode() and handle the failure appropriately. Add documentation to describing the MCU update procedure. TEST=Create an FW image for soraka and flash, create a chromeos-firmwareupdate shellball with a newer MCU and perform an update. Make sue that the currently loaded microcode version matches the one in firmwareupdate. Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: dhaval v sharma <dhaval.v.sharma(a)intel.com> Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> --- M Documentation/soc/intel/index.md A Documentation/soc/intel/ucode_update/flash_layout.svg A Documentation/soc/intel/ucode_update/microcode_update_model.md A src/soc/intel/common/basecode/fw_update/Kconfig A src/soc/intel/common/basecode/fw_update/Makefile.inc A src/soc/intel/common/basecode/fw_update/ucode_update.c A src/soc/intel/common/basecode/include/intelbasecode/ucode_update.h 7 files changed, 644 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/27369/47 -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 47 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: intel/txt: Try to validate TPM NV indexes
by Patrick Rudolph (Code Review) 19 Sep '19

19 Sep '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35469 ) Change subject: intel/txt: Try to validate TPM NV indexes ...................................................................... intel/txt: Try to validate TPM NV indexes fixme Change-Id: Ia96d5fb89d97d2de90f8e050a7d672998d6d2830 --- M src/security/intel/txt/txt.c 1 file changed, 51 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/35469/1 diff --git a/src/security/intel/txt/txt.c b/src/security/intel/txt/txt.c index d8defb3..1d8b3d2 100644 --- a/src/security/intel/txt/txt.c +++ b/src/security/intel/txt/txt.c @@ -264,6 +264,54 @@ return 0; } +static int verify_tpm(void) +{ + + uint32_t result; + +#if CONFIG(TPM1) + result = tlcl_read(0x50000003, NULL, 0); + + if (result != TPM_SUCCESS) { + printk(BIOS_ERR, "TEE-TXT: TPM 1.2 AUX NV index not set\n"); + return -1; + } + + // Write 0x50000003 with size 96 for SHA1 + result = tlcl_define_space(0x50000003, 0, 96); + if (result != TPM_E_NV_DEFINED) { + } +#endif +#if CONFIG(TPM2) + struct nv_read_public_response resp; + + tlcl_nv_undefine_special(0xC10102); + + result = tlcl_nv_read_public(0xC10102, &resp); + printk(BIOS_DEBUG, "resp nameAlg %x\n", resp.nvPublic.nameAlg); + printk(BIOS_DEBUG, "resp dataSize %x\n", resp.nvPublic.dataSize); + + if (result != TPM_SUCCESS) { + printk(BIOS_ERR, "TEE-TXT: TPM 2.0 AUX NV index not set\n"); + //return -1; + } + + static const TPMA_NV tpma = {.TPMA_NV_POLICYWRITE = 1, + .TPMA_NV_AUTHREAD = 1, + .TPMA_NV_PLATFORMCREATE = 1, + .TPMA_NV_POLICY_DELETE = 1, + .TPMA_NV_NO_DA = 1, + .TPMA_NV_WRITE_STCLEAR = 1, + }; + // Write 0x1C10102 with size 104 for SHA256 + result = tlcl_define_space(0xC10102, 104, tpma, NULL, 0); + if (result != TPM_E_NV_DEFINED) { + } +#endif + + return 0; +} + /* * Test all bits for TXT execution. * @@ -599,6 +647,9 @@ if (CONFIG(PARALLEL_MP) && CONFIG(PARALLEL_MP_AP_WORK)) mp_park_aps(); + if (verify_tpm()) + failure = true; + return failure; } -- To view, visit https://review.coreboot.org/c/coreboot/+/35469 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia96d5fb89d97d2de90f8e050a7d672998d6d2830 Gerrit-Change-Number: 35469 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/tpm/tss: Implement NV_UndefineSpaceSpecial
by Patrick Rudolph (Code Review) 19 Sep '19

19 Sep '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35468 ) Change subject: security/tpm/tss: Implement NV_UndefineSpaceSpecial ...................................................................... security/tpm/tss: Implement NV_UndefineSpaceSpecial fixme Change-Id: I8d7861f2246d753406b1f049733ab9abfec462a7 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/security/tpm/tss.h M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss/tcg-2.0/tss_marshaling.c M src/security/tpm/tss/tcg-2.0/tss_structures.h 4 files changed, 45 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/35468/1 diff --git a/src/security/tpm/tss.h b/src/security/tpm/tss.h index b7eb97f..1da4b8d 100644 --- a/src/security/tpm/tss.h +++ b/src/security/tpm/tss.h @@ -184,6 +184,7 @@ uint32_t tlcl_nv_read_public(uint32_t index, struct nv_read_public_response *resp); +uint32_t tlcl_nv_undefine_special(uint32_t index); /** * Perform a TPM_Extend. */ diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index bc0ce6c..ee1e0f4 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -303,6 +303,26 @@ return TPM_SUCCESS; } +uint32_t tlcl_nv_undefine_special(uint32_t index) +{ + struct tpm2_response *response; + /* TPM Wll reject attempts to write at non-defined index. */ + struct tpm2_nv_undefine_space_cmd nv_rp = { + .nvIndex = HR_NV_INDEX + index, + .use_platform_auth = 1, + }; + + response = tpm_process_command(TPM2_NV_UndefineSpaceSpecial, &nv_rp); + + printk(BIOS_INFO, "%s: response is %x\n", + __func__, response ? response->hdr.tpm_code : -1); + + if (!response || response->hdr.tpm_code) + return TPM_E_IOERROR; + + return TPM_SUCCESS; +} + uint32_t tlcl_startup(void) { return tlcl_send_startup(TPM_SU_CLEAR); diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index 8e768d5..e33c0ef 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -223,6 +223,19 @@ return rc; } +static int marshal_nv_undefine_space_special(struct obuf *ob, + struct tpm2_nv_undefine_space_cmd *command_body) +{ + int rc = 0; + uint32_t handles[] = { command_body->nvIndex, TPM_RH_PLATFORM }; + if (!command_body->use_platform_auth) + handles[1] = TPM_RH_OWNER; + + rc |= marshal_common_session_header(ob, handles, ARRAY_SIZE(handles)); + + return rc; +} + static int marshal_nv_read(struct obuf *ob, struct tpm2_nv_read_cmd *command_body) { @@ -367,6 +380,10 @@ rc |= marshal_nv_read_public(ob, tpm_command_body); break; + case TPM2_NV_UndefineSpaceSpecial: + rc |= marshal_nv_undefine_space_special(ob, tpm_command_body); + break; + case TPM2_SelfTest: rc |= marshal_selftest(ob, tpm_command_body); break; @@ -626,6 +643,7 @@ case TPM2_Hierarchy_Control: case TPM2_Clear: case TPM2_NV_DefineSpace: + case TPM2_NV_UndefineSpaceSpecial: case TPM2_NV_Write: case TPM2_NV_WriteLock: case TPM2_PCR_Extend: diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index 92c6a3f..413c0a2 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -46,6 +46,7 @@ #define SHA256_DIGEST_SIZE 32 /* Some hardcoded hierarchies. */ +#define TPM_RH_OWNER 0x40000001 #define TPM_RH_NULL 0x40000007 #define TPM_RS_PW 0x40000009 #define TPM_RH_PLATFORM 0x4000000C @@ -412,6 +413,11 @@ TPMI_RH_NV_INDEX nvIndex; }; +struct tpm2_nv_undefine_space_cmd { + TPMI_RH_NV_INDEX nvIndex; + uint8_t use_platform_auth; +}; + struct tpm2_nv_write_lock_cmd { TPMI_RH_NV_INDEX nvIndex; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/35468 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d7861f2246d753406b1f049733ab9abfec462a7 Gerrit-Change-Number: 35468 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/tpm: Add TPM2_NV_ReadPublic
by Patrick Rudolph (Code Review) 19 Sep '19

19 Sep '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35467 ) Change subject: security/tpm: Add TPM2_NV_ReadPublic ...................................................................... security/tpm: Add TPM2_NV_ReadPublic Fixme Change-Id: Ia819f0e1b1ebd2c2d82f953272c8932d733ed229 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/security/tpm/tss.h M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss/tcg-2.0/tss_marshaling.c M src/security/tpm/tss/tcg-2.0/tss_structures.h 4 files changed, 116 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/35467/1 diff --git a/src/security/tpm/tss.h b/src/security/tpm/tss.h index 30e2a7b..b7eb97f 100644 --- a/src/security/tpm/tss.h +++ b/src/security/tpm/tss.h @@ -179,6 +179,12 @@ uint32_t tlcl_lock_nv_write(uint32_t index); /** + * Read the public attributes of a defined NV index. + */ +uint32_t tlcl_nv_read_public(uint32_t index, + struct nv_read_public_response *resp); + +/** * Perform a TPM_Extend. */ uint32_t tlcl_extend(int pcr_num, const uint8_t *in_digest, diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index 08a7caa..bc0ce6c 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -281,6 +281,28 @@ return TPM_SUCCESS; } +uint32_t tlcl_nv_read_public(uint32_t index, + struct nv_read_public_response *resp) +{ + struct tpm2_response *response; + /* TPM Wll reject attempts to write at non-defined index. */ + struct tpm2_nv_read_public_cmd nv_rp = { + .nvIndex = HR_NV_INDEX + index, + }; + + response = tpm_process_command(TPM2_NV_ReadPublic, &nv_rp); + + printk(BIOS_INFO, "%s: response is %x\n", + __func__, response ? response->hdr.tpm_code : -1); + + if (!response || response->hdr.tpm_code) + return TPM_E_IOERROR; + + memcpy(resp, &response->nv_read_public, sizeof(*resp)); + + return TPM_SUCCESS; +} + uint32_t tlcl_startup(void) { return tlcl_send_startup(TPM_SU_CLEAR); diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index 345aec5..8e768d5 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -21,6 +21,7 @@ #define unmarshal_TPM_CC(a, b) ibuf_read_be32(a, b) #define unmarshal_TPM_PT(a, b) ibuf_read_be32(a, b) #define unmarshal_TPM_HANDLE(a, b) ibuf_read_be32(a, b) +#define unmarshal_TPMI_ALG_HASH(a, b) ibuf_read_be16(a, b) #define marshal_TPM_HANDLE(a, b) obuf_write_be32(a, b) #define marshal_TPMI_ALG_HASH(a, b) obuf_write_be16(a, b) @@ -204,6 +205,12 @@ return marshal_common_session_header(ob, handles, ARRAY_SIZE(handles)); } +static int marshal_nv_read_public(struct obuf *ob, + struct tpm2_nv_read_public_cmd *command_body) +{ + return marshal_TPM_HANDLE(ob, command_body->nvIndex); +} + static int marshal_pcr_extend(struct obuf *ob, struct tpm2_pcr_extend_cmd *command_body) { @@ -356,6 +363,10 @@ rc |= marshal_nv_write_lock(ob, tpm_command_body); break; + case TPM2_NV_ReadPublic: + rc |= marshal_nv_read_public(ob, tpm_command_body); + break; + case TPM2_SelfTest: rc |= marshal_selftest(ob, tpm_command_body); break; @@ -502,6 +513,51 @@ return 0; } +static int unmarshal_TPMA_NV(struct ibuf *ib, TPMA_NV *v) +{ + uint32_t tmp; + + if (ibuf_read_be32(ib, &tmp)) + return -1; + + memcpy(v, &tmp, sizeof(tmp)); + return 0; +} + +static int unmarshal_nv_read_public(struct ibuf *ib, struct nv_read_public_response *resp) +{ + uint16_t size; + + if (ibuf_read_be16(ib, &size)) + return -1; + + if (unmarshal_TPM_HANDLE(ib, &resp->nvPublic.nvIndex)) + return -1; + if (unmarshal_TPMI_ALG_HASH(ib, &resp->nvPublic.nameAlg)) + return -1; + if (unmarshal_TPMA_NV(ib, &resp->nvPublic.attributes)) + return -1; + if (ibuf_read_be16(ib, &resp->nvPublic.authPolicy.size)) + return -1; + if (resp->nvPublic.authPolicy.size > sizeof(resp->nvPublic.authPolicy.buffer)) + return -1; + if (ibuf_read(ib, &resp->nvPublic.authPolicy.buffer, resp->nvPublic.authPolicy.size)) + return -1; + if (ibuf_read_be16(ib, &resp->nvPublic.dataSize)) + return -1; + if (ibuf_read_be16(ib, &resp->nvName.size)) + return -1; + printk(BIOS_ERR, "resp->nvName.size %x\n", resp->nvName.size); + + if (resp->nvName.size > sizeof(resp->nvName.buffer)) + return -1; + if (ibuf_read(ib, &resp->nvName.buffer, resp->nvName.size)) + return -1; + ibuf_oob_drain(ib, ibuf_remaining(ib)); + + return 0; +} + static int unmarshal_vendor_command(struct ibuf *ib, struct vendor_command_response *vcr) { @@ -563,6 +619,10 @@ rc |= unmarshal_nv_read(ib, &tpm2_resp->nvr); break; + case TPM2_NV_ReadPublic: + rc |= unmarshal_nv_read_public(ib, &tpm2_resp->nv_read_public); + break; + case TPM2_Hierarchy_Control: case TPM2_Clear: case TPM2_NV_DefineSpace: diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index 7332739..92c6a3f 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -66,6 +66,7 @@ } __packed; /* TPM command codes. */ +#define TPM2_NV_UndefineSpaceSpecial ((TPM_CC)0x0000011F) #define TPM2_Hierarchy_Control ((TPM_CC)0x00000121) #define TPM2_Clear ((TPM_CC)0x00000126) #define TPM2_NV_DefineSpace ((TPM_CC)0x0000012A) @@ -75,6 +76,7 @@ #define TPM2_Startup ((TPM_CC)0x00000144) #define TPM2_Shutdown ((TPM_CC)0x00000145) #define TPM2_NV_Read ((TPM_CC)0x0000014E) +#define TPM2_NV_ReadPublic ((TPM_CC)0x00000169) #define TPM2_GetCapability ((TPM_CC)0x0000017A) #define TPM2_PCR_Extend ((TPM_CC)0x00000182) /* TPM2 specifies vendor commands need to have this bit set. Vendor command @@ -353,6 +355,27 @@ uint8_t *auth; }; +typedef struct { + uint16_t size; + uint8_t buffer[64]; +} TPM2B_NAME; + +typedef struct { + TPMI_RH_NV_INDEX nvIndex; + TPMI_ALG_HASH nameAlg; + TPMA_NV attributes; + struct { + uint16_t size; + TPMU_HA buffer; + } authPolicy; + uint16_t dataSize; +} TPM2B_PUBLIC; + +struct nv_read_public_response { + TPM2B_PUBLIC nvPublic; + TPM2B_NAME nvName; +} __packed; + struct tpm2_response { struct tpm_header hdr; union { @@ -360,6 +383,7 @@ struct nv_read_response nvr; struct tpm2_session_header def_space; struct vendor_command_response vcr; + struct nv_read_public_response nv_read_public; }; }; @@ -384,6 +408,10 @@ uint16_t offset; }; +struct tpm2_nv_read_public_cmd { + TPMI_RH_NV_INDEX nvIndex; +}; + struct tpm2_nv_write_lock_cmd { TPMI_RH_NV_INDEX nvIndex; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/35467 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia819f0e1b1ebd2c2d82f953272c8932d733ed229 Gerrit-Change-Number: 35467 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation/mainboard: Fix index
by Nico Huber (Code Review) 19 Sep '19

19 Sep '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35462 ) Change subject: Documentation/mainboard: Fix index ...................................................................... Documentation/mainboard: Fix index Remove duplicate headings, move vendor sections that were placed amidst other vendor hierarchies, and while we are at it, sort it alphabetically. Change-Id: I1f684deac3bbf98e8584089be05daf1c73e74a2d Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M Documentation/mainboard/index.md 1 file changed, 23 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/35462/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 08689b7..2745a71 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -2,6 +2,11 @@ This section contains documentation about coreboot on specific mainboards. +## ASRock + +- [H81M-HDS](asrock/h81m-hds.md) +- [H110M-DVS](asrock/h110m-dvs.md) + ## ASUS - [F2A85-M](asus/f2a85-m.md) @@ -9,11 +14,6 @@ - [P8H61-M Pro](asus/p8h61-m_pro.md) - [P8Z77-M Pro](asus/p8z77-m_pro.md) -## ASRock - -- [H81M-HDS](asrock/h81m-hds.md) -- [H110M-DVS](asrock/h110m-dvs.md) - ## Cavium - [CN81XX EVB SFF](cavium/cn8100_sff_evb.md) @@ -26,12 +26,6 @@ - [Qemu RISC-V emulator](emulation/qemu-riscv.md) - [Qemu AArch64 emulator](emulation/qemu-aarch64.md) -## Intel - -- [DG43GT](intel/dg43gt.md) -- [IceLake RVP](intel/icelake_rvp.md) -- [KBLRVP11](intel/kblrvp11.md) - ## Facebook - [FBG-1701](facebook/fbg1701.md) @@ -48,11 +42,6 @@ - [Dragonegg](google/dragonegg.md) -## Open Cellular - -- [Elgon](opencellular/elgon.md) -- [Rotundu](opencellular/rotundu.md) - ## HP - [Compaq 8200 Elite SFF](hp/compaq_8200_sff.md) @@ -63,6 +52,12 @@ - [EliteBook common](hp/elitebook_series.md) - [EliteBook 8760w](hp/8760w.md) +## Intel + +- [DG43GT](intel/dg43gt.md) +- [IceLake RVP](intel/icelake_rvp.md) +- [KBLRVP11](intel/kblrvp11.md) + ## Lenovo - [Mainboard codenames](lenovo/codenames.md) @@ -70,10 +65,6 @@ - [T4xx common](lenovo/t4xx_series.md) - [X2xx common](lenovo/x2xx_series.md) -## Portwell - -- [PQ7-M107](portwell/pq7-m107.md) - ### Sandy Bridge series - [T420](lenovo/t420.md) @@ -92,17 +83,23 @@ - [MS-7707](msi/ms7707/ms7707.md) -## PC Engines +## Open Cellular -- [APU2](pcengines/apu2.md) - -## Roda - -- [RK9 Flash Header](roda/rk9/flash_header.md) +- [Elgon](opencellular/elgon.md) +- [Rotundu](opencellular/rotundu.md) ## PC Engines - [APU1](pcengines/apu1.md) +- [APU2](pcengines/apu2.md) + +## Portwell + +- [PQ7-M107](portwell/pq7-m107.md) + +## Roda + +- [RK9 Flash Header](roda/rk9/flash_header.md) ## SiFive -- To view, visit https://review.coreboot.org/c/coreboot/+/35462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f684deac3bbf98e8584089be05daf1c73e74a2d Gerrit-Change-Number: 35462 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/basecode: Add support for updating ucode loaded via FIT
by Patrick Rudolph (Code Review) 19 Sep '19

19 Sep '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 ) Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT ...................................................................... Patch Set 46: Code-Review+1 (5 comments) https://review.coreboot.org/c/coreboot/+/27369/46//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/27369/46//COMMIT_MSG@36 PS46, Line 36: current slot MCU and RW staging MCU are same. If so, update the staging area why do you need to update the staging area if it's the same microcode? https://review.coreboot.org/c/coreboot/+/27369/46//COMMIT_MSG@39 PS46, Line 39: Also, make sure that the top is enabled in normal/developer mode and disabled top swap? https://review.coreboot.org/c/coreboot/+/27369/46/src/soc/intel/common/base… File src/soc/intel/common/basecode/fw_update/ucode_update.c: https://review.coreboot.org/c/coreboot/+/27369/46/src/soc/intel/common/base… PS46, Line 33: __weak void ucode_update_reboot(void) I don't see the need for weak here https://review.coreboot.org/c/coreboot/+/27369/46/src/soc/intel/common/base… PS46, Line 143: /* Get slot MCU */ why is it called slot? Isn't it a file in CBFS? https://review.coreboot.org/c/coreboot/+/27369/46/src/soc/intel/common/base… PS46, Line 160: /* Compare */ that's clear by memcmp. What do you compare? -- To view, visit https://review.coreboot.org/c/coreboot/+/27369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655 Gerrit-Change-Number: 27369 Gerrit-PatchSet: 46 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Dhaval Sharma <dhaval.v.sharma(a)intel.corp-partner.google.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-CC: rushikesh s kadam <rushikesh.s.kadam(a)intel.com> Gerrit-Comment-Date: Thu, 19 Sep 2019 06:46:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: security/tpm/tss/tcg-2.0: Add multi digits support to tlcl_extend()
by Frans Hendriks (Code Review) 19 Sep '19

19 Sep '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33252 Change subject: security/tpm/tss/tcg-2.0: Add multi digits support to tlcl_extend() ...................................................................... security/tpm/tss/tcg-2.0: Add multi digits support to tlcl_extend() To support multi digists the tlcl_extend() for TPM2 expects TPML_DIGEST_VALUE pointer as input argument. BUG=N/A TEST=Build binary and verified logging on Facebook FBG-1701 Change-Id: I8d86c41c23e4e93a84e0527d7cddcfd30d5d8394 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/security/tpm/tspi/tspi.c M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss/tcg-2.0/tss_structures.h 3 files changed, 65 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/33252/1 diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 4698a4d..df1ca3b 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -4,6 +4,7 @@ * Copyright (c) 2013 The Chromium OS Authors. All rights reserved. * Copyright 2017 Facebook Inc. * Copyright 2018 Siemens AG + * Copyright 2019 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -209,7 +210,28 @@ if (!digest) return TPM_E_IOERROR; - result = tlcl_extend(pcr, digest, NULL); + if (CONFIG(TPM2)) { + TPML_DIGEST_VALUES tpml_digests; + + tpml_digests.count = 1; + switch (digest_algo) { + case VB2_HASH_SHA1: + tpml_digests.digests[0].hashAlg = TPM_ALG_SHA1; + memcpy(tpml_digests.digests[0].digest.sha1, digest, + sizeof(TPMU_HA)); + break; + case VB2_HASH_SHA256: + tpml_digests.digests[0].hashAlg = TPM_ALG_SHA256; + memcpy(tpml_digests.digests[0].digest.sha256, digest, + sizeof(TPMU_HA)); + break; + default: + return TPM_E_IOERROR; + } + result = tlcl_extend(pcr, (uint8_t *)&tpml_digests, NULL); + } else { + result = tlcl_extend(pcr, digest, NULL); + } if (result != TPM_SUCCESS) return result; diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index e579bff..4574b4f 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -126,24 +126,53 @@ } /* - * The caller will provide the digest in a 32 byte buffer, let's consider it a - * sha256 digest. + * The caller will provide the digest in a 32 byte buffer */ uint32_t tlcl_extend(int pcr_num, const uint8_t *in_digest, uint8_t *out_digest) { struct tpm2_pcr_extend_cmd pcr_ext_cmd; struct tpm2_response *response; + int i; + TPML_DIGEST_VALUES *tpml_digests; pcr_ext_cmd.pcrHandle = HR_PCR + pcr_num; - pcr_ext_cmd.digests.count = 1; - pcr_ext_cmd.digests.digests[0].hashAlg = TPM_ALG_SHA256; - memcpy(pcr_ext_cmd.digests.digests[0].digest.sha256, in_digest, - sizeof(pcr_ext_cmd.digests.digests[0].digest.sha256)); + tpml_digests = (TPML_DIGEST_VALUES *)in_digest; + pcr_ext_cmd.digests.count = tpml_digests->count; + + for (i = 0; i < tpml_digests->count ; i++) { + pcr_ext_cmd.digests.digests[i].hashAlg = + tpml_digests->digests[i].hashAlg; + switch (tpml_digests->digests[i].hashAlg) { + case TPM_ALG_SHA1: + memcpy(pcr_ext_cmd.digests.digests[i].digest.sha1, + tpml_digests->digests[i].digest.sha1, + sizeof(TPMU_HA)); + break; + case TPM_ALG_SHA256: + memcpy(pcr_ext_cmd.digests.digests[i].digest.sha256, + tpml_digests->digests[i].digest.sha256, + sizeof(TPMU_HA)); + } + } response = tpm_process_command(TPM2_PCR_Extend, &pcr_ext_cmd); - printk(BIOS_INFO, "%s: response is %x\n", + /* + * Check if we are invalidating the pcrs, ignore the error if this is + * the case + */ + if ((tpml_digests->count == 1) && + (tpml_digests->digests[0].hashAlg == TPM_ALG_ERROR) && + (tpml_digests->digests[0].digest.invalidate_pcrs == 1) && + response && (response->hdr.tpm_code & ~TPM_RC_N_MASK) == + (TPM_RC_P | TPM_RC_HASH)) { + printk(BIOS_SPEW, "%s: TPM_RC_HASH returned this is" + " expected\n", __func__); + return TPM_SUCCESS; + } + + printk(BIOS_INFO, "%s: response is 0x%x\n", __func__, response ? response->hdr.tpm_code : -1); if (!response || response->hdr.tpm_code) return TPM_E_IOERROR; diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index 991cbcf..b11a9f4 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -79,6 +79,12 @@ space is defined by the lower 16 bits. */ #define TPM_CC_VENDOR_BIT_MASK 0x20000000 +/* Table 15 - TPM_RC Constants (Actions) */ +#define RC_FMT1 (TPM_RC)(0x080) +#define TPM_RC_HASH (TPM_RC)(RC_FMT1 + 0x003) +#define TPM_RC_P (TPM_RC)(0x040) +#define TPM_RC_N_MASK (TPM_RC)(0xF00) + /* Startup values. */ #define TPM_SU_CLEAR 0 #define TPM_SU_STATE 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/33252 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d86c41c23e4e93a84e0527d7cddcfd30d5d8394 Gerrit-Change-Number: 33252 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

6 23

Change in coreboot[master]: cpu/x86/lapic: Refactor timer_fsb()
by Kyösti Mälkki (Code Review) 18 Sep '19

18 Sep '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34091 ) Change subject: cpu/x86/lapic: Refactor timer_fsb() ...................................................................... cpu/x86/lapic: Refactor timer_fsb() Common apic_timer code in cpu/x86 should not depend on intel header files. Change-Id: Ib099921d4b8e561daea47219385762bb00fc4548 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/common/fsb.c M src/cpu/x86/lapic/apic_timer.c M src/include/delay.h 3 files changed, 40 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/34091/1 diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index d66e87a..151ad9e 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -11,12 +11,14 @@ * GNU General Public License for more details. */ +#include <arch/early_variables.h> #include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/fsb.h> #include <console/console.h> #include <commonlib/helpers.h> +#include <delay.h> static int get_fsb(void) { @@ -95,3 +97,23 @@ printk(BIOS_ERR, "FSB not supported or not found\n"); return -1; } + + + +static u32 g_timer_fsb CAR_GLOBAL; + +int set_timer_fsb(void) +{ + int ia32_fsb = get_ia32_fsb(); + + if (ia32_fsb > 0) { + car_set_var(g_timer_fsb, ia32_fsb); + return 0; + } + return -1; +} + +u32 get_timer_fsb(void) +{ + return car_get_var(g_timer_fsb); +} diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c index 6521a8a..2e0583b 100644 --- a/src/cpu/x86/lapic/apic_timer.c +++ b/src/cpu/x86/lapic/apic_timer.c @@ -20,44 +20,8 @@ #include <thread.h> #include <arch/cpu.h> #include <arch/early_variables.h> -#include <cpu/intel/fsb.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> -#include <cpu/intel/speedstep.h> - -/* NOTE: This code uses global variables, so it can not be used during - * memory init. - */ - -#if CONFIG_UDELAY_LAPIC_FIXED_FSB != 0 -static inline u32 get_timer_fsb(void) -{ - return CONFIG_UDELAY_LAPIC_FIXED_FSB; -} - -static int set_timer_fsb(void) -{ - return 0; -} -#else -static u32 g_timer_fsb CAR_GLOBAL; - -static int set_timer_fsb(void) -{ - int ia32_fsb = get_ia32_fsb(); - - if (ia32_fsb > 0) { - car_set_var(g_timer_fsb, ia32_fsb); - return 0; - } - return -1; -} - -static inline u32 get_timer_fsb(void) -{ - return car_get_var(g_timer_fsb); -} -#endif void init_timer(void) { diff --git a/src/include/delay.h b/src/include/delay.h index 8f894d2..acdd374 100644 --- a/src/include/delay.h +++ b/src/include/delay.h @@ -1,6 +1,24 @@ #ifndef DELAY_H #define DELAY_H +#include <stdint.h> + +#if CONFIG_UDELAY_LAPIC_FIXED_FSB != 0 +static inline u32 get_timer_fsb(void) +{ + return CONFIG_UDELAY_LAPIC_FIXED_FSB; +} + +static int set_timer_fsb(void) +{ + return 0; +} +#else +int set_timer_fsb(void); +u32 get_timer_fsb(void); +#endif + + void init_timer(void); void udelay(unsigned int usecs); -- To view, visit https://review.coreboot.org/c/coreboot/+/34091 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib099921d4b8e561daea47219385762bb00fc4548 Gerrit-Change-Number: 34091 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: mb/google/hatch: Remove GPIO_DRIVER from pen eject GPIO configuration
by Tim Wawrzynczak (Code Review) 18 Sep '19

18 Sep '19

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35459 ) Change subject: mb/google/hatch: Remove GPIO_DRIVER from pen eject GPIO configuration ...................................................................... mb/google/hatch: Remove GPIO_DRIVER from pen eject GPIO configuration A closer read of the EDS indicates that when GPIO Driver mode is selected, GPIO input event updates are limited to GPI_STS only. GPI_GPE_STS updates are therefore masked, and we don't want to enable this behavior. It masks the GPE and does not allow us to see this GPE as a wake source, obscuring the reason that the system woke up. BUG=b:132981083 BRANCH=none TEST=Wake up system from S0ix using pen eject, verify that mosys eventlog shows GPE#8 as the S0ix wakeup source. Change-Id: If017e12e23134f5cfed7cbb6047cc9badd9bf7e8 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/35459/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index fcb1a61..1414776 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -31,7 +31,7 @@ /* A7 : PP3300_SOC_A */ PAD_NC(GPP_A7, NONE), /* A8 : PEN_GARAGE_DET_L (wake) */ - PAD_CFG_GPI_GPIO_DRIVER_SCI(GPP_A8, NONE, DEEP, LEVEL, NONE), + PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, LEVEL, NONE), /* A9 : ESPI_CLK */ /* A10 : FPMCU_PCH_BOOT1 */ PAD_CFG_GPO(GPP_A10, 0, DEEP), -- To view, visit https://review.coreboot.org/c/coreboot/+/35459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If017e12e23134f5cfed7cbb6047cc9badd9bf7e8 Gerrit-Change-Number: 35459 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: soc/intel/common/intelblocks: Remove PAD_CFG_GPI_GPIO_DRIVER_SCI
by Tim Wawrzynczak (Code Review) 18 Sep '19

18 Sep '19

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35460 ) Change subject: soc/intel/common/intelblocks: Remove PAD_CFG_GPI_GPIO_DRIVER_SCI ...................................................................... soc/intel/common/intelblocks: Remove PAD_CFG_GPI_GPIO_DRIVER_SCI Intel's EDS says "1 = GPIO Driver Mode. GPIO input event updates are limited to GPI_STS. GPI_GPE_STS, GPI_NMI_STS and/or GPI_SMI_STS updates are masked." Therefore, the GPI_GPIO_DRIVER_SCI option for pad configuration is meaningless, as any GPE will be masked if the GPIO driver is set as owner. Change-Id: Ia0cd0041dfc985cbe388cb89a4026038c7fb4383 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 0 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/35460/1 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index d46e404..15df187 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -411,13 +411,6 @@ PAD_IOSSTATE(TxDRxE)) #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT) -/* GPI, GPIO Driver, SCI interrupt */ -#define PAD_CFG_GPI_GPIO_DRIVER_SCI(pad, pull, rst, trig, inv) \ - _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ - PAD_IRQ_CFG(SCI, trig, inv), \ - PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxDRxE)) - #define PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ -- To view, visit https://review.coreboot.org/c/coreboot/+/35460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia0cd0041dfc985cbe388cb89a4026038c7fb4383 Gerrit-Change-Number: 35460 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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