Hello Patrick Rudolph, Aaron Durbin, dhaval v sharma, Subrata Banik, Patrick Rudolph, Paul Menzel, Duncan Laurie, build bot (Jenkins), Patrick Georgi, Furquan Shaikh, Varshit B Pandya, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/27369
to look at the new patch set (#47).
Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT
......................................................................
soc/intel/basecode: Add support for updating ucode loaded via FIT
Intel’s FIT (Firmware Interface Table) based MCU (microcode/pcode patch)
loading mechanism patches the microcode before CPU reset. In the current
Chromebooks field updatable FW has to be first verified by vboot. Since
the MCU is loaded before reset vboot cannot verify the same and hence we
end up restricting FIT based MCU update only from RO.
This patch implements a scheme which will allow chromebooks to update
MCU in the field.
Create 2 bootblocks (use INTEL_ADD_TOP_SWAP_BOOTBLOCK) each containing their
own FIT table. First bootblock FIT has pointers to MCUs (in microcode_blob.bin)
which resides in RO section. This is will be used in the recovery scenario.
Second bootblock (Normal mode) is identical to the first one except the FIT.
Insert an additional pointer to a MCU that will reside in a staging area.
Use the CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG config to insert the address
of the staging area into FIT.
Top swap control bit in RTC BUC register (0x3414) is used to switch between
the two bootblocks.
Reserve a region in the FMAP which is equal to or greater than the MCU size
specified in the BWG for a particular SoC (e.g., for Skylake/Kaby Lake it is
192K). This is a RW region just like the RW_MRC_CACHE. MCU from RW-A/RW-B will
be copied to this region during boot. Protect this staging area with a FPR.
Basic update flow:
In non-recovery mode, Once a slot has been selected and loaded, check if the
current slot MCU and RW staging MCU are same. If not, update the staging area
with the MCU found in the current slot and reset the system.
Also, make sure that the top-swap is enabled in normal/developer mode and disabled
in recovery mode.
In order to enable the update feature:
* The mainboard chromeos.fmd should include a new region for staging MCU
e.g, RW_UCODE_STAGED.
* Select config TOP_SWAP_BASED_VBOOT_UCODE_UPDATE.
* Implement a call to check_and_update_ucode() and handle the failure
appropriately.
Add documentation to describing the MCU update procedure.
TEST=Create an FW image for soraka and flash, create a chromeos-firmwareupdate
shellball with a newer MCU and perform an update. Make sue that the
currently loaded microcode version matches the one in firmwareupdate.
Change-Id: Iab6ba36a2eb587f331fe522c778e2c430c8eb655
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Signed-off-by: dhaval v sharma <dhaval.v.sharma(a)intel.com>
Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com>
---
M Documentation/soc/intel/index.md
A Documentation/soc/intel/ucode_update/flash_layout.svg
A Documentation/soc/intel/ucode_update/microcode_update_model.md
A src/soc/intel/common/basecode/fw_update/Kconfig
A src/soc/intel/common/basecode/fw_update/Makefile.inc
A src/soc/intel/common/basecode/fw_update/ucode_update.c
A src/soc/intel/common/basecode/include/intelbasecode/ucode_update.h
7 files changed, 644 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/27369/47
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Gerrit-PatchSet: 47
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27369 )
Change subject: soc/intel/basecode: Add support for updating ucode loaded via FIT
......................................................................
Patch Set 46: Code-Review+1
(5 comments)
https://review.coreboot.org/c/coreboot/+/27369/46//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/27369/46//COMMIT_MSG@36
PS46, Line 36: current slot MCU and RW staging MCU are same. If so, update the staging area
why do you need to update the staging area if it's the same microcode?
https://review.coreboot.org/c/coreboot/+/27369/46//COMMIT_MSG@39
PS46, Line 39: Also, make sure that the top is enabled in normal/developer mode and disabled
top swap?
https://review.coreboot.org/c/coreboot/+/27369/46/src/soc/intel/common/base…
File src/soc/intel/common/basecode/fw_update/ucode_update.c:
https://review.coreboot.org/c/coreboot/+/27369/46/src/soc/intel/common/base…
PS46, Line 33: __weak void ucode_update_reboot(void)
I don't see the need for weak here
https://review.coreboot.org/c/coreboot/+/27369/46/src/soc/intel/common/base…
PS46, Line 143: /* Get slot MCU */
why is it called slot?
Isn't it a file in CBFS?
https://review.coreboot.org/c/coreboot/+/27369/46/src/soc/intel/common/base…
PS46, Line 160: /* Compare */
that's clear by memcmp. What do you compare?
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Gerrit-Comment-Date: Thu, 19 Sep 2019 06:46:54 +0000
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Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35459 )
Change subject: mb/google/hatch: Remove GPIO_DRIVER from pen eject GPIO configuration
......................................................................
mb/google/hatch: Remove GPIO_DRIVER from pen eject GPIO configuration
A closer read of the EDS indicates that when GPIO Driver mode is
selected, GPIO input event updates are limited to GPI_STS only.
GPI_GPE_STS updates are therefore masked, and we don't want to enable
this behavior. It masks the GPE and does not allow us to see this GPE
as a wake source, obscuring the reason that the system woke up.
BUG=b:132981083
BRANCH=none
TEST=Wake up system from S0ix using pen eject, verify that mosys
eventlog shows GPE#8 as the S0ix wakeup source.
Change-Id: If017e12e23134f5cfed7cbb6047cc9badd9bf7e8
Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
---
M src/mainboard/google/hatch/variants/baseboard/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/35459/1
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c
index fcb1a61..1414776 100644
--- a/src/mainboard/google/hatch/variants/baseboard/gpio.c
+++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c
@@ -31,7 +31,7 @@
/* A7 : PP3300_SOC_A */
PAD_NC(GPP_A7, NONE),
/* A8 : PEN_GARAGE_DET_L (wake) */
- PAD_CFG_GPI_GPIO_DRIVER_SCI(GPP_A8, NONE, DEEP, LEVEL, NONE),
+ PAD_CFG_GPI_SCI(GPP_A8, NONE, DEEP, LEVEL, NONE),
/* A9 : ESPI_CLK */
/* A10 : FPMCU_PCH_BOOT1 */
PAD_CFG_GPO(GPP_A10, 0, DEEP),
--
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