coreboot-gerrit August 2019

coreboot-gerrit@coreboot.org

1 participants
1942 discussions

Change in coreboot[master]: libpayload: usbmsc: Skip zero-length packets at end of data
by build bot (Jenkins) (Code Review) 21 Aug '19

21 Aug '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34485 ) Change subject: libpayload: usbmsc: Skip zero-length packets at end of data ...................................................................... Patch Set 4: (8 comments) https://review.coreboot.org/c/coreboot/+/34485/4/payloads/libpayload/driver… File payloads/libpayload/drivers/usb/usbmsc.c: https://review.coreboot.org/c/coreboot/+/34485/4/payloads/libpayload/driver… PS4, Line 222: int ret = ctrlr->bulk (ep, sizeof (csw_t), (u8 *) csw, 1); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/c/coreboot/+/34485/4/payloads/libpayload/driver… PS4, Line 222: int ret = ctrlr->bulk (ep, sizeof (csw_t), (u8 *) csw, 1); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/c/coreboot/+/34485/4/payloads/libpayload/driver… PS4, Line 227: ret = ctrlr->bulk (ep, sizeof (csw_t), (u8 *) csw, 1); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/c/coreboot/+/34485/4/payloads/libpayload/driver… PS4, Line 227: ret = ctrlr->bulk (ep, sizeof (csw_t), (u8 *) csw, 1); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/c/coreboot/+/34485/4/payloads/libpayload/driver… PS4, Line 231: if (ctrlr->bulk (ep, sizeof (csw_t), (u8 *) csw, 1) < 0) { space prohibited between function name and open parenthesis '(' https://review.coreboot.org/c/coreboot/+/34485/4/payloads/libpayload/driver… PS4, Line 231: if (ctrlr->bulk (ep, sizeof (csw_t), (u8 *) csw, 1) < 0) { space prohibited between function name and open parenthesis '(' https://review.coreboot.org/c/coreboot/+/34485/4/payloads/libpayload/driver… PS4, Line 231: if (ctrlr->bulk (ep, sizeof (csw_t), (u8 *) csw, 1) < 0) { braces {} are not necessary for single statement blocks https://review.coreboot.org/c/coreboot/+/34485/4/payloads/libpayload/driver… PS4, Line 237: usb_debug ("MSC: received malformed CSW\n"); space prohibited between function name and open parenthesis '(' -- To view, visit https://review.coreboot.org/c/coreboot/+/34485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24f183f27b2c4f0142ba6c4b35b490c5798d0d21 Gerrit-Change-Number: 34485 Gerrit-PatchSet: 4 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Aug 2019 00:07:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: libpayload: usbmsc: Skip zero-length packets at end of data
by Julius Werner (Code Review) 21 Aug '19

21 Aug '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34485 ) Change subject: libpayload: usbmsc: Skip zero-length packets at end of data ...................................................................... Patch Set 4: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/34485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24f183f27b2c4f0142ba6c4b35b490c5798d0d21 Gerrit-Change-Number: 34485 Gerrit-PatchSet: 4 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Aug 2019 00:07:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in libgfxinit[master]: gma pipe setup: Fix secondary pipe cursors <= Sandy Bridge
by Angel Pons (Code Review) 21 Aug '19

21 Aug '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/27154 ) Change subject: gma pipe setup: Fix secondary pipe cursors <= Sandy Bridge ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/libgfxinit/+/27154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I4d79f59a8cb693d73d6da666525f091021efb4fd Gerrit-Change-Number: 27154 Gerrit-PatchSet: 5 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Adrian-Ken Rueegsegger <ken(a)codelabs.ch> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Reto Buerki <reet(a)codelabs.ch> Gerrit-Comment-Date: Tue, 20 Aug 2019 22:35:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in libgfxinit[master]: gfx_test: Refactor to allow Restrictions (No_Elaboration_Code)
by Angel Pons (Code Review) 21 Aug '19

21 Aug '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/27146 ) Change subject: gfx_test: Refactor to allow Restrictions (No_Elaboration_Code) ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/libgfxinit/+/27146 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I63c72501fd7d49574042fc5a459d6751a776a1f1 Gerrit-Change-Number: 27146 Gerrit-PatchSet: 4 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 20 Aug 2019 22:31:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: Makefile.inc, payloads: Enable -Wvla
by Jacob Garber (Code Review) 20 Aug '19

20 Aug '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33846 Change subject: Makefile.inc, payloads: Enable -Wvla ...................................................................... Makefile.inc, payloads: Enable -Wvla Variable length arrays are dangerous, so let's make sure they don't sneak back into coreboot or any of the payloads. Change-Id: Idf2488cf0efab51c9569a3789ae953368b61880c Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> --- M Makefile.inc M payloads/bayou/Makefile M payloads/coreinfo/Makefile M payloads/libpayload/Makefile.inc M payloads/linuxcheck/Makefile M payloads/nvramcui/Makefile 6 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/33846/1 diff --git a/Makefile.inc b/Makefile.inc index 362243e..498674e 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -401,7 +401,7 @@ CFLAGS_common += -pipe -g -nostdinc -std=gnu11 CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs +CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wvla CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time -Wtype-limits CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie diff --git a/payloads/bayou/Makefile b/payloads/bayou/Makefile index 7a4b08b..b893ca7 100644 --- a/payloads/bayou/Makefile +++ b/payloads/bayou/Makefile @@ -39,7 +39,7 @@ OBJECTS-$(CONFIG_NRV2B) += nrv2b.o OBJECTS-$(CONFIG_BUILTIN_LAR) += builtin-lar.o -CFLAGS= -Wall -Werror -Os $(FFLAGS-y) +CFLAGS= -Wall -Wvla -Werror -Os $(FFLAGS-y) LDFLAGS=-Wl,-T,bayou.ldscript -static LIBGCC=$(shell $(CC) -m32 -print-libgcc-file-name) diff --git a/payloads/coreinfo/Makefile b/payloads/coreinfo/Makefile index 50659d3..bcc5354 100644 --- a/payloads/coreinfo/Makefile +++ b/payloads/coreinfo/Makefile @@ -83,7 +83,7 @@ LPCC := CC="$(CC)" $(LIBPAYLOAD_OBJ)/bin/lpgcc LPAS := AS="$(AS)" $(LIBPAYLOAD_OBJ)/bin/lpas -CFLAGS += -Wall -Werror -Os -fno-builtin $(CFLAGS_$(ARCH-y)) $(INCLUDES) +CFLAGS += -Wall -Wvla -Werror -Os -fno-builtin $(CFLAGS_$(ARCH-y)) $(INCLUDES) ifneq ($(strip $(HAVE_DOTCONFIG)),) include $(src)/.config diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index 7787762..aae3921 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -63,7 +63,7 @@ CFLAGS += -nostdlib -fno-builtin -ffreestanding -fomit-frame-pointer CFLAGS += -ffunction-sections -fdata-sections CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs +CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wvla CFLAGS += -Wstrict-aliasing -Wshadow -Werror $(obj)/libpayload-config.h: $(KCONFIG_AUTOHEADER) diff --git a/payloads/linuxcheck/Makefile b/payloads/linuxcheck/Makefile index b967369..838c90d 100644 --- a/payloads/linuxcheck/Makefile +++ b/payloads/linuxcheck/Makefile @@ -3,7 +3,7 @@ # build libpayload and put .config file in $(CURDIR) instead of ../libpayload # to avoid pollute the libpayload source directory and possible conflicts LPOPTS=obj="$(CURDIR)/build" DESTDIR="$(CURDIR)" DOTCONFIG="$(CURDIR)/.config" -CFLAGS += -Wall -Werror -Os -ffreestanding -nostdinc -nostdlib +CFLAGS += -Wall -Wvla -Werror -Os -ffreestanding -nostdinc -nostdlib ifeq ($(CONFIG_ARCH_X86),y) TARGETARCH = i386 endif diff --git a/payloads/nvramcui/Makefile b/payloads/nvramcui/Makefile index c6a9cd0..bf7053b 100644 --- a/payloads/nvramcui/Makefile +++ b/payloads/nvramcui/Makefile @@ -3,7 +3,7 @@ # build libpayload and put .config file in $(CURDIR) instead of ../libpayload # to avoid pollute the libpayload source directory and possible conflicts LPOPTS=obj="$(CURDIR)/build" DESTDIR="$(CURDIR)" DOTCONFIG="$(CURDIR)/.config" -CFLAGS += -Wall -Werror -Os -ffreestanding -nostdinc -nostdlib +CFLAGS += -Wall -Wvla -Werror -Os -ffreestanding -nostdinc -nostdlib all: nvramcui.elf -- To view, visit https://review.coreboot.org/c/coreboot/+/33846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf2488cf0efab51c9569a3789ae953368b61880c Gerrit-Change-Number: 33846 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

4 13

Change in ...coreboot[master]: nb/via/vx900: Use 64 bits to prevent overflow
by Jacob Garber (Code Review) 20 Aug '19

20 Aug '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32291 Change subject: nb/via/vx900: Use 64 bits to prevent overflow ...................................................................... nb/via/vx900: Use 64 bits to prevent overflow The bit operations are currently done using 32 bit math. Cast the first argument to 64 bits to prevent possible overflow. Found-by: Coverity Scan, CID 1229665, 1229666 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Change-Id: Idd180f31e8cff797a6499b12bc685daa993aae05 --- M src/northbridge/via/vx900/northbridge.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/32291/1 diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c index d865f38..dcb7fd5 100644 --- a/src/northbridge/via/vx900/northbridge.c +++ b/src/northbridge/via/vx900/northbridge.c @@ -266,8 +266,8 @@ * to be always mapped to the top of 1M, but this can be overcome with * some smart positive/subtractive resource decoding */ ram_resource(dev, idx++, 768, (tolmk - 768)); - uma_memory_size = fbufk << 10; - uma_memory_base = tolmk << 10; + uma_memory_size = (uint64_t)fbufk << 10; + uma_memory_base = (uint64_t)tolmk << 10; //uma_resource(dev, idx++, uma_memory_base>>10, uma_memory_size>>10); -- To view, visit https://review.coreboot.org/c/coreboot/+/32291 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd180f31e8cff797a6499b12bc685daa993aae05 Gerrit-Change-Number: 32291 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: mb/ocp/monolake: Add IPMI CMOS clear support
by Johnny Lin (Code Review) 20 Aug '19

20 Aug '19

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34857 ) Change subject: mb/ocp/monolake: Add IPMI CMOS clear support ...................................................................... mb/ocp/monolake: Add IPMI CMOS clear support coreboot would clear CMOS by request via IPMI command, for example BMC can issue "bios-util server --boot_order enable --clear_CMOS" to set the request and reboot the system, then coreboot would clear CMOS on the next boot. Tested on Mono Lake Change-Id: I21d44557896680cfac3c3b6d83e07b755b242cad --- M src/mainboard/ocp/monolake/Kconfig M src/mainboard/ocp/monolake/Makefile.inc A src/mainboard/ocp/monolake/ipmi.c A src/mainboard/ocp/monolake/ipmi.h M src/mainboard/ocp/monolake/mainboard.c 5 files changed, 147 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/34857/1 diff --git a/src/mainboard/ocp/monolake/Kconfig b/src/mainboard/ocp/monolake/Kconfig index 13d7876..c55c84e 100644 --- a/src/mainboard/ocp/monolake/Kconfig +++ b/src/mainboard/ocp/monolake/Kconfig @@ -12,6 +12,7 @@ select MAINBOARD_USES_IFD_GBE_REGION select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_TPM1 + select IPMI_KCS config INTEGRATED_UART def_bool n diff --git a/src/mainboard/ocp/monolake/Makefile.inc b/src/mainboard/ocp/monolake/Makefile.inc index 1606476..b6a26b0 100644 --- a/src/mainboard/ocp/monolake/Makefile.inc +++ b/src/mainboard/ocp/monolake/Makefile.inc @@ -14,3 +14,4 @@ ## ramstage-y += irqroute.c +ramstage-y += ipmi.c diff --git a/src/mainboard/ocp/monolake/ipmi.c b/src/mainboard/ocp/monolake/ipmi.c new file mode 100755 index 0000000..84530e1 --- /dev/null +++ b/src/mainboard/ocp/monolake/ipmi.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Wiwynn Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <stdint.h> +#include <drivers/ipmi/ipmi_kcs.h> +#include <console/console.h> +#include "ipmi.h" + +#define BMC_KCS_BASE 0xca2 + +int is_ipmi_clear_cmos_set(ipmi_oem_rsp_t *rsp) +{ + int ret; + ipmi_oem_req_t req; + + if (rsp == NULL) { + printk(BIOS_ERR, "%s failed, null pointer parameter\n", + __func__); + return 0; + } + ret = ipmi_kcs_message(BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, + IPMI_OEM_GET_BIOS_BOOT_ORDER, + (const unsigned char *) &req, sizeof(ipmi_oem_req_t), + (unsigned char *) rsp, sizeof(ipmi_oem_rsp_t)); + + if (ret < sizeof(struct ipmi_rsp) || rsp->CompletionCode) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp->CompletionCode); + return 0; + } + + if (rsp->Data.Valid && rsp->Data.CmosClear) { + printk(BIOS_INFO, "IPMI CMOS clear requested\n"); + return 1; + } + + printk(BIOS_DEBUG, "IPMI CMOS clear is not set\n"); + return 0; +} + +void clear_ipmi_flags(ipmi_oem_rsp_t *rsp_get) +{ + int ret; + ipmi_oem_req_t req; + struct ipmi_rsp rsp; + + if (rsp_get == NULL) { + printk(BIOS_ERR, "%s failed, null pointer parameter\n", + __func__); + return; + } + + req = rsp_get->Data; + req.CmosClear = 0; + req.Valid = 0; + ret = ipmi_kcs_message(BMC_KCS_BASE, IPMI_NETFN_OEM, 0x0, + IPMI_OEM_SET_BIOS_BOOT_ORDER, + (const unsigned char *) &req, sizeof(ipmi_oem_req_t), + (unsigned char *) &rsp, sizeof(rsp)); + + if (ret < sizeof(struct ipmi_rsp) || rsp.completion_code) { + printk(BIOS_ERR, "IPMI: %s command failed (ret=%d resp=0x%x)\n", + __func__, ret, rsp.completion_code); + return; + } + + printk(BIOS_INFO, "clear IPMI flags done\n"); +} diff --git a/src/mainboard/ocp/monolake/ipmi.h b/src/mainboard/ocp/monolake/ipmi.h new file mode 100644 index 0000000..ef4fbd3 --- /dev/null +++ b/src/mainboard/ocp/monolake/ipmi.h @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Wiwynn Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MONOLAKE_IPMI_H +#define MONOLAKE_IPMI_H + +#define IPMI_NETFN_OEM 0x30 +#define IPMI_OEM_SET_BIOS_BOOT_ORDER 0x52 +#define IPMI_OEM_GET_BIOS_BOOT_ORDER 0x53 + +typedef struct { + u8 BiosType:1; + u8 CmosClear:1; + u8 ForceBiosSetup:1; + u8 Reserved:4; + u8 Valid:1; + u8 Boot0000; + u8 Boot0001; + u8 Boot0002; + u8 Boot0003; + u8 Boot0004; +} __packed ipmi_oem_req_t; + +typedef struct { + u16 KcsRsp; + u8 CompletionCode; + ipmi_oem_req_t Data; +} __packed ipmi_oem_rsp_t; + +/* + * IPMI get response to check if Valid and CMOS clear bit + * are both set and store the IPMI response data to the parameter. + */ +int is_ipmi_clear_cmos_set(ipmi_oem_rsp_t *rsp); +/* + * Clear Valid bit and CMOS clear bit from the parameter + * and set it back via IPMI. + */ +void clear_ipmi_flags(ipmi_oem_rsp_t *rsp); + +#endif + diff --git a/src/mainboard/ocp/monolake/mainboard.c b/src/mainboard/ocp/monolake/mainboard.c index bbfeeaf..56aef6b 100644 --- a/src/mainboard/ocp/monolake/mainboard.c +++ b/src/mainboard/ocp/monolake/mainboard.c @@ -19,6 +19,9 @@ #if CONFIG(VGA_ROM_RUN) #include <x86emu/x86emu.h> #endif +#include <pc80/mc146818rtc.h> +#include <cf9_reset.h> +#include "ipmi.h" #define BMC_KCS_BASE 0xca2 #define INTERFACE_IS_IO 0x1 @@ -57,9 +60,18 @@ /* Enable access to the BMC IPMI via KCS */ struct device *lpc_sio_dev = dev_find_slot_pnp(BMC_KCS_BASE, 0); struct resource *res = new_resource(lpc_sio_dev, BMC_KCS_BASE); + ipmi_oem_rsp_t rsp; res->base = BMC_KCS_BASE; res->size = 1; res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + if (is_ipmi_clear_cmos_set(&rsp)) { + /* TODO: Should also try to restore CMOS to cmos.default + * if USE_OPTION_TABLE is set */ + cmos_init(1); + clear_ipmi_flags(&rsp); + system_reset(); + } } struct chip_operations mainboard_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/34857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21d44557896680cfac3c3b6d83e07b755b242cad Gerrit-Change-Number: 34857 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin Gerrit-MessageType: newchange

3 14

Change in coreboot[master]: mb/google/hatch: Skip SD card controller WP pin configuration from FSP
by Aamir Bohra (Code Review) 20 Aug '19

20 Aug '19

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34901 ) Change subject: mb/google/hatch: Skip SD card controller WP pin configuration from FSP ...................................................................... mb/google/hatch: Skip SD card controller WP pin configuration from FSP BUG=b:123907904 TEST=SD WP GPIO PAD retains coreboot configuration and FSP ScsSdCardWpPinEnabled UPD is set to 0. Change-Id: I30367cda09cc8c88abb649f70b4587889083f9af Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/34901/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index c87a8bc..8b5fc1a 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -46,6 +46,8 @@ register "tcc_offset" = "10" # TCC of 90C # Unlock GPIO pads register "PchUnlockGpioPads" = "1" + # SD card WP pin confguration + register "ScsSdCardWpPinEnabled" = "0" # NOTE: if any variant wants to override this value, use the same format # as register "common_soc_config.pch_thermal_trip" = "value", instead of -- To view, visit https://review.coreboot.org/c/coreboot/+/34901 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30367cda09cc8c88abb649f70b4587889083f9af Gerrit-Change-Number: 34901 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: soc/intel/cnl: Add provision to configure SD controller write protect...
by Aamir Bohra (Code Review) 20 Aug '19

20 Aug '19

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34900 ) Change subject: soc/intel/cnl: Add provision to configure SD controller write protect pin ...................................................................... soc/intel/cnl: Add provision to configure SD controller write protect pin FSP allows provison to configure SD controller WP pin, however some of board design might choose not to use the SD WP pin from SD card controller. This implementation adds a config that allows to enable /disable SD controller WP pin configuration from FSP. Change-Id: Ic1736a2ec4b9370d23a8e3349603eb363e6f59b9 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/34900/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 71aa208..4056817 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -186,6 +186,8 @@ uint8_t EmmcHs400RxStrobeDll1; /* 0-78: number of active delay for TX data, unit is 125 psec */ uint8_t EmmcHs400TxDataDll; + /* Enable/disable SD Card Write Protect Pin */ + uint8_t ScsSdCardWpPinEnabled; /* Integrated Sensor */ uint8_t PchIshEnable; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 0f27c47..612e582 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -336,6 +336,7 @@ params->ScsSdCardEnabled = dev->enabled; params->SdCardPowerEnableActiveHigh = CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE); + params->ScsSdCardWpPinEnabled = config->ScsSdCardWpPinEnabled; } dev = pcidev_path_on_root(PCH_DEVFN_UFS); -- To view, visit https://review.coreboot.org/c/coreboot/+/34900 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1736a2ec4b9370d23a8e3349603eb363e6f59b9 Gerrit-Change-Number: 34900 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

4 11

Change in coreboot[master]: intel/apollolake: Move LPC decode enables to bootblock
by Kyösti Mälkki (Code Review) 20 Aug '19

20 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34969 ) Change subject: intel/apollolake: Move LPC decode enables to bootblock ...................................................................... intel/apollolake: Move LPC decode enables to bootblock Doing this allows to call console_init() earlier in romstage. This also fixes IO UART in bootblock, although it appears there is currently no board that was affected. Change-Id: Iec363a8c651cc1b05b24229db09d686938118f3a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/romstage.c 2 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/34969/1 diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 7b4eaef..f86c18e 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -21,6 +21,7 @@ #include <device/pci_ops.h> #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/lpc_lib.h> #include <intelblocks/p2sb.h> #include <intelblocks/pcr.h> #include <intelblocks/rtc.h> @@ -96,6 +97,8 @@ /* Prepare UART for serial console. */ if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) uart_bootblock_init(); + if (CONFIG(DRIVERS_UART_8250IO)) + lpc_io_setup_comm_a_b(); if (CONFIG(TPM_ON_FAST_SPI)) tpm_enable(); diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 3178dbf..1464d2c 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -92,9 +92,6 @@ /* Enable decoding for HPET. Needed for FSP global pointer storage */ pci_write_config8(PCH_DEV_P2SB, P2SB_HPTC, P2SB_HPTC_ADDRESS_SELECT_0 | P2SB_HPTC_ADDRESS_ENABLE); - - if (CONFIG(DRIVERS_UART_8250IO)) - lpc_io_setup_comm_a_b(); } /* Thermal throttle activation offset */ @@ -208,10 +205,10 @@ timestamp_add_now(TS_START_ROMSTAGE); - soc_early_romstage_init(); - console_init(); + soc_early_romstage_init(); + s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); -- To view, visit https://review.coreboot.org/c/coreboot/+/34969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec363a8c651cc1b05b24229db09d686938118f3a Gerrit-Change-Number: 34969 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

4 4

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2019