coreboot-gerrit August 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: AMD fam10: Remove HAVE_ACPI_RESUME support
by Kyösti Mälkki (Code Review) 21 Aug '19

21 Aug '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/15474 ) Change subject: AMD fam10: Remove HAVE_ACPI_RESUME support ...................................................................... Patch Set 13: Thanks! Although somebody on the mailing list just asked how to produce the logs, at least I can say it was not me who pulled the trigger :) -- To view, visit https://review.coreboot.org/c/coreboot/+/15474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62bbba8cfe515b3cae413582ff8d062a20e6741b Gerrit-Change-Number: 15474 Gerrit-PatchSet: 13 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Gerrit-Reviewer: Rudolf Marek <r.marek(a)assembler.cz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Aug 2019 09:47:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [WIP]payloads/tianocore: Enable UEFIPayload
by Lance Zhao (Code Review) 21 Aug '19

21 Aug '19

Hello Lijian Zhao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34459 to review the following change. Change subject: [WIP]payloads/tianocore: Enable UEFIPayload ...................................................................... [WIP]payloads/tianocore: Enable UEFIPayload Corebootpayload package in upstream tianocore had been replaced with UEFIPayload, make the changes in coreboot side as well. BUG=N/A TEST=Able to build with tianocore debug and release build. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I0b7785fde9f4113b2cd91323ac0358b229c5a6e6 --- M payloads/external/tianocore/Makefile 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/34459/1 diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index f208e59..727aa22 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -39,9 +39,9 @@ endif ifeq ($(CONFIG_TIANOCORE_TARGET_IA32), y) - BUILD_STR=-a IA32 -t COREBOOT -p CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc -b $(BUILD_TYPE) $(TIMER) + BUILD_STR=-a IA32 -t COREBOOT -p UefiPayloadPkg/UefiPayloadPkgIa32.dsc -b $(BUILD_TYPE) $(TIMER) -D BOOTLOADER=COREBOOT else - BUILD_STR=-a IA32 -a X64 -t COREBOOT -p CorebootPayloadPkg/CorebootPayloadPkgIa32X64.dsc -b $(BUILD_TYPE) $(TIMER) + BUILD_STR=-a IA32 -a X64 -t COREBOOT -p UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc -b $(BUILD_TYPE) $(TIMER) -D BOOTLOADER=COREBOOT endif all: clean build @@ -85,9 +85,9 @@ echo " Copying custom bootsplash image"; \ case "$(CONFIG_TIANOCORE_BOOTSPLASH_FILE)" in \ /*) cp $(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \ - $(project_dir)/CorebootPayloadPkg/Logo/Logo.bmp;; \ + $(project_dir)/UefiPayloadPkg/Logo/Logo.bmp;; \ *) cp $(top)/$(CONFIG_TIANOCORE_BOOTSPLASH_FILE) \ - $(project_dir)/CorebootPayloadPkg/Logo/Logo.bmp;; \ + $(project_dir)/UefiPayloadPkg/Logo/Logo.bmp;; \ esac \ fi; \ cd $(project_dir); \ @@ -99,8 +99,8 @@ cat ../tools_def.txt >> $(project_dir)/Conf/tools_def.txt; \ fi; \ build $(BUILD_STR); \ - mv $(project_dir)/Build/CorebootPayloadPkg*/*/FV/UEFIPAYLOAD.fd $(project_dir)/Build/UEFIPAYLOAD.fd; \ - git checkout CorebootPayloadPkg/Logo/Logo.bmp > /dev/null 2>&1 || true + mv $(project_dir)/Build/UefiPayloadPkg*/*/FV/UEFIPAYLOAD.fd $(project_dir)/Build/UEFIPAYLOAD.fd; \ + git checkout UefiPayloadPkg/Logo/Logo.bmp > /dev/null 2>&1 || true clean: test -d $(project_dir) && (cd $(project_dir); rm -rf Build; rm -f Conf/tools_def.txt) || exit 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/34459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b7785fde9f4113b2cd91323ac0358b229c5a6e6 Gerrit-Change-Number: 34459 Gerrit-PatchSet: 1 Gerrit-Owner: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/smm: Remove redundant masking op
by Tim Wawrzynczak (Code Review) 21 Aug '19

21 Aug '19

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34797 ) Change subject: soc/intel/common/smm: Remove redundant masking op ...................................................................... soc/intel/common/smm: Remove redundant masking op The next operation using the 'data' variable after the offending mask op is a read, indicating the masking op is not unused. Change-Id: I71da74e5e08e7d7e6d61c1925db19324efd73f0a Found-by: Coverity CID 1381621 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/common/block/smm/smitraphandler.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/34797/1 diff --git a/src/soc/intel/common/block/smm/smitraphandler.c b/src/soc/intel/common/block/smm/smitraphandler.c index bfa9846..e71e00c2 100644 --- a/src/soc/intel/common/block/smm/smitraphandler.c +++ b/src/soc/intel/common/block/smm/smitraphandler.c @@ -107,7 +107,6 @@ printk(BIOS_DEBUG, "SMI1 command\n"); /* Trapped write data */ data = pcr_read32(PID_PSTH, PCR_PSTH_TRPD); - data &= mask; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/34797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I71da74e5e08e7d7e6d61c1925db19324efd73f0a Gerrit-Change-Number: 34797 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

5 10

Change in coreboot[master]: vboot: update vboot2 functions to use new vb2_error_t
by Joel Kitching (Code Review) 21 Aug '19

21 Aug '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34860 ) Change subject: vboot: update vboot2 functions to use new vb2_error_t ...................................................................... vboot: update vboot2 functions to use new vb2_error_t To make explicit when vboot2 error codes should be returned, use the new vb2_error_t type on all functions which return VB2_ERROR_* constants. NOTE: This patch was merged separately on the Chromium tree: https://chromium-review.googlesource.com/c/1728499 BUG=b:124141368, chromium:988410 TEST=make clean && make test-abuild BRANCH=none Change-Id: I804c2b407e496d0c8eb9833be629b7c40118415c Signed-off-by: Joel Kitching <kitching(a)google.com> Cq-Depend: chromium:1728292 --- M src/security/vboot/secdata_mock.c M src/security/vboot/secdata_tpm.c M src/security/vboot/tpm_common.c M src/security/vboot/tpm_common.h M src/security/vboot/vboot_logic.c M src/soc/rockchip/rk3288/crypto.c 6 files changed, 34 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/34860/1 diff --git a/src/security/vboot/secdata_mock.c b/src/security/vboot/secdata_mock.c index 43206df..de58bf5 100644 --- a/src/security/vboot/secdata_mock.c +++ b/src/security/vboot/secdata_mock.c @@ -38,38 +38,39 @@ #include "antirollback.h" -int vb2ex_tpm_clear_owner(struct vb2_context *ctx) +vb2_error_t vb2ex_tpm_clear_owner(struct vb2_context *ctx) { return VB2_SUCCESS; } -uint32_t antirollback_read_space_firmware(struct vb2_context *ctx) +vb2_error_t antirollback_read_space_firmware(struct vb2_context *ctx) { vb2api_secdata_create(ctx); return VB2_SUCCESS; } -uint32_t antirollback_write_space_firmware(struct vb2_context *ctx) +vb2_error_t antirollback_write_space_firmware(struct vb2_context *ctx) { return VB2_SUCCESS; } -uint32_t antirollback_lock_space_firmware(void) +vb2_error_t antirollback_lock_space_firmware(void) { return VB2_SUCCESS; } -uint32_t antirollback_lock_space_rec_hash(void) +vb2_error_t antirollback_lock_space_rec_hash(void) { return VB2_SUCCESS; } -uint32_t antirollback_read_space_rec_hash(uint8_t *data, uint32_t size) +vb2_error_t antirollback_read_space_rec_hash(uint8_t *data, uint32_t size) { return VB2_SUCCESS; } -uint32_t antirollback_write_space_rec_hash(const uint8_t *data, uint32_t size) +vb2_error_t antirollback_write_space_rec_hash(const uint8_t *data, + uint32_t size) { return VB2_SUCCESS; } diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 09c7e72..1dec0ca 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -486,7 +486,7 @@ return write_secdata(REC_HASH_NV_INDEX, data, size); } -int vb2ex_tpm_clear_owner(struct vb2_context *ctx) +vb2_error_t vb2ex_tpm_clear_owner(struct vb2_context *ctx) { uint32_t rv; printk(BIOS_INFO, "Clearing TPM owner\n"); diff --git a/src/security/vboot/tpm_common.c b/src/security/vboot/tpm_common.c index 1a07ef6..1db7189 100644 --- a/src/security/vboot/tpm_common.c +++ b/src/security/vboot/tpm_common.c @@ -30,12 +30,12 @@ return result; } -uint32_t vboot_extend_pcr(struct vb2_context *ctx, int pcr, - enum vb2_pcr_digest which_digest) +vb2_error_t vboot_extend_pcr(struct vb2_context *ctx, int pcr, + enum vb2_pcr_digest which_digest) { uint8_t buffer[VB2_PCR_DIGEST_RECOMMENDED_SIZE]; uint32_t size = sizeof(buffer); - int rv; + vb2_error_t rv; rv = vb2api_get_pcr_digest(ctx, which_digest, buffer, &size); if (rv != VB2_SUCCESS) diff --git a/src/security/vboot/tpm_common.h b/src/security/vboot/tpm_common.h index 6bb32bb..e1faa0c 100644 --- a/src/security/vboot/tpm_common.h +++ b/src/security/vboot/tpm_common.h @@ -17,8 +17,8 @@ uint32_t vboot_setup_tpm(struct vb2_context *ctx); /* vboot_extend_pcr function for vb2 context */ -uint32_t vboot_extend_pcr(struct vb2_context *ctx, int pcr, - enum vb2_pcr_digest which_digest); +vb2_error_t vboot_extend_pcr(struct vb2_context *ctx, int pcr, + enum vb2_pcr_digest which_digest); #else diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 7f00df5..d049740 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -55,11 +55,11 @@ return; } -int vb2ex_read_resource(struct vb2_context *ctx, - enum vb2_resource_index index, - uint32_t offset, - void *buf, - uint32_t size) +vb2_error_t vb2ex_read_resource(struct vb2_context *ctx, + enum vb2_resource_index index, + uint32_t offset, + void *buf, + uint32_t size) { struct region_device rdev; const char *name; @@ -88,19 +88,21 @@ } /* No-op stubs that can be overridden by SoCs with hardware crypto support. */ -__weak int vb2ex_hwcrypto_digest_init(enum vb2_hash_algorithm hash_alg, - uint32_t data_size) +__weak vb2_error_t vb2ex_hwcrypto_digest_init(enum vb2_hash_algorithm hash_alg, + uint32_t data_size) { return VB2_ERROR_EX_HWCRYPTO_UNSUPPORTED; } -__weak int vb2ex_hwcrypto_digest_extend(const uint8_t *buf, uint32_t size) +__weak vb2_error_t vb2ex_hwcrypto_digest_extend(const uint8_t *buf, + uint32_t size) { BUG(); /* Should never get called if init() returned an error. */ return VB2_ERROR_UNKNOWN; } -__weak int vb2ex_hwcrypto_digest_finalize(uint8_t *digest, uint32_t digest_size) +__weak vb2_error_t vb2ex_hwcrypto_digest_finalize(uint8_t *digest, + uint32_t digest_size) { BUG(); /* Should never get called if init() returned an error. */ return VB2_ERROR_UNKNOWN; @@ -169,7 +171,8 @@ return 0; } -static int hash_body(struct vb2_context *ctx, struct region_device *fw_main) +static vb2_error_t hash_body(struct vb2_context *ctx, + struct region_device *fw_main) { uint64_t load_ts; uint32_t expected_size; @@ -178,7 +181,7 @@ const size_t hash_digest_sz = sizeof(hash_digest); size_t block_size = sizeof(block); size_t offset; - int rv; + vb2_error_t rv; /* Clear the full digest so that any hash digests less than the * max have trailing zeros. */ @@ -313,7 +316,7 @@ { struct vb2_context ctx; struct region_device fw_main; - int rv; + vb2_error_t rv; timestamp_add_now(TS_START_VBOOT); diff --git a/src/soc/rockchip/rk3288/crypto.c b/src/soc/rockchip/rk3288/crypto.c index c429258..00885bc 100644 --- a/src/soc/rockchip/rk3288/crypto.c +++ b/src/soc/rockchip/rk3288/crypto.c @@ -68,8 +68,8 @@ } *crypto = (void *)CRYPTO_BASE; check_member(rk3288_crypto, trng_dout[7], 0x220); -int vb2ex_hwcrypto_digest_init(enum vb2_hash_algorithm hash_alg, - uint32_t data_size) +vb2_error_t vb2ex_hwcrypto_digest_init(enum vb2_hash_algorithm hash_alg, + uint32_t data_size) { if (hash_alg != VB2_HASH_SHA256) { printk(BIOS_INFO, "RK3288 doesn't support hash_alg %d!\n", @@ -94,7 +94,7 @@ return VB2_SUCCESS; } -int vb2ex_hwcrypto_digest_extend(const uint8_t *buf, uint32_t size) +vb2_error_t vb2ex_hwcrypto_digest_extend(const uint8_t *buf, uint32_t size) { uint32_t intsts; @@ -115,7 +115,8 @@ return VB2_SUCCESS; } -int vb2ex_hwcrypto_digest_finalize(uint8_t *digest, uint32_t digest_size) +vb2_error_t vb2ex_hwcrypto_digest_finalize(uint8_t *digest, + uint32_t digest_size) { uint32_t *dest = (uint32_t *)digest; uint32_t *src = crypto->hash_dout; -- To view, visit https://review.coreboot.org/c/coreboot/+/34860 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I804c2b407e496d0c8eb9833be629b7c40118415c Gerrit-Change-Number: 34860 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: Update vboot submodule to upstream master
by Joel Kitching (Code Review) 21 Aug '19

21 Aug '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34859 ) Change subject: Update vboot submodule to upstream master ...................................................................... Update vboot submodule to upstream master Updating from commit id 9c906110: 2019-08-06 06:07:01 +0000 - (vboot/tpm: fix return type inconsistencies) to commit id 7ad9f519: 2019-08-13 08:27:53 +0000 - (vboot/secdata: remove retries from rollback functions) This brings in 13 new commits. Change-Id: Ic334ce8a5f24a0119fa2aaf000ce76c4c9e4932a Signed-off-by: Joel Kitching <kitching(a)google.com> --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/34859/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index 9c90611..7ad9f51 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 9c906110972f538ee5753845916ebd1f826f54b6 +Subproject commit 7ad9f51996d9d950dfbf6c11c82144f7026a68aa -- To view, visit https://review.coreboot.org/c/coreboot/+/34859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic334ce8a5f24a0119fa2aaf000ce76c4c9e4932a Gerrit-Change-Number: 34859 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: soc/intel/common: use PAD_BUF() inside PAD_CFG_* macros
by Maxim Polyakov (Code Review) 21 Aug '19

21 Aug '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34844 ) Change subject: soc/intel/common: use PAD_BUF() inside PAD_CFG_* macros ...................................................................... soc/intel/common: use PAD_BUF() inside PAD_CFG_* macros Use PAD_BUF() to disable the input/output buffer inside PAD_CFG_* macros instead PAD_CFG0_RX_DISABLE/PAD_CFG0_TX_DISABLE [1] https://review.coreboot.org/c/coreboot/+/34337 Change-Id: I19fd993e1f60d80eab0ce51eaed5e74ce1c6a34d Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 24 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/34844/1 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 0c52f7d..d46e404 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -228,34 +228,34 @@ #define PAD_CFG_GPO(pad, val, rst) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_CFG0_TRIG_OFF | PAD_BUF(RX_DISABLE) | !!val, \ PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE)) /* General purpose output, with termination specified */ #define PAD_CFG_TERM_GPO(pad, val, pull, rst) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_CFG0_TRIG_OFF | PAD_BUF(RX_DISABLE) | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) /* General purpose output, no pullup/down. */ #define PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_CFG0_TRIG_OFF | PAD_BUF(RX_DISABLE) | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | PAD_CFG1_GPIO_DRIVER) /* General purpose output. */ #define PAD_CFG_GPO_IOSSTATE_IOSTERM(pad, val, rst, pull, iosstate, ioterm) \ _PAD_CFG_STRUCT(pad, \ PAD_FUNC(GPIO) | PAD_RESET(rst) | \ - PAD_CFG0_TRIG_OFF | PAD_CFG0_RX_DISABLE | !!val, \ + PAD_CFG0_TRIG_OFF | PAD_BUF(RX_DISABLE) | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(ioterm)) /* General purpose input */ #define PAD_CFG_GPI(pad, pull, rst) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) /* General purpose input. The following macro sets the @@ -263,26 +263,24 @@ */ #define PAD_CFG_GPI_GPIO_DRIVER(pad, pull, rst) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE), \ PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxDRxE)) #define PAD_CFG_GPIO_DRIVER_HI_Z(pad, pull, rst, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ - PAD_CFG0_RX_DISABLE, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_RX_DISABLE), \ PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | \ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) #define PAD_CFG_GPIO_HI_Z(pad, pull, rst, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ - PAD_CFG0_RX_DISABLE, PAD_PULL(pull) | \ - PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_RX_DISABLE), \ + PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) /* GPIO Interrupt */ #define PAD_CFG_GPI_INT(pad, pull, rst, trig) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_CFG0_TRIG_##trig | PAD_CFG0_RX_POL_NONE, \ PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxDRxE)) @@ -293,20 +291,20 @@ */ #define PAD_NC(pad, pull) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | \ - PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE, \ + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | \ + PAD_CFG0_TRIG_OFF | PAD_BUF(TX_RX_DISABLE), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) #if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS) #define PAD_CFG_GPI_APIC(pad, pull, rst) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_IRQ_CFG(IOAPIC, LEVEL, NONE), PAD_PULL(pull)) #define PAD_CFG_GPI_APIC_INVERT(pad, pull, rst) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_IRQ_CFG(IOAPIC, LEVEL, INVERT), PAD_PULL(pull)) #define PAD_CFG_GPI_ACPI_SCI(pad, pull, rst, inv) \ @@ -327,7 +325,7 @@ /* General purpose input, routed to APIC */ #define PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE)) #endif @@ -335,7 +333,7 @@ /* General purpose input, routed to APIC - with IOStandby Config*/ #define PAD_CFG_GPI_APIC_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_IRQ_CFG(IOAPIC, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) @@ -356,14 +354,14 @@ /* General purpose input, routed to SMI */ #define PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE)) /* General purpose input, routed to SMI */ #define PAD_CFG_GPI_SMI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_IRQ_CFG(SMI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) @@ -376,14 +374,14 @@ /* General purpose input, routed to SCI */ #define PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE)) /* General purpose input, routed to SCI */ #define PAD_CFG_GPI_SCI_IOS(pad, pull, rst, trig, inv, iosstate, iosterm) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) @@ -395,7 +393,7 @@ #define PAD_CFG_GPI_SCI_DEBEN(pad, pull, rst, trig, inv, dur) \ _PAD_CFG_STRUCT_3(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_IRQ_CFG(SCI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE), PAD_CFG2_DEBEN | PAD_CFG2_##dur) @@ -408,7 +406,7 @@ /* General purpose input, routed to NMI */ #define PAD_CFG_GPI_NMI(pad, pull, rst, trig, inv) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_IRQ_CFG(NMI, trig, inv), PAD_PULL(pull) | \ PAD_IOSSTATE(TxDRxE)) @@ -416,13 +414,13 @@ /* GPI, GPIO Driver, SCI interrupt */ #define PAD_CFG_GPI_GPIO_DRIVER_SCI(pad, pull, rst, trig, inv) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_IRQ_CFG(SCI, trig, inv), \ PAD_PULL(pull) | PAD_CFG1_GPIO_DRIVER | PAD_IOSSTATE(TxDRxE)) #define PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE | \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_BUF(TX_DISABLE) | \ PAD_IRQ_CFG_DUAL_ROUTE(route1, route2, trig, inv), \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) -- To view, visit https://review.coreboot.org/c/coreboot/+/34844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19fd993e1f60d80eab0ce51eaed5e74ce1c6a34d Gerrit-Change-Number: 34844 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: soc/intel/common: gpio_defs: set trig to disable in PAD_NC
by Maxim Polyakov (Code Review) 21 Aug '19

21 Aug '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34843 ) Change subject: soc/intel/common: gpio_defs: set trig to disable in PAD_NC ...................................................................... soc/intel/common: gpio_defs: set trig to disable in PAD_NC There is no need to change the default value for the RX Level/Edge Configuration parameter if the pad is not used/connected (PAD_NC) Change-Id: Ie7eee83fba9320d52240166371fe0c757dbdce49 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/34843/1 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 7440952..0c52f7d 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -289,11 +289,11 @@ /* * No Connect configuration for unused pad. * Both TX and RX are disabled. RX disabling is done to avoid unnecessary - * setting of GPI_STS. + * setting of GPI_STS. RX Level/Edge Trig Configuration set to disable */ #define PAD_NC(pad, pull) \ _PAD_CFG_STRUCT(pad, \ - PAD_FUNC(GPIO) | PAD_RESET(DEEP) | \ + PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_CFG0_TRIG_OFF | \ PAD_CFG0_TX_DISABLE | PAD_CFG0_RX_DISABLE, \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) -- To view, visit https://review.coreboot.org/c/coreboot/+/34843 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7eee83fba9320d52240166371fe0c757dbdce49 Gerrit-Change-Number: 34843 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ACPI S3: Drop ACPI_HUGE_LOWMEM_BACKUP
by Patrick Georgi (Code Review) 21 Aug '19

21 Aug '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/15476 ) Change subject: ACPI S3: Drop ACPI_HUGE_LOWMEM_BACKUP ...................................................................... Patch Set 13: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/15476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifae41b51b359010ec02269c674936a87bd15623b Gerrit-Change-Number: 15476 Gerrit-PatchSet: 13 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Aug 2019 09:31:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: AMD fam10: Remove HAVE_ACPI_RESUME support
by Patrick Georgi (Code Review) 21 Aug '19

21 Aug '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/15474 ) Change subject: AMD fam10: Remove HAVE_ACPI_RESUME support ...................................................................... AMD fam10: Remove HAVE_ACPI_RESUME support Change-Id: I62bbba8cfe515b3cae413582ff8d062a20e6741b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/15474 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/arch/x86/acpi_s3.c M src/arch/x86/include/arch/acpi.h M src/cpu/amd/car/post_cache_as_ram.c M src/cpu/amd/family_10h-family_15h/Kconfig M src/mainboard/asus/kcma-d8/Kconfig M src/mainboard/asus/kgpe-d16/Kconfig 6 files changed, 4 insertions(+), 79 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 98c53d1..47f28d2 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -116,23 +116,6 @@ return 0; } -void *acpi_backup_container(uintptr_t base, size_t size) -{ - struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME); - if (!backup_mem) - return NULL; - - if (!IS_ALIGNED(base, BACKUP_PAGE_SZ) || !IS_ALIGNED(size, - BACKUP_PAGE_SZ)) - return NULL; - - if (backup_create_or_update(backup_mem, base, size) < 0) - return NULL; - - backup_mem->valid = 1; - return (void *)(uintptr_t)backup_mem->cbmem; -} - void backup_ramstage_section(uintptr_t base, size_t size) { struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME); diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 259efcd..660f0dc 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -976,13 +976,6 @@ return CONFIG(HAVE_ACPI_RESUME); } -/* Return address in reserved memory where to backup low memory - * while platform resumes from S3 suspend. Caller is responsible of - * making a complete copy of the region base..base+size, with - * parameteres base and size that meet page alignment requirement. - */ -void *acpi_backup_container(uintptr_t base, size_t size); - #if CONFIG(HAVE_ACPI_RESUME) #ifdef __PRE_RAM__ diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index aa8222b..dfa4c3d 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -27,6 +27,7 @@ #include <cpu/amd/car.h> #include <cpu/amd/msr.h> #include <arch/acpi.h> +#include <program_loading.h> #include <romstage_handoff.h> #include "cpu/amd/car/disable_cache_as_ram.c" @@ -44,12 +45,6 @@ #define print_car_debug(format, arg...) #endif -static size_t backup_size(void) -{ - size_t car_size = car_data_size(); - return ALIGN_UP(car_size + 1024, 1024); -} - static void memcpy_(void *d, const void *s, size_t len) { print_car_debug(" Copy [%08x-%08x] to [%08x - %08x] ...", @@ -58,13 +53,6 @@ memcpy(d, s, len); } -static void memset_(void *d, int val, size_t len) -{ - print_car_debug(" Fill [%08x-%08x] ...", - (uint32_t) d, (uint32_t) (d + len - 1)); - memset(d, val, len); -} - static int memcmp_(void *d, const void *s, size_t len) { print_car_debug(" Compare [%08x-%08x] with [%08x - %08x] ...", @@ -73,41 +61,6 @@ return memcmp(d, s, len); } -static void prepare_romstage_ramstack(int s3resume) -{ - size_t backup_top = backup_size(); - print_car_debug("Prepare CAR migration and stack regions..."); - - if (s3resume) { - void *resume_backup_memory = - acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - if (resume_backup_memory) - memcpy_(resume_backup_memory - + HIGH_MEMORY_SAVE - backup_top, - (void *)(CONFIG_RAMTOP - backup_top), - backup_top); - } - memset_((void *)(CONFIG_RAMTOP - backup_top), 0, backup_top); - - print_car_debug(" Done\n"); -} - -static void prepare_ramstage_region(int s3resume) -{ - size_t backup_top = backup_size(); - print_car_debug("Prepare ramstage memory region..."); - - if (s3resume) { - void *resume_backup_memory = - acpi_backup_container(CONFIG_RAMBASE, HIGH_MEMORY_SAVE); - if (resume_backup_memory) - memcpy_(resume_backup_memory, (void *) CONFIG_RAMBASE, - HIGH_MEMORY_SAVE - backup_top); - } - - print_car_debug(" Done\n"); -} - /* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33 * and RevGuide for Fam12h, Pub#44739 Rev 3.10 */ @@ -137,9 +90,10 @@ if ((*lower_stack_boundary) != 0xdeadbeef) printk(BIOS_WARNING, "BSP overran lower stack boundary. Undefined behaviour may result!\n"); - s3resume = acpi_is_wakeup_s3(); - prepare_romstage_ramstack(s3resume); + /* ACPI S3 is not supported without RELOCATABLE_RAMSTAGE and + * this will always return 0. */ + s3resume = acpi_is_wakeup_s3(); romstage_handoff_init(s3resume); @@ -177,8 +131,6 @@ set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); enable_cache(); - prepare_ramstage_region(acpi_is_wakeup_s3()); - set_sysinfo_in_ram(1); // So other core0 could start to train mem /*copy and execute ramstage */ diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig index e9ee855..ad4f5f4 100644 --- a/src/cpu/amd/family_10h-family_15h/Kconfig +++ b/src/cpu/amd/family_10h-family_15h/Kconfig @@ -10,7 +10,6 @@ select SUPPORT_CPU_UCODE_IN_CBFS select CPU_MICROCODE_MULTIPLE_FILES select CAR_GLOBAL_MIGRATION - select ACPI_HUGE_LOWMEM_BACKUP if CPU_AMD_MODEL_10XXX diff --git a/src/mainboard/asus/kcma-d8/Kconfig b/src/mainboard/asus/kcma-d8/Kconfig index 1a2dd90..d568ff5 100644 --- a/src/mainboard/asus/kcma-d8/Kconfig +++ b/src/mainboard/asus/kcma-d8/Kconfig @@ -27,7 +27,6 @@ select BOARD_ROMSIZE_KB_2048 select ENABLE_APIC_EXT_ID select SPI_FLASH - select HAVE_ACPI_RESUME select DRIVERS_I2C_W83795 select DRIVERS_ASPEED_AST2050 select MAINBOARD_FORCE_NATIVE_VGA_INIT diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig index 32c4dbc..f3f5a5c 100644 --- a/src/mainboard/asus/kgpe-d16/Kconfig +++ b/src/mainboard/asus/kgpe-d16/Kconfig @@ -28,7 +28,6 @@ select ENABLE_APIC_EXT_ID select SPI_FLASH select MAINBOARD_HAS_LPC_TPM - select HAVE_ACPI_RESUME select DRIVERS_I2C_W83795 select DRIVERS_ASPEED_AST2050 select MAINBOARD_FORCE_NATIVE_VGA_INIT -- To view, visit https://review.coreboot.org/c/coreboot/+/15474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I62bbba8cfe515b3cae413582ff8d062a20e6741b Gerrit-Change-Number: 15474 Gerrit-PatchSet: 13 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Gerrit-Reviewer: Rudolf Marek <r.marek(a)assembler.cz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in coreboot[master]: soc/intel/common: Set controller state to active in uart init
by Usha P (Code Review) 21 Aug '19

21 Aug '19

Usha P has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34810 ) Change subject: soc/intel/common: Set controller state to active in uart init ...................................................................... soc/intel/common: Set controller state to active in uart init Set the controller state to D0 during the uart init sequence, this ensures the controller is up and active. One more argument "const struct device *dev" has been added to uart_lpss_init function for the same. BUG=b:135941367 TEST=Verify no timeouts seen during UART controller enumeration sequence in CML, ICl and APL platforms Change-Id: Ie91b502a38d1a40a3dea3711b015b7a5b7ede2db Signed-off-by: Usha P <usha.p(a)intel.com> --- M src/soc/intel/common/block/uart/uart.c 1 file changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/34810/1 diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index f556aed..364835d 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -33,8 +33,11 @@ extern const struct uart_gpio_pad_config uart_gpio_pads[]; extern const int uart_max_index; -static void uart_lpss_init(uintptr_t baseaddr) +static void uart_lpss_init(const struct device *dev, uintptr_t baseaddr) { + /* Ensure controller is in D0 state */ + lpss_set_power_state(dev, STATE_D0); + /* Take UART out of reset */ lpss_reset_release(baseaddr); @@ -79,7 +82,7 @@ /* Enable memory access and bus master */ pci_write_config32(dev, PCI_COMMAND, UART_PCI_ENABLE); - uart_lpss_init(baseaddr); + uart_lpss_init(device, baseaddr); } const struct device *uart_get_device(void) @@ -231,7 +234,7 @@ base = pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xFFF; if (base) - uart_lpss_init(base); + uart_lpss_init(dev, base); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/34810 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie91b502a38d1a40a3dea3711b015b7a5b7ede2db Gerrit-Change-Number: 34810 Gerrit-PatchSet: 1 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-MessageType: newchange

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