coreboot-gerrit August 2019

coreboot-gerrit@coreboot.org

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1942 discussions

Change in coreboot[master]: soc/intel: Add function to set DPR
by Patrick Rudolph (Code Review) 22 Aug '19

22 Aug '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33417 ) Change subject: soc/intel: Add function to set DPR ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/33417/7/src/soc/intel/fsp_broadwel… File src/soc/intel/fsp_broadwell_de/ramstage.c: https://review.coreboot.org/c/coreboot/+/33417/7/src/soc/intel/fsp_broadwel… PS7, Line 31: #include <soc/broadwell_de.h> > IMHO, If possible, I would suggest addressing the conflicts between fsp_broadwell_de and <intelblock […] Feel free to address those conflicts, but keep in mind that BroadwellDE is a server platform, while intel/common is for consumer/desktop platforms. It's not easy to unify those and out of scope of this commit. I don't see the need to have a shared header, as I can include the correct header using preprocessor guards. -- To view, visit https://review.coreboot.org/c/coreboot/+/33417 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43d2b50a7a6bb41146be99e645cd2ac6a6c9f703 Gerrit-Change-Number: 33417 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 22 Aug 2019 07:16:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

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Change in coreboot[master]: x86: Introduce RESET_VECTOR_IN_RAM option
by Kyösti Mälkki (Code Review) 22 Aug '19

22 Aug '19

Hello Aaron Durbin, Julius Werner, Marshall Dawson, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35004 to look at the new patch set (#7). Change subject: x86: Introduce RESET_VECTOR_IN_RAM option ...................................................................... x86: Introduce RESET_VECTOR_IN_RAM option Create a new Kconfig symbol that allows an x86 device to begin execution when its reset vector is in DRAM and not at the traditional 0xfffffff0. The implementation will follow later, this is just to setup various ENV_xxx definitions correctly for the build environment. Change-Id: I098ecf8bf200550db1e15f178f7661c1ac516dc5 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/Kconfig M src/arch/x86/memlayout.ld M src/include/rules.h 3 files changed, 18 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/35004/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/35004 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I098ecf8bf200550db1e15f178f7661c1ac516dc5 Gerrit-Change-Number: 35004 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Split MAYBE_STATIC to _BSS and _NONZERO variants
by Kyösti Mälkki (Code Review) 22 Aug '19

22 Aug '19

Hello Aaron Durbin, Patrick Rudolph, Julius Werner, Marshall Dawson, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35003 to look at the new patch set (#7). Change subject: Split MAYBE_STATIC to _BSS and _NONZERO variants ...................................................................... Split MAYBE_STATIC to _BSS and _NONZERO variants These are required to cover the absensce of .data and .bss sections in some programs, most notably ARCH_X86 in execute-in-place with cache-as-ram. Change-Id: I80485ebac94b88c5864a949b17ad1dccdfda6a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/device/device_const.c M src/ec/google/chromeec/ec_boardid.c M src/ec/google/chromeec/ec_lpc.c M src/ec/google/wilco/boardid.c M src/include/stddef.h M src/lib/lzma.c M src/lib/timestamp.c M src/mainboard/google/stout/chromeos.c M src/mainboard/intel/glkrvp/boardid.c M src/mainboard/intel/glkrvp/variants/baseboard/boardid.c M src/mainboard/intel/icelake_rvp/board_id.c M src/mainboard/intel/kblrvp/board_id.c M src/security/tpm/tspi/log.c M src/soc/intel/baytrail/northcluster.c M src/soc/intel/braswell/northcluster.c M toolchain.inc 16 files changed, 26 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/35003/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/35003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80485ebac94b88c5864a949b17ad1dccdfda6a40 Gerrit-Change-Number: 35003 Gerrit-PatchSet: 7 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: ACPI S3: Depend on RELOCATABLE_RAMSTAGE
by Kyösti Mälkki (Code Review) 22 Aug '19

22 Aug '19

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/26834 ) Change subject: ACPI S3: Depend on RELOCATABLE_RAMSTAGE ...................................................................... ACPI S3: Depend on RELOCATABLE_RAMSTAGE With RELOCATABLE_RAMSTAGE, S3 resume path only uses memory that is reserved from OS. So there is no need for low memory backup and recovery. Change-Id: If7f83711685ac445abf4cd1aa6b66c3391e0e554 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26834 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/Kconfig M src/arch/x86/acpi_s3.c M src/arch/x86/include/arch/acpi.h M src/arch/x86/wakeup.S M src/lib/hardwaremain.c M src/lib/prog_loaders.c 6 files changed, 4 insertions(+), 130 deletions(-) Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Arthur Heymans: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved diff --git a/src/Kconfig b/src/Kconfig index 333643e..d49ca25 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -484,6 +484,7 @@ config HAVE_ACPI_RESUME bool default n + depends on RELOCATABLE_RAMSTAGE config RESUME_PATH_SAME_AS_BOOT bool diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index decaf2b..ff9d60c 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -70,124 +70,20 @@ } #endif /* ENV_RAMSTAGE */ -struct resume_backup { - uint64_t cbmem; - uint64_t lowmem; - uint64_t size; - uint8_t valid; -}; - -#define BACKUP_PAGE_SZ 4096 - -static int backup_create_or_update(struct resume_backup *backup_mem, - uintptr_t base, size_t size) -{ - uintptr_t top; - - /* Align backup region to complete pages. */ - top = ALIGN_UP(base + size, BACKUP_PAGE_SZ); - base = ALIGN_DOWN(base, BACKUP_PAGE_SZ); - size = top - base; - - /* Cannot extend existing region, should not happen. */ - if (backup_mem && (backup_mem->size < size)) - return -1; - - /* Allocate backup with room for header. */ - if (!backup_mem) { - size_t header_sz = ALIGN_UP(sizeof(*backup_mem), - BACKUP_PAGE_SZ); - backup_mem = cbmem_add(CBMEM_ID_RESUME, header_sz + size); - if (!backup_mem) - return -1; - - /* Container starts from boundary after header. */ - backup_mem->cbmem = (uintptr_t)backup_mem + header_sz; - } - - backup_mem->valid = 0; - backup_mem->lowmem = base; - backup_mem->size = size; - return 0; -} - -void backup_ramstage_section(uintptr_t base, size_t size) -{ - struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME); - - /* For first boot we exit here as CBMEM_ID_RESUME is only - * created late in ramstage with acpi_prepare_resume_backup(). - */ - if (!backup_mem) - return; - - /* Check that the backup is not done twice. */ - if (backup_mem->valid) - return; - - /* When we are called from ramstage loader, update header with - * properties of the ramstage we will load. - */ - if (backup_create_or_update(backup_mem, base, size) < 0) - return; - - /* Back up the OS-controlled memory where ramstage will be loaded. */ - memcpy((void *)(uintptr_t)backup_mem->cbmem, - (void *)(uintptr_t)backup_mem->lowmem, - (size_t)backup_mem->size); - backup_mem->valid = 1; -} - -/* Let's prepare the ACPI S3 Resume area now already, so we can rely on - * it being there during reboot time. If this fails, ACPI resume will - * be disabled. We assume that ramstage does not change while in suspend, - * so base and size of the currently running ramstage are used - * for allocation. - */ -void acpi_prepare_resume_backup(void) -{ - if (!acpi_s3_resume_allowed()) - return; - - if (CONFIG(RELOCATABLE_RAMSTAGE)) - return; - - backup_create_or_update(NULL, (uintptr_t)_program, - REGION_SIZE(program)); -} - #define WAKEUP_BASE 0x600 -asmlinkage void (*acpi_do_wakeup)(uintptr_t vector, u32 backup_source, - u32 backup_target, u32 backup_size) = (void *)WAKEUP_BASE; +asmlinkage void (*acpi_do_wakeup)(uintptr_t vector) = (void *)WAKEUP_BASE; extern unsigned char __wakeup; extern unsigned int __wakeup_size; static void acpi_jump_to_wakeup(void *vector) { - uintptr_t source = 0, target = 0; - size_t size = 0; - if (!acpi_s3_resume_allowed()) { printk(BIOS_WARNING, "ACPI: S3 resume not allowed.\n"); return; } - if (!CONFIG(RELOCATABLE_RAMSTAGE)) { - struct resume_backup *backup_mem = cbmem_find(CBMEM_ID_RESUME); - if (backup_mem && backup_mem->valid) { - backup_mem->valid = 0; - target = backup_mem->lowmem; - source = backup_mem->cbmem; - size = backup_mem->size; - } else { - printk(BIOS_WARNING, "ACPI: Backup memory missing. " - "No S3 resume.\n"); - return; - } - } - /* Copy wakeup trampoline in place. */ memcpy((void *)WAKEUP_BASE, &__wakeup, __wakeup_size); @@ -195,7 +91,7 @@ timestamp_add_now(TS_ACPI_WAKE_JUMP); - acpi_do_wakeup((uintptr_t)vector, source, target, size); + acpi_do_wakeup((uintptr_t)vector); } void __weak mainboard_suspend_resume(void) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 670948a..16e4269 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -934,7 +934,6 @@ /* For ACPI S3 support. */ void acpi_fail_wakeup(void); void acpi_resume(void *wake_vec); -void acpi_prepare_resume_backup(void); void mainboard_suspend_resume(void); void *acpi_find_wakeup_vector(void); diff --git a/src/arch/x86/wakeup.S b/src/arch/x86/wakeup.S index ba502fe..1362eb4 100644 --- a/src/arch/x86/wakeup.S +++ b/src/arch/x86/wakeup.S @@ -64,14 +64,6 @@ shr $4, %eax movw %ax, (__wakeup_segment) - /* Then overwrite coreboot with our backed up memory */ - cld - movl 8(%esp), %esi - movl 12(%esp), %edi - movl 16(%esp), %ecx - shrl $2, %ecx - rep movsl - /* Activate the right segment descriptor real mode. */ ljmp $0x28, $RELOCATED(1f) 1: diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 2881162..3c6fb93 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -187,8 +187,6 @@ boot_states[BS_OS_RESUME].arg = wake_vector; return BS_OS_RESUME; } - - acpi_prepare_resume_backup(); #endif timestamp_add_now(TS_CBMEM_POST); diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index dfabd31..2ef6bdf 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -107,18 +107,6 @@ return rmodule_stage_load(&rmod_ram); } -static int load_nonrelocatable_ramstage(struct prog *ramstage) -{ - if (CONFIG(HAVE_ACPI_RESUME)) { - uintptr_t base = 0; - size_t size = cbfs_prog_stage_section(ramstage, &base); - if (size) - backup_ramstage_section(base, size); - } - - return cbfs_prog_stage_load(ramstage); -} - void run_ramstage(void) { struct prog ramstage = @@ -147,7 +135,7 @@ if (CONFIG(RELOCATABLE_RAMSTAGE)) { if (load_relocatable_ramstage(&ramstage)) goto fail; - } else if (load_nonrelocatable_ramstage(&ramstage)) + } else if (cbfs_prog_stage_load(&ramstage)) goto fail; stage_cache_add(STAGE_RAMSTAGE, &ramstage); -- To view, visit https://review.coreboot.org/c/coreboot/+/26834 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7f83711685ac445abf4cd1aa6b66c3391e0e554 Gerrit-Change-Number: 26834 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: ACPI S3: Drop ACPI_HUGE_LOWMEM_BACKUP
by Kyösti Mälkki (Code Review) 22 Aug '19

22 Aug '19

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/15476 ) Change subject: ACPI S3: Drop ACPI_HUGE_LOWMEM_BACKUP ...................................................................... ACPI S3: Drop ACPI_HUGE_LOWMEM_BACKUP ACPI S3 resume path can only modify low memory where the non-relocatable ramstage resides, there is no need to maintain a bigger backup copy. Change-Id: Ifae41b51b359010ec02269c674936a87bd15623b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/15476 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/Kconfig M src/arch/x86/acpi_s3.c M src/arch/x86/include/arch/acpi.h 3 files changed, 0 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Aaron Durbin: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved diff --git a/src/Kconfig b/src/Kconfig index 6288d0b..333643e 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -485,12 +485,6 @@ bool default n -config ACPI_HUGE_LOWMEM_BACKUP - bool - default n - help - On S3 resume path, backup low memory from RAMBASE..RAMTOP in CBMEM. - config RESUME_PATH_SAME_AS_BOOT bool default y if ARCH_X86 diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index 47f28d2..decaf2b 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -84,11 +84,6 @@ { uintptr_t top; - if (CONFIG(ACPI_HUGE_LOWMEM_BACKUP)) { - base = CONFIG_RAMBASE; - size = HIGH_MEMORY_SAVE; - } - /* Align backup region to complete pages. */ top = ALIGN_UP(base + size, BACKUP_PAGE_SZ); base = ALIGN_DOWN(base, BACKUP_PAGE_SZ); diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 660f0dc..670948a 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -26,8 +26,6 @@ #ifndef __ASM_ACPI_H #define __ASM_ACPI_H -#define HIGH_MEMORY_SAVE (CONFIG_RAMTOP - CONFIG_RAMBASE) - /* * The type and enable fields are common in ACPI, but the * values themselves are hardware implementation defined. -- To view, visit https://review.coreboot.org/c/coreboot/+/15476 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifae41b51b359010ec02269c674936a87bd15623b Gerrit-Change-Number: 15476 Gerrit-PatchSet: 14 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: Split MAYBE_STATIC to _BSS and _NONZERO variants
by Kyösti Mälkki (Code Review) 22 Aug '19

22 Aug '19

Hello Aaron Durbin, Patrick Rudolph, Julius Werner, Marshall Dawson, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/35003 to look at the new patch set (#6). Change subject: Split MAYBE_STATIC to _BSS and _NONZERO variants ...................................................................... Split MAYBE_STATIC to _BSS and _NONZERO variants These are required to cover the absensce of .data and .bss sections in some programs, most notably ARCH_X86 in execute-in-place with cache-as-ram. Change-Id: I80485ebac94b88c5864a949b17ad1dccdfda6a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/device/device_const.c M src/ec/google/chromeec/ec_boardid.c M src/ec/google/chromeec/ec_lpc.c M src/ec/google/wilco/boardid.c M src/include/stddef.h M src/lib/lzma.c M src/lib/program.ld M src/lib/timestamp.c M src/mainboard/google/stout/chromeos.c M src/mainboard/intel/glkrvp/boardid.c M src/mainboard/intel/glkrvp/variants/baseboard/boardid.c M src/mainboard/intel/icelake_rvp/board_id.c M src/mainboard/intel/kblrvp/board_id.c M src/security/tpm/tspi/log.c M src/soc/intel/baytrail/northcluster.c M src/soc/intel/braswell/northcluster.c M toolchain.inc 17 files changed, 28 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/35003/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/35003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80485ebac94b88c5864a949b17ad1dccdfda6a40 Gerrit-Change-Number: 35003 Gerrit-PatchSet: 6 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Split MAYBE_STATIC to _BSS and _NONZERO variants
by Kyösti Mälkki (Code Review) 22 Aug '19

22 Aug '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35003 ) Change subject: Split MAYBE_STATIC to _BSS and _NONZERO variants ...................................................................... Patch Set 5: Code-Review-2 Need to fix lib/program.ld overruling arch/x86/car.ld for placement of .bss. CB:35014 -- To view, visit https://review.coreboot.org/c/coreboot/+/35003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80485ebac94b88c5864a949b17ad1dccdfda6a40 Gerrit-Change-Number: 35003 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Aug 2019 03:58:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Split MAYBE_STATIC to _BSS and _NONZERO variants
by Furquan Shaikh (Code Review) 22 Aug '19

22 Aug '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35003 ) Change subject: Split MAYBE_STATIC to _BSS and _NONZERO variants ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80485ebac94b88c5864a949b17ad1dccdfda6a40 Gerrit-Change-Number: 35003 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 22 Aug 2019 03:26:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: arch/x86: Add <arch/romstage.h>
by Kyösti Mälkki (Code Review) 22 Aug '19

22 Aug '19

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34911 ) Change subject: arch/x86: Add <arch/romstage.h> ...................................................................... arch/x86: Add <arch/romstage.h> Start with moving all postcar_frame related function declarations here from <arch/cpu.h>. Change-Id: I9aeef07f9009e44cc08927c85fe1862edf5c70dc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34911 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/x86/include/arch/cpu.h A src/arch/x86/include/arch/romstage.h M src/arch/x86/postcar.c M src/arch/x86/postcar_loader.c M src/cpu/intel/car/romstage.c M src/drivers/amd/agesa/mtrr_fixme.c M src/drivers/amd/agesa/romstage.c M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp2_0/temp_ram_exit.c M src/include/cpu/intel/romstage.h M src/mainboard/emulation/qemu-i440fx/romstage.c M src/mainboard/emulation/qemu-q35/romstage.c M src/northbridge/amd/agesa/agesa_helper.h M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/i440bx/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/nehalem/memmap.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/x4x/memmap.c M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/quark/romstage/fsp2_0.c M src/soc/intel/skylake/romstage/romstage_fsp20.c 32 files changed, 113 insertions(+), 80 deletions(-) Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved HAOUAS Elyes: Looks good to me, but someone else must approve diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 9aa446e..263b734 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -279,11 +279,10 @@ c->x86_model += ((tfms >> 16) & 0xF) << 4; } -#endif +/* romcc does not understand regparm. */ #define asmlinkage __attribute__((regparm(0))) -#ifndef __ROMCC__ /* * When using CONFIG_C_ENVIRONMENT_BOOTBLOCK the car_stage_entry() * is the symbol jumped to for each stage after bootblock using @@ -291,66 +290,6 @@ */ asmlinkage void car_stage_entry(void); -/* - * Support setting up a stack frame consisting of MTRR information - * for use in bootstrapping the caching attributes after cache-as-ram - * is torn down. - */ - -struct postcar_frame { - uintptr_t stack; - uint32_t upper_mask; - int max_var_mtrrs; - int num_var_mtrrs; - int skip_common_mtrr; -}; - -/* - * Initialize postcar_frame object allocating stack from cbmem, - * with stack_size == 0, default 4 KiB is allocated. - * Returns 0 on success, < 0 on error. - */ -int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size); - -/* - * Add variable MTRR covering the provided range with MTRR type. - */ -void postcar_frame_add_mtrr(struct postcar_frame *pcf, - uintptr_t addr, size_t size, int type); - -/* - * Add variable MTRR covering the memory-mapped ROM with given MTRR type. - */ -void postcar_frame_add_romcache(struct postcar_frame *pcf, int type); - -/* - * Add a common MTRR setup most platforms will have as a subset. - */ -void postcar_frame_common_mtrrs(struct postcar_frame *pcf); - -/* - * Push used MTRR and Max MTRRs on to the stack - * and return pointer to stack top. - */ -void *postcar_commit_mtrrs(struct postcar_frame *pcf); - -/* - * Load and run a program that takes control of execution that - * tears down CAR and loads ramstage. The postcar_frame object - * indicates how to set up the frame. If caching is enabled at - * the time of the call it is up to the platform code to handle - * coherency with dirty lines in the cache using some mechansim - * such as platform_prog_run() because run_postcar_phase() - * utilizes prog_run() internally. - */ -void run_postcar_phase(struct postcar_frame *pcf); - -/* - * Systems without a native coreboot cache-as-ram teardown may implement - * this to use an alternate method. - */ -void late_car_teardown(void); - #endif /* diff --git a/src/arch/x86/include/arch/romstage.h b/src/arch/x86/include/arch/romstage.h new file mode 100644 index 0000000..42c9fbb --- /dev/null +++ b/src/arch/x86/include/arch/romstage.h @@ -0,0 +1,81 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ARCH_ROMSTAGE_H__ +#define __ARCH_ROMSTAGE_H__ + +#include <arch/cpu.h> +#include <stddef.h> +#include <stdint.h> + +/* + * Support setting up a stack frame consisting of MTRR information + * for use in bootstrapping the caching attributes after cache-as-ram + * is torn down. + */ + +struct postcar_frame { + uintptr_t stack; + uint32_t upper_mask; + int max_var_mtrrs; + int num_var_mtrrs; + int skip_common_mtrr; +}; + +/* + * Initialize postcar_frame object allocating stack from cbmem, + * with stack_size == 0, default 4 KiB is allocated. + * Returns 0 on success, < 0 on error. + */ +int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size); + +/* + * Add variable MTRR covering the provided range with MTRR type. + */ +void postcar_frame_add_mtrr(struct postcar_frame *pcf, + uintptr_t addr, size_t size, int type); + +/* + * Add variable MTRR covering the memory-mapped ROM with given MTRR type. + */ +void postcar_frame_add_romcache(struct postcar_frame *pcf, int type); + +/* + * Add a common MTRR setup most platforms will have as a subset. + */ +void postcar_frame_common_mtrrs(struct postcar_frame *pcf); + +/* + * Push used MTRR and Max MTRRs on to the stack + * and return pointer to stack top. + */ +void *postcar_commit_mtrrs(struct postcar_frame *pcf); + +/* + * Load and run a program that takes control of execution that + * tears down CAR and loads ramstage. The postcar_frame object + * indicates how to set up the frame. If caching is enabled at + * the time of the call it is up to the platform code to handle + * coherency with dirty lines in the cache using some mechansim + * such as platform_prog_run() because run_postcar_phase() + * utilizes prog_run() internally. + */ +void run_postcar_phase(struct postcar_frame *pcf); + +/* + * Systems without a native coreboot cache-as-ram teardown may implement + * this to use an alternate method. + */ +void late_car_teardown(void); + +#endif /* __ARCH_ROMSTAGE_H__ */ diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c index b4efc94..e082596 100644 --- a/src/arch/x86/postcar.c +++ b/src/arch/x86/postcar.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include <arch/cpu.h> +#include <arch/romstage.h> #include <cbmem.h> #include <console/console.h> #include <cpu/x86/mtrr.h> diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index b1b2da0..816f41e 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include <arch/cpu.h> +#include <arch/romstage.h> #include <cbmem.h> #include <console/console.h> #include <cpu/cpu.h> diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index e24225e..a0dc743 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -11,6 +11,8 @@ * GNU General Public License for more details. */ +#include <arch/cpu.h> +#include <arch/romstage.h> #include <bootblock_common.h> #include <console/console.h> #include <cpu/intel/romstage.h> diff --git a/src/drivers/amd/agesa/mtrr_fixme.c b/src/drivers/amd/agesa/mtrr_fixme.c index fcb353c..bbb9eb0 100644 --- a/src/drivers/amd/agesa/mtrr_fixme.c +++ b/src/drivers/amd/agesa/mtrr_fixme.c @@ -11,7 +11,7 @@ * GNU General Public License for more details. */ -#include <arch/cpu.h> +#include <arch/romstage.h> #include <cbmem.h> #include <console/console.h> #include <commonlib/helpers.h> diff --git a/src/drivers/amd/agesa/romstage.c b/src/drivers/amd/agesa/romstage.c index adf6e0d..fad49c3 100644 --- a/src/drivers/amd/agesa/romstage.c +++ b/src/drivers/amd/agesa/romstage.c @@ -15,6 +15,7 @@ #include <arch/acpi.h> #include <arch/cpu.h> +#include <arch/romstage.h> #include <cbmem.h> #include <cpu/amd/car.h> #include <cpu/x86/bist.h> diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c index 67fbe69..fafe838 100644 --- a/src/drivers/intel/fsp1_1/car.c +++ b/src/drivers/intel/fsp1_1/car.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <arch/romstage.h> #include <arch/symbols.h> #include <cbmem.h> #include <console/console.h> diff --git a/src/drivers/intel/fsp2_0/temp_ram_exit.c b/src/drivers/intel/fsp2_0/temp_ram_exit.c index 075e923..342fc35 100644 --- a/src/drivers/intel/fsp2_0/temp_ram_exit.c +++ b/src/drivers/intel/fsp2_0/temp_ram_exit.c @@ -9,7 +9,7 @@ * (at your option) any later version. */ -#include <arch/cpu.h> +#include <arch/romstage.h> #include <console/console.h> #include <fsp/api.h> #include <fsp/util.h> diff --git a/src/include/cpu/intel/romstage.h b/src/include/cpu/intel/romstage.h index ff0a167..fd5d7f4 100644 --- a/src/include/cpu/intel/romstage.h +++ b/src/include/cpu/intel/romstage.h @@ -1,7 +1,7 @@ #ifndef _CPU_INTEL_ROMSTAGE_H #define _CPU_INTEL_ROMSTAGE_H -#include <arch/cpu.h> +#include <arch/romstage.h> void mainboard_romstage_entry(void); diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index 6b1883c..32eab3d 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -15,10 +15,10 @@ */ #include <arch/cpu.h> +#include <arch/romstage.h> #include <stdint.h> #include <cbmem.h> #include <console/console.h> -#include <cpu/intel/romstage.h> #include <timestamp.h> #include <program_loading.h> diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index dbaead9..6cd9ee4 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -15,10 +15,10 @@ */ #include <arch/cpu.h> +#include <arch/romstage.h> #include <stdint.h> #include <cbmem.h> #include <console/console.h> -#include <cpu/intel/romstage.h> #include <timestamp.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <program_loading.h> diff --git a/src/northbridge/amd/agesa/agesa_helper.h b/src/northbridge/amd/agesa/agesa_helper.h index 17819e9..dcc3360 100644 --- a/src/northbridge/amd/agesa/agesa_helper.h +++ b/src/northbridge/amd/agesa/agesa_helper.h @@ -17,7 +17,7 @@ #define _AGESA_HELPER_H_ #include <stddef.h> -#include <arch/cpu.h> +#include <arch/romstage.h> enum { PICK_DMI, /* DMI Interface */ diff --git a/src/northbridge/intel/e7505/memmap.c b/src/northbridge/intel/e7505/memmap.c index 7033f89..9a63cff 100644 --- a/src/northbridge/intel/e7505/memmap.c +++ b/src/northbridge/intel/e7505/memmap.c @@ -15,7 +15,7 @@ #define __SIMPLE_DEVICE__ #include <device/pci_ops.h> -#include <arch/cpu.h> +#include <arch/romstage.h> #include <cbmem.h> #include <console/console.h> #include <cpu/intel/romstage.h> diff --git a/src/northbridge/intel/gm45/memmap.c b/src/northbridge/intel/gm45/memmap.c index ceb6476..4814e35 100644 --- a/src/northbridge/intel/gm45/memmap.c +++ b/src/northbridge/intel/gm45/memmap.c @@ -18,7 +18,7 @@ #define __SIMPLE_DEVICE__ #include <stdint.h> -#include <arch/cpu.h> +#include <arch/romstage.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <console/console.h> diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index f43bd2f..b1d86db 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -16,7 +16,7 @@ // Use simple device model for this file even in ramstage #define __SIMPLE_DEVICE__ -#include <arch/cpu.h> +#include <arch/romstage.h> #include <console/console.h> #include <cpu/x86/mtrr.h> #include <device/pci_ops.h> diff --git a/src/northbridge/intel/i440bx/memmap.c b/src/northbridge/intel/i440bx/memmap.c index e4e5de7..6a1730e 100644 --- a/src/northbridge/intel/i440bx/memmap.c +++ b/src/northbridge/intel/i440bx/memmap.c @@ -15,7 +15,7 @@ #define __SIMPLE_DEVICE__ -#include <arch/cpu.h> +#include <arch/romstage.h> #include <device/pci_ops.h> #include <cbmem.h> #include <console/console.h> diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index f2518f4..b0764f6 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -17,7 +17,7 @@ #define __SIMPLE_DEVICE__ #include <device/pci_ops.h> -#include <arch/cpu.h> +#include <arch/romstage.h> #include <cbmem.h> #include "i945.h" #include <console/console.h> diff --git a/src/northbridge/intel/nehalem/memmap.c b/src/northbridge/intel/nehalem/memmap.c index d592aea..8787df6 100644 --- a/src/northbridge/intel/nehalem/memmap.c +++ b/src/northbridge/intel/nehalem/memmap.c @@ -16,7 +16,7 @@ #define __SIMPLE_DEVICE__ -#include <arch/cpu.h> +#include <arch/romstage.h> #include <device/pci_ops.h> #include <cbmem.h> #include <console/console.h> diff --git a/src/northbridge/intel/pineview/memmap.c b/src/northbridge/intel/pineview/memmap.c index 8be63ef..eaf27f6 100644 --- a/src/northbridge/intel/pineview/memmap.c +++ b/src/northbridge/intel/pineview/memmap.c @@ -16,7 +16,7 @@ #define __SIMPLE_DEVICE__ -#include <arch/cpu.h> +#include <arch/romstage.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci_def.h> diff --git a/src/northbridge/intel/sandybridge/memmap.c b/src/northbridge/intel/sandybridge/memmap.c index 9e2e333..44bbbd2 100644 --- a/src/northbridge/intel/sandybridge/memmap.c +++ b/src/northbridge/intel/sandybridge/memmap.c @@ -15,7 +15,7 @@ #define __SIMPLE_DEVICE__ -#include <arch/cpu.h> +#include <arch/romstage.h> #include <device/pci_ops.h> #include <cbmem.h> #include <console/console.h> diff --git a/src/northbridge/intel/x4x/memmap.c b/src/northbridge/intel/x4x/memmap.c index 9480fc0..b8a3b94 100644 --- a/src/northbridge/intel/x4x/memmap.c +++ b/src/northbridge/intel/x4x/memmap.c @@ -20,7 +20,7 @@ #include <cbmem.h> #include <commonlib/helpers.h> #include <stdint.h> -#include <arch/cpu.h> +#include <arch/romstage.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <console/console.h> diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 7970b0e..4f18b42 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -16,6 +16,7 @@ #include <device/pci_ops.h> #include <arch/cpu.h> +#include <arch/romstage.h> #include <arch/acpi.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> diff --git a/src/soc/amd/stoneyridge/romstage.c b/src/soc/amd/stoneyridge/romstage.c index c76f7cd..0d65ef6 100644 --- a/src/soc/amd/stoneyridge/romstage.c +++ b/src/soc/amd/stoneyridge/romstage.c @@ -16,6 +16,7 @@ #include <device/pci_ops.h> #include <arch/cpu.h> +#include <arch/romstage.h> #include <arch/acpi.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index fb8473c..1464d2c 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -17,6 +17,7 @@ */ #include <arch/cpu.h> +#include <arch/romstage.h> #include <device/pci_ops.h> #include <arch/symbols.h> #include <assert.h> diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 63e36aa..f20c363 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -16,6 +16,7 @@ #include <stddef.h> #include <arch/cpu.h> #include <arch/io.h> +#include <arch/romstage.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <bootblock_common.h> diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index e7b8ae0..3f264ff 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -16,7 +16,7 @@ #include <stddef.h> #include <stdint.h> #include <arch/cbfs.h> -#include <arch/cpu.h> +#include <arch/romstage.h> #include <bootblock_common.h> #include <bootmode.h> #include <cbmem.h> diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 94b9899..9f02c8b 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -14,6 +14,7 @@ */ #include <arch/cpu.h> +#include <arch/romstage.h> #include <cpu/x86/mtrr.h> #include <cbmem.h> #include <console/console.h> diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 53c51f4..9c41486 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -15,6 +15,7 @@ */ #include <arch/cpu.h> +#include <arch/romstage.h> #include <arch/io.h> #include <cbmem.h> #include <cf9_reset.h> diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c index 65e65cc..8312f17 100644 --- a/src/soc/intel/icelake/romstage/romstage.c +++ b/src/soc/intel/icelake/romstage/romstage.c @@ -14,6 +14,7 @@ */ #include <arch/cpu.h> +#include <arch/romstage.h> #include <cpu/x86/mtrr.h> #include <cbmem.h> #include <console/console.h> diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 20f2ad7..0489621 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -14,6 +14,7 @@ */ #include <arch/cpu.h> +#include <arch/romstage.h> #include <arch/symbols.h> #include <console/console.h> #include <cbmem.h> diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 221c6c4..8b5cd18 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -14,6 +14,7 @@ */ #include <arch/cpu.h> +#include <arch/romstage.h> #include <arch/symbols.h> #include <assert.h> #include <cpu/x86/mtrr.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/34911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9aeef07f9009e44cc08927c85fe1862edf5c70dc Gerrit-Change-Number: 34911 Gerrit-PatchSet: 8 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mediatek/mt8183: Enable DRAM frequency 3600Mbps for EMCP DDR
by Yu-Ping Wu (Code Review) 22 Aug '19

22 Aug '19

Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34990 ) Change subject: mediatek/mt8183: Enable DRAM frequency 3600Mbps for EMCP DDR ...................................................................... Patch Set 2: (3 comments) https://review.coreboot.org/c/coreboot/+/34990/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/34990/2//COMMIT_MSG@9 PS2, Line 9: 3600Mbs Mbps https://review.coreboot.org/c/coreboot/+/34990/2//COMMIT_MSG@11 PS2, Line 11: proformance performance https://review.coreboot.org/c/coreboot/+/34990/2/src/soc/mediatek/mt8183/em… File src/soc/mediatek/mt8183/emi.c: https://review.coreboot.org/c/coreboot/+/34990/2/src/soc/mediatek/mt8183/em… PS2, Line 23: #define LP4X_HIGH_FREQ LP4X_DDR3600 : #define LP4X_MIDDLE_FREQ LP4X_DDR3200 : #define LP4X_LOW_FREQ LP4X_DDR1600 Consider aligning these 3 lines: ``` #define LP4X_HIGH_FREQ LP4X_DDR3600 #define LP4X_MIDDLE_FREQ LP4X_DDR3200 #define LP4X_LOW_FREQ LP4X_DDR1600 ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/34990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab6a9c2c390feeb9497b051a255b29566909e656 Gerrit-Change-Number: 34990 Gerrit-PatchSet: 2 Gerrit-Owner: huayang duan <huayangduan(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: SJ Huang <sj.huang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: huayang duan <huayangduan(a)gmail.com> Gerrit-CC: Huayang Duan <huayang.duan(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Thu, 22 Aug 2019 02:44:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit August 2019