coreboot-gerrit August 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: mediatek/mt8183: Enlarge PRERAM_CBFS_CACHE region
by Tristan Hsieh (Code Review) 21 Aug '19

21 Aug '19

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34896 ) Change subject: mediatek/mt8183: Enlarge PRERAM_CBFS_CACHE region ...................................................................... mediatek/mt8183: Enlarge PRERAM_CBFS_CACHE region Enlarge PRERAM_CBFS_CACHE region from (16K - 4) to (48K - 4) bytes to decompress and load more data from CBFS in romstage. BUG=b:134351649 BRANCH=none TEST=emerge-kukui coreboot Change-Id: Idc23a67c886718e910ca3c50468e5793f19c8d66 Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- M src/soc/mediatek/mt8183/include/soc/memlayout.ld 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/34896/1 diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld index d8d5f66..73c880a 100644 --- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld @@ -32,11 +32,11 @@ VBOOT2_TPM_LOG(0x00103000, 2K) PRERAM_CBMEM_CONSOLE(0x00103800, 14K) WATCHDOG_TOMBSTONE(0x00107000, 4) - PRERAM_CBFS_CACHE(0x00107004, 16K - 4) - TIMESTAMP(0x0010B000, 4K) - STACK(0x0010C000, 16K) - TTB(0x00110000, 28K) - DMA_COHERENT(0x00117000, 4K) + PRERAM_CBFS_CACHE(0x00107004, 48K - 4) + TIMESTAMP(0x00113000, 4K) + STACK(0x00114000, 16K) + TTB(0x00118000, 28K) + DMA_COHERENT(0x0011f000, 4K) SRAM_END(0x00120000) SRAM_L2C_START(0x00200000) -- To view, visit https://review.coreboot.org/c/coreboot/+/34896 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc23a67c886718e910ca3c50468e5793f19c8d66 Gerrit-Change-Number: 34896 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mediatek/mt8183: Overlap verstage and romstage in memory layout
by Tristan Hsieh (Code Review) 21 Aug '19

21 Aug '19

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34871 ) Change subject: mediatek/mt8183: Overlap verstage and romstage in memory layout ...................................................................... mediatek/mt8183: Overlap verstage and romstage in memory layout Since SRAM space is too small to fit all needed features, enable VBOOT_RETURN_FROM_VERSTAGE and overlap verstage and romstage to gain more space. BUG=b:134351649 BRANCH=none TEST=emerge-kukui coreboot Change-Id: Ibe336cf93b01fa2ea57b4c2e0a89685424878c91 Signed-off-by: Tristan Shieh <tristan.shieh(a)mediatek.com> --- M src/soc/mediatek/mt8183/Kconfig M src/soc/mediatek/mt8183/include/soc/memlayout.ld 2 files changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/34871/1 diff --git a/src/soc/mediatek/mt8183/Kconfig b/src/soc/mediatek/mt8183/Kconfig index c60cdea..9ac57bd 100644 --- a/src/soc/mediatek/mt8183/Kconfig +++ b/src/soc/mediatek/mt8183/Kconfig @@ -15,6 +15,7 @@ select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE + select VBOOT_RETURN_FROM_VERSTAGE config DEBUG_DRAM bool "Output verbose DRAM related debug messages" diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld index 6a11a0e..7da282e 100644 --- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld @@ -40,9 +40,9 @@ SRAM_END(0x00120000) SRAM_L2C_START(0x00200000) - OVERLAP_DECOMPRESSOR_ROMSTAGE(0x000201000, 152K) - BOOTBLOCK(0x00227000, 89K) - VERSTAGE(0x0023E000, 114K) + DECOMPRESSOR(0x00201000, 28K) + BOOTBLOCK(0x00208000, 64K) + OVERLAP_VERSTAGE_ROMSTAGE(0x00218000, 160K) SRAM_L2C_END(0x00280000) DRAM_START(0x40000000) -- To view, visit https://review.coreboot.org/c/coreboot/+/34871 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe336cf93b01fa2ea57b4c2e0a89685424878c91 Gerrit-Change-Number: 34871 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-MessageType: newchange

4 6

Change in ...coreboot[master]: mediatek: Support GPIO based SPI CS
by You-Cheng Syu (Code Review) 21 Aug '19

21 Aug '19

You-Cheng Syu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33165 Change subject: mediatek: Support GPIO based SPI CS ...................................................................... mediatek: Support GPIO based SPI CS In some cases we might want to use GPIO based SPI CS. When using GPIO based SPI CS, we need to manually make CS low/high before/after SPI transactions. BUG=b:132311067 TEST=Verified that b/132311067 is irreproducible now. Change-Id: I61653fb19242b6ee6be9a45545a8b66e5c9c7cad --- M src/soc/mediatek/common/include/soc/spi_common.h M src/soc/mediatek/common/spi.c 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/33165/1 diff --git a/src/soc/mediatek/common/include/soc/spi_common.h b/src/soc/mediatek/common/include/soc/spi_common.h index 162db59..2e87720 100644 --- a/src/soc/mediatek/common/include/soc/spi_common.h +++ b/src/soc/mediatek/common/include/soc/spi_common.h @@ -16,6 +16,7 @@ #ifndef MTK_COMMON_SPI_H #define MTK_COMMON_SPI_H +#include <soc/gpio_base.h> #include <spi-generic.h> enum { @@ -77,6 +78,7 @@ struct mtk_spi_regs *regs; int initialized; int state; + gpio_t *cs_gpio; }; extern const struct spi_ctrlr spi_ctrlr; diff --git a/src/soc/mediatek/common/spi.c b/src/soc/mediatek/common/spi.c index 71ed95a..c8aadbf 100644 --- a/src/soc/mediatek/common/spi.c +++ b/src/soc/mediatek/common/spi.c @@ -17,6 +17,7 @@ #include <assert.h> #include <console/console.h> #include <endian.h> +#include <gpio.h> #include <stdlib.h> #include <soc/pll.h> #include <soc/spi.h> @@ -87,6 +88,9 @@ clrsetbits_le32(&regs->spi_pad_macro_sel_reg, SPI_PAD_SEL_MASK, pad_select); + + if (slave->cs_gpio != NULL) + gpio_output(*slave->cs_gpio, 1); } static void mtk_spi_dump_data(const char *name, const uint8_t *data, int size) @@ -109,6 +113,9 @@ setbits_le32(&regs->spi_cmd_reg, 1 << SPI_CMD_PAUSE_EN_SHIFT); mtk_slave->state = MTK_SPI_IDLE; + if (mtk_slave->cs_gpio != NULL) + gpio_output(*mtk_slave->cs_gpio, 0); + return 0; } @@ -243,6 +250,9 @@ clrbits_le32(&regs->spi_cmd_reg, SPI_CMD_PAUSE_EN); spi_sw_reset(regs); mtk_slave->state = MTK_SPI_IDLE; + + if (mtk_slave->cs_gpio != NULL) + gpio_output(*mtk_slave->cs_gpio, 1); } static int spi_ctrlr_setup(const struct spi_slave *slave) -- To view, visit https://review.coreboot.org/c/coreboot/+/33165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61653fb19242b6ee6be9a45545a8b66e5c9c7cad Gerrit-Change-Number: 33165 Gerrit-PatchSet: 1 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib/bootsplash: Improve bootsplash logging
by Johanna Schander (Code Review) 21 Aug '19

21 Aug '19

Johanna Schander has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34598 ) Change subject: lib/bootsplash: Improve bootsplash logging ...................................................................... lib/bootsplash: Improve bootsplash logging Change-Id: Ib4a06d53c0134b99d3e9e6d3eda9fa30fca9ef7d Signed-off-by: Johanna Schander <coreboot(a)mimoja.de> --- M src/lib/bootsplash.c 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/34598/1 diff --git a/src/lib/bootsplash.c b/src/lib/bootsplash.c index 5527b23..e7f9ba1 100644 --- a/src/lib/bootsplash.c +++ b/src/lib/bootsplash.c @@ -25,7 +25,6 @@ { const vbe_mode_info_t *mode_info = vbe_mode_info(); if (mode_info != NULL) { - printk(BIOS_INFO, "Setting up bootsplash\n"); unsigned int x_resolution = le16_to_cpu(mode_info->vesa.x_resolution); unsigned int y_resolution = le16_to_cpu(mode_info->vesa.y_resolution); unsigned int fb_resolution = mode_info->vesa.bits_per_pixel; @@ -42,6 +41,8 @@ void set_bootsplash(unsigned char *framebuffer, unsigned int x_resolution, unsigned int y_resolution, unsigned int fb_resolution) { + printk(BIOS_INFO, "Setting up bootsplash in %dx%d@%d\n", x_resolution, y_resolution, + fb_resolution); struct jpeg_decdata *decdata; unsigned char *jpeg = cbfs_boot_map_with_leak("bootsplash.jpg", CBFS_TYPE_BOOTSPLASH, NULL); @@ -50,6 +51,11 @@ return; } + int image_width, image_height; + jpeg_fetch_size(jpeg, &image_width, &image_height); + + printk(BIOS_DEBUG, "Bootsplash resolution: %dx%d\n", image_width, image_height); + decdata = malloc(sizeof(*decdata)); int ret = jpeg_decode(jpeg, framebuffer, x_resolution, y_resolution, fb_resolution, decdata); -- To view, visit https://review.coreboot.org/c/coreboot/+/34598 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4a06d53c0134b99d3e9e6d3eda9fa30fca9ef7d Gerrit-Change-Number: 34598 Gerrit-PatchSet: 1 Gerrit-Owner: Johanna Schander <coreboot(a)mimoja.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/lenovo/h8: Add an option to set F1-F12 as primary function
by Iru Cai (vimacs) (Code Review) 21 Aug '19

21 Aug '19

Hello Iru Cai, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34639 to review the following change. Change subject: ec/lenovo/h8: Add an option to set F1-F12 as primary function ...................................................................... ec/lenovo/h8: Add an option to set F1-F12 as primary function Tested on Lenovo ThinkPad T440p. Change-Id: I83dc2c19341475abeeacd374a1b6cf152ec9b497 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- M src/ec/lenovo/h8/h8.c 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/34639/1 diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 2b959ce..46b83b6 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -86,6 +86,14 @@ ec_clr_bit(0x0, 3); } +static void f1_to_f12_as_primary(int on) +{ + if (on) + ec_set_bit(0x3b, 3); + else + ec_clr_bit(0x3b, 3); +} + static void h8_log_ec_version(void) { char ecfw[17]; @@ -334,6 +342,9 @@ val = 0; h8_sticky_fn(val); + if (get_option(&val, "f1_to_f12_as_primary") == CB_SUCCESS) + f1_to_f12_as_primary(val); + if (get_option(&val, "first_battery") != CB_SUCCESS) val = PRIMARY_BATTERY; h8_charge_priority(val); -- To view, visit https://review.coreboot.org/c/coreboot/+/34639 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I83dc2c19341475abeeacd374a1b6cf152ec9b497 Gerrit-Change-Number: 34639 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Iru Cai (vimacs) <mytbk920423(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/kohaku: Correct DPTF temp sensor IDs
by shkim (Code Review) 21 Aug '19

21 Aug '19

Hello Seunghwan Kim, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34985 to review the following change. Change subject: mb/google/kohaku: Correct DPTF temp sensor IDs ...................................................................... mb/google/kohaku: Correct DPTF temp sensor IDs This change corrects DPTF temperature sensor IDs BUG=none BRANCH=none TEST=none Change-Id: I25c76b0e938b2568da1833a4a5685ed36c00275e Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.com> --- M src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/34985/1 diff --git a/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl b/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl index f6fd907..375be8e 100644 --- a/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/hatch/variants/kohaku/include/variant/acpi/dptf.asl @@ -26,12 +26,12 @@ #define DPTF_TSR1_PASSIVE 65 #define DPTF_TSR1_CRITICAL 75 -#define DPTF_TSR2_SENSOR_ID 1 +#define DPTF_TSR2_SENSOR_ID 2 #define DPTF_TSR2_SENSOR_NAME "Thermal Sensor - IA" #define DPTF_TSR2_PASSIVE 65 #define DPTF_TSR2_CRITICAL 75 -#define DPTF_TSR3_SENSOR_ID 1 +#define DPTF_TSR3_SENSOR_ID 3 #define DPTF_TSR3_SENSOR_NAME "Thermal Sensor - GT" #define DPTF_TSR3_PASSIVE 65 #define DPTF_TSR3_CRITICAL 75 -- To view, visit https://review.coreboot.org/c/coreboot/+/34985 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25c76b0e938b2568da1833a4a5685ed36c00275e Gerrit-Change-Number: 34985 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
by Maxim Polyakov (Code Review) 21 Aug '19

21 Aug '19

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32734 ) Change subject: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF ...................................................................... Patch Set 74: (2 comments) https://review.coreboot.org/c/coreboot/+/32734/68/src/mainboard/supermicro/… File src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb: https://review.coreboot.org/c/coreboot/+/32734/68/src/mainboard/supermicro/… PS68, Line 28: register "SkipExtGfxScan" = "1" > No, as the aspeed VGA is assumed to be "onboard" as it's part of the devicetree and coreboot will di […] Ok, thanks for the clarification. https://review.coreboot.org/c/coreboot/+/32734/68/src/mainboard/supermicro/… PS68, Line 210: device pci 01.1 on > - I think it would be better to use width limit. […] Sorry, I meant "link training", not bus. "bus training" is the wrong term for this. -- To view, visit https://review.coreboot.org/c/coreboot/+/32734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 Gerrit-Change-Number: 32734 Gerrit-PatchSet: 74 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Keno Fischer <keno(a)alumni.harvard.edu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Name of user not set #1002358 Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: T. Hudson <trammell.hudson(a)gmail.com> Gerrit-Reviewer: Trammell Hudson <hudson(a)trmm.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Michael Niewöhner Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 21 Aug 2019 09:23:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: usbmsc: Skip zero-length packets at end of data
by Patrick Georgi (Code Review) 21 Aug '19

21 Aug '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34485 ) Change subject: libpayload: usbmsc: Skip zero-length packets at end of data ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/34485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I24f183f27b2c4f0142ba6c4b35b490c5798d0d21 Gerrit-Change-Number: 34485 Gerrit-PatchSet: 4 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Aug 2019 08:33:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload: usbmsc: Factor out usb_msc_force_init() function
by Patrick Georgi (Code Review) 21 Aug '19

21 Aug '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34227 ) Change subject: libpayload: usbmsc: Factor out usb_msc_force_init() function ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/34227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50392128409cb2a879954f234149a5e3b060a229 Gerrit-Change-Number: 34227 Gerrit-PatchSet: 3 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Aug 2019 08:31:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation/soc/intel: Add documentation for MCU update
by Varshit B Pandya (Code Review) 21 Aug '19

21 Aug '19

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35015 ) Change subject: Documentation/soc/intel: Add documentation for MCU update ...................................................................... Documentation/soc/intel: Add documentation for MCU update Change-Id: Ia1a9e77e44344dd2483fa88c8a51a25403267a13 Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> --- M Documentation/soc/intel/index.md D Documentation/soc/intel/ucode_update/Flash_Layout.PNG M Documentation/soc/intel/ucode_update/microcode_update_model.md 3 files changed, 50 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/35015/1 diff --git a/Documentation/soc/intel/index.md b/Documentation/soc/intel/index.md index f30ff9a..0cc4cc1 100644 --- a/Documentation/soc/intel/index.md +++ b/Documentation/soc/intel/index.md @@ -10,3 +10,4 @@ - [MP Initialization](mp_init/mp_init.md) - [Firmware Interface Table](fit.md) - [Apollolake](apollolake/index.md) +- [Microcode Update](ucode_update/microcode_update_model.md) diff --git a/Documentation/soc/intel/ucode_update/Flash_Layout.PNG b/Documentation/soc/intel/ucode_update/Flash_Layout.PNG deleted file mode 100644 index ac18977..0000000 --- a/Documentation/soc/intel/ucode_update/Flash_Layout.PNG +++ /dev/null Binary files differ diff --git a/Documentation/soc/intel/ucode_update/microcode_update_model.md b/Documentation/soc/intel/ucode_update/microcode_update_model.md index c7bcc74..9fe3c3b 100644 --- a/Documentation/soc/intel/ucode_update/microcode_update_model.md +++ b/Documentation/soc/intel/ucode_update/microcode_update_model.md @@ -2,42 +2,76 @@ ## Introduction -Processor microcode (MCU) is akin to processor firmware. Processors may need updates to their microcode to operate correctly. These updates fix bugs/errata that can cause anything from incorrect processing, to code and data corruption, and system lockups. +Processor microcode (MCU) is akin to processor firmware. Processors may +need updates to their microcode to operate correctly. These updates fix +bugs/errata that can cause anything from incorrect processing, to code +and data corruption, and system lockups. ##Problem Statement -As per chrome design, any field updatable FW has to be first verified by vboot (chrome root of trust - CROT) before it is allowed to run on the system. CROT executes on the CPU, hence FW such as MCU loaded before the CPU reset cannot be verified before it actually gets loaded. As a result today Chromebooks are not able to apply MCU in the field. This proposal tries to address the issue +As per chrome design, any field updatable FW has to be first verified +by vboot (chrome root of trust - CROT) before it is allowed to run on +the system. CROT executes on the CPU, hence FW such as MCU loaded before +the CPU reset cannot be verified before it actually gets loaded. As a +result today Chromebooks are not able to apply MCU in the field. This +proposal tries to address the issue -Prior to CPU reset, the CPU HW locates the FIT table from the storage, walks over the FIT table and picks-up the MCU that matches the CPU Family, Model, Stepping and PLATFORM ID with the highest revision ID. CPU verifies that MCU is signed by Intel and once verification is successful, it attempts to load the MCU. +Prior to CPU reset, the CPU HW locates the FIT table from the storage, +walks over the FIT table and picks-up the MCU that matches the CPU +Family, Model, Stepping and PLATFORM ID with the highest revision ID. +CPU verifies that MCU is signed by Intel and once verification is +successful, it attempts to load the MCU. -However FIT does not contain any fall back mechanism. If one MCU loading fails for whatever reason, it drops the further loading process and moves on to CPU reset. While it is fairly a remote chance, in case of any failure to load MCU which cause hang like situations before CPU reset, a platform based mechanism can be put in place to enter recovery mode. As detailed below, if we are using BUC register based top swap implementation, then an RTC reset may be required to clear top swap bit. +However FIT does not contain any fall back mechanism. If one MCU +loading fails for whatever reason, it drops the further loading process +and moves on to CPU reset. While it is fairly a remote chance, in case +of any failure to load MCU which cause hang like situations before CPU +reset, a platform based mechanism can be put in place to enter recovery +mode. As detailed below, if we are using BUC register based top swap +implementation, then an RTC reset may be required to clear top swap bit. ## Design Proposal The proposal relies on the following Intel SoC features: -1. Top swap, which enables the BIOS to have 2 bootblocks and bot from either using a RTC backed Top swap control bit in BUC register. +1. Top swap, which enables the BIOS to have 2 bootblocks and bot from +either using a RTC backed Top swap control bit in BUC register. 2. Firmware Interface Table (FIT) based MCU loading. -The idea is to have 2 bootblocks, each having its own FIT table. The FIT in one of them will be configured to point to an MCU in RO firmware, and the FIT in other one will point to a fixed flash region (aka MCU staging area), which will contain an MCU from RW firmware. +The idea is to have 2 bootblocks, each having its own FIT table. The FIT +in one of them will be configured to point to an MCU in RO firmware, and +the FIT in other one will point to a fixed flash region (aka MCU staging +area), which will contain an MCU from RW firmware. -Top-swap feature of Intel CPUs, will be used to switch between 2 bootblocks, based on the bootmode i.e., recovery or normal/developer mode. +Top-swap feature of Intel CPUs, will be used to switch between 2 +bootblocks, based on the bootmode i.e., recovery or normal/developer +mode. -coreboot will keep the MCU staging area updated with the MCU from the currently selected RW firmware. +coreboot will keep the MCU staging area updated with the MCU from the +currently selected RW firmware. ## Implementation Details -1. Create 2 BBs (bb_ro_ucode and bb_staged_ucode) each containing their own FIT tables. Both bootblocks will be in the RO section. - a. bb_ro_ucode contains a FIT which has pointer to MCU (microcode_blob.bin) which resides in RO section. This is will be used in the recovery scenario. - b. bb_staged_ucode is identical to bb_ro_ucode but contains a FIT which has pointer to a MCU that will reside in a staging area. +1. Create 2 BBs (bb_ro_ucode and bb_staged_ucode) each containing their +own FIT tables. Both bootblocks will be in the RO section. + a. bb_ro_ucode contains a FIT which has pointer to MCU + (microcode_blob.bin) which resides in RO section. This is will + be used in the recovery scenario. + b. bb_staged_ucode is identical to bb_ro_ucode but contains a + FIT which has pointer to a MCU that will reside in a staging + area. 2. Create a MCU staging area - a. Reserve a region in the FMAP which is equal to or greater than the MCU size specified in the BWG for that SoC. This is a RW region just lke the RW_MRC_CACHE. - b. MCU from RW-A/RW-B will be copied to this region during boot. - c. A Flash Protected Range (FPR) should be configured to write protect this MCU Staging area. + a. Reserve a region in the FMAP which is equal to or greater + than the MCU size specified in the BWG for that SoC. This is a + RW region just lke the RW_MRC_CACHE. + b. MCU from RW-A/RW-B will be copied to this region during + boot. + c. A Flash Protected Range (FPR) should be configured to write + protect this MCU Staging area. d. bb_staged_ucode FIT points to the MCU in this staging area. 3. The resulting flash layout is shown below, **Flash Layout** ![Flash Layout][flash_layout] -[flash_layout]: Flash_Layout.PNG +[flash_layout]: flash_layout.png 4. The proposed design uses the PCR register based control for top-swap -- To view, visit https://review.coreboot.org/c/coreboot/+/35015 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1a9e77e44344dd2483fa88c8a51a25403267a13 Gerrit-Change-Number: 35015 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit August 2019