coreboot-gerrit August 2019

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Change in coreboot[master]: intel/fsp_baytrail: Remove uses of #ifndef __PRE_RAM__
by Kyösti Mälkki (Code Review) 21 Aug '19

21 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34928 ) Change subject: intel/fsp_baytrail: Remove uses of #ifndef __PRE_RAM__ ...................................................................... intel/fsp_baytrail: Remove uses of #ifndef __PRE_RAM__ Either the files are only built for ramstage, or garbage collection takes care of it otherwise. Change-Id: Id295227df344fb209d7d5fd12e82aa450198bbb8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/intel/fsp1_0/fsp_util.c M src/drivers/intel/fsp1_0/fsp_util.h M src/soc/intel/fsp_baytrail/gpio.c M src/soc/intel/fsp_baytrail/include/soc/baytrail.h M src/soc/intel/fsp_baytrail/include/soc/romstage.h M src/soc/intel/fsp_baytrail/romstage/report_platform.c M src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c 7 files changed, 1 insertion(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/34928/1 diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c index d787c7b..c6c88cf 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.c +++ b/src/drivers/intel/fsp1_0/fsp_util.c @@ -25,7 +25,6 @@ #include <cpu/intel/microcode.h> #include <cf9_reset.h> -#ifndef __PRE_RAM__ /* Globals pointers for FSP structures */ void *FspHobListPtr = NULL; FSP_INFO_HEADER *fsp_header_ptr = NULL; @@ -60,9 +59,6 @@ if (Status != 0) printk(BIOS_ERR,"FSP API NotifyPhase failed for phase 0x%x with status: 0x%x\n", Phase, Status); } -#endif /* #ifndef __PRE_RAM__ */ - -#ifdef __PRE_RAM__ /* The FSP returns here after the fsp_early_init call */ static void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) @@ -115,7 +111,6 @@ /* Should never return. Control will continue from ContinuationFunc */ die("Uh Oh! FspInitApi returned"); } -#endif /* __PRE_RAM__ */ volatile u8 *find_fsp() { @@ -225,8 +220,6 @@ } #endif /* FSP_RESERVE_MEMORY_SIZE */ -#ifndef __PRE_RAM__ /* Only parse HOB data in ramstage */ - void print_fsp_info(void) { if (fsp_header_ptr == NULL) @@ -249,7 +242,6 @@ (u8)(fsp_header_ptr->ImageRevision & 0xff)); } - #if CONFIG(ENABLE_MRC_CACHE) /** * Save the FSP memory HOB (mrc data) to the MRC area in CBMEM @@ -363,4 +355,3 @@ /* Update the MRC/fast boot cache as part of the late table writing stage */ BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, find_fsp_hob_update_mrc, NULL); -#endif /* #ifndef __PRE_RAM__ */ diff --git a/src/drivers/intel/fsp1_0/fsp_util.h b/src/drivers/intel/fsp1_0/fsp_util.h index e09bbd9..a02e34d 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.h +++ b/src/drivers/intel/fsp1_0/fsp_util.h @@ -79,9 +79,7 @@ struct mrc_data_container *find_current_mrc_cache(void); -#if !defined(__PRE_RAM__) void update_mrc_cache(void *unused); -#endif #endif @@ -99,9 +97,7 @@ #define ERROR_INFO_HEAD_SIG_MISMATCH 5 #define ERROR_FSP_SIG_MISMATCH 6 -#ifndef __PRE_RAM__ extern void *FspHobListPtr; -#endif #define UPD_DEFAULT_CHECK(member) \ if (config->member != UPD_DEFAULT) { \ diff --git a/src/soc/intel/fsp_baytrail/gpio.c b/src/soc/intel/fsp_baytrail/gpio.c index 6da1258..3e2499a 100644 --- a/src/soc/intel/fsp_baytrail/gpio.c +++ b/src/soc/intel/fsp_baytrail/gpio.c @@ -29,13 +29,11 @@ * PCU iLB GPIO CFIO_SCORE Address Map * PCU iLB GPIO CFIO_SSUS Address Map */ -#ifndef __PRE_RAM__ static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] = { 19, 18, 17, 20, 21, 22, 24, 25, /* [ 0: 7] */ 23, 16, 14, 15, 12, 26, 27, 1, /* [ 8:15] */ 4, 8, 11, 0, 3, 6, 10, 13, /* [16:23] */ 2, 5, 9 }; /* [24:26] */ -#endif static const u8 gpscore_gpio_to_pad[GPSCORE_COUNT] = { 85, 89, 93, 96, 99, 102, 98, 101, /* [ 0: 7] */ @@ -61,8 +59,6 @@ 52, 53, 59, 40 }; /* [40:43] */ -#ifndef __PRE_RAM__ - /* GPIO bank descriptions */ static const struct gpio_bank gpncore_bank = { .gpio_count = GPNCORE_COUNT, @@ -253,7 +249,6 @@ printk(BIOS_DEBUG, "Default/empty GPIO config\n"); return NULL; } -#endif /* #ifndef __PRE_RAM__ */ /** \brief returns the input / output value from an SCORE GPIO * diff --git a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h index 34831b1..fa2f508 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h +++ b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h @@ -51,7 +51,6 @@ int bridge_silicon_revision(void); void rangeley_early_initialization(void); -#ifndef __PRE_RAM__ /* soc.c */ int soc_silicon_revision(void); int soc_silicon_type(void); @@ -60,7 +59,6 @@ void report_platform_info(void); -#endif /* __PRE_RAM__ */ #endif /* __ASSEMBLER__ */ #endif /* __ACPI__ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/romstage.h b/src/soc/intel/fsp_baytrail/include/soc/romstage.h index 5f0bd8d..1f318b3 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/romstage.h +++ b/src/soc/intel/fsp_baytrail/include/soc/romstage.h @@ -21,8 +21,6 @@ #error "Don't include romstage.h from a ramstage compilation unit!" #endif -void report_platform_info(void); - #include <stdint.h> #include <drivers/intel/fsp1_0/fsp_util.h> diff --git a/src/soc/intel/fsp_baytrail/romstage/report_platform.c b/src/soc/intel/fsp_baytrail/romstage/report_platform.c index 98f35f0..2b5dad7 100644 --- a/src/soc/intel/fsp_baytrail/romstage/report_platform.c +++ b/src/soc/intel/fsp_baytrail/romstage/report_platform.c @@ -17,7 +17,7 @@ #include <console/console.h> #include <device/pci_ops.h> #include <soc/iosf.h> -#include <soc/romstage.h> +#include <soc/baytrail.h> #include <cpu/x86/msr.h> #include <soc/msr.h> #include <cpu/x86/name.h> diff --git a/src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c b/src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c index ba56543..bbcf753 100644 --- a/src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c +++ b/src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c @@ -43,9 +43,7 @@ // // Pointer to the HOB should be initialized with the output of FSP INIT PARAMS // -#ifndef __PRE_RAM__ extern volatile void *FspHobListPtr; -#endif /** Reads a 64-bit value from memory that may be unaligned. @@ -116,12 +114,8 @@ VOID ) { -#ifndef __PRE_RAM__ ASSERT (FspHobListPtr != NULL); return ((VOID *)FspHobListPtr); -#else - return ((VOID *)NULL); -#endif } /** -- To view, visit https://review.coreboot.org/c/coreboot/+/34928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id295227df344fb209d7d5fd12e82aa450198bbb8 Gerrit-Change-Number: 34928 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: southbridge/intel: Tidy up preprocessor and headers
by Kyösti Mälkki (Code Review) 21 Aug '19

21 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34980 ) Change subject: southbridge/intel: Tidy up preprocessor and headers ...................................................................... southbridge/intel: Tidy up preprocessor and headers Change-Id: I52a7b39566acd64ac21a345046675e05649a40f5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/bd82x6x/pcie.c M src/southbridge/intel/bd82x6x/sata.c M src/southbridge/intel/bd82x6x/usb_xhci.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/ibexpeak/me.h M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/ibexpeak/sata.c M src/southbridge/intel/lynxpoint/chip.h M src/southbridge/intel/lynxpoint/lp_gpio.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/me.h M src/southbridge/intel/lynxpoint/me_9.x.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/pcie.c M src/southbridge/intel/lynxpoint/sata.c M src/southbridge/intel/lynxpoint/serialio.c M src/southbridge/intel/lynxpoint/usb_xhci.c 22 files changed, 42 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/34980/1 diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index e3379d6..744fe7d 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -23,6 +23,8 @@ #include <device/mmio.h> #include <delay.h> #include <device/azalia_device.h> + +#include "chip.h" #include "pch.h" #define HDA_ICII_REG 0x68 diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index bd3c993..592c70f 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -32,6 +32,7 @@ #include <cpu/x86/smm.h> #include <cbmem.h> #include <string.h> +#include "chip.h" #include "pch.h" #include "nvs.h" #include <southbridge/intel/common/pciehp.h> diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index 2708864..203d0c0 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -238,17 +238,14 @@ /* Defined in me_status.c for both romstage and ramstage */ void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes); -#ifdef __PRE_RAM__ void intel_early_me_status(void); int intel_early_me_init(void); int intel_early_me_uma_size(void); int intel_early_me_init_done(u8 status); -#endif -#ifdef __SMM__ void intel_me_finalize_smm(void); void intel_me8_finalize_smm(void); -#endif + typedef struct { u32 major_version : 16; u32 minor_version : 16; diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index e4eccd7..475def3 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -24,9 +24,11 @@ #include <device/pci.h> #endif #include <device/pci_ops.h> -#include "pch.h" #include <string.h> +#include "chip.h" +#include "pch.h" + int pch_silicon_revision(void) { static int pch_revision_id = -1; diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index bc6c8b3..fcb15ac 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -56,20 +56,19 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 -#if !defined(__ASSEMBLER__) -#if !defined(__PRE_RAM__) -#if !defined(__SIMPLE_DEVICE__) -#include "chip.h" -void pch_enable(struct device *dev); -#endif + int pch_silicon_revision(void); int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -#else /* __PRE_RAM__ */ + void enable_smbus(void); void enable_usb_bar(void); + +#if ENV_ROMSTAGE int smbus_read_byte(unsigned device, unsigned address); +#endif + void early_thermal_init(void); void southbridge_configure_default_intmap(void); void southbridge_rcba_config(void); @@ -87,14 +86,11 @@ }; #ifndef __ROMCC__ +void pch_enable(struct device *dev); extern const struct southbridge_usb_port mainboard_usb_ports[14]; #endif -void -early_usb_init (const struct southbridge_usb_port *portmap); - -#endif -#endif +void early_usb_init(const struct southbridge_usb_port *portmap); /* PM I/O Space */ #define UPRWC 0x3c diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 97306e4..686930d 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -22,6 +22,8 @@ #include <device/pci_ids.h> #include <southbridge/intel/common/pciehp.h> #include <assert.h> + +#include "chip.h" #include "pch.h" static void pch_pcie_pm_early(struct device *dev) diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 6a39873..3ec065f 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -24,6 +24,7 @@ #include <acpi/sata.h> #include <types.h> +#include "chip.h" #include "pch.h" typedef struct southbridge_intel_bd82x6x_config config_t; diff --git a/src/southbridge/intel/bd82x6x/usb_xhci.c b/src/southbridge/intel/bd82x6x/usb_xhci.c index 85e450d..55c8948 100644 --- a/src/southbridge/intel/bd82x6x/usb_xhci.c +++ b/src/southbridge/intel/bd82x6x/usb_xhci.c @@ -21,6 +21,7 @@ #include "pch.h" #include <device/pci_ehci.h> #include <device/pci_ops.h> +#include "chip.h" static void usb_xhci_init(struct device *dev) { diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index c7464a0..a6bbe64 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -34,6 +34,7 @@ #include <cbmem.h> #include <string.h> #include <cpu/x86/smm.h> +#include "chip.h" #include "pch.h" #include "nvs.h" #include <southbridge/intel/common/pciehp.h> diff --git a/src/southbridge/intel/ibexpeak/me.h b/src/southbridge/intel/ibexpeak/me.h index be65cc5..5694dd7 100644 --- a/src/southbridge/intel/ibexpeak/me.h +++ b/src/southbridge/intel/ibexpeak/me.h @@ -239,17 +239,14 @@ /* Defined in me_status.c for both romstage and ramstage */ void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes); -#ifdef __PRE_RAM__ void intel_early_me_status(void); int intel_early_me_init(void); int intel_early_me_uma_size(void); int intel_early_me_init_done(u8 status); -#endif -#ifdef __SMM__ void intel_me_finalize_smm(void); void intel_me8_finalize_smm(void); -#endif + typedef struct { u32 major_version : 16; u32 minor_version : 16; diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 24a7905..ee0f9ad 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -51,29 +51,26 @@ #ifndef __ACPI__ #define DEBUG_PERIODIC_SMIS 0 -#if !defined(__ASSEMBLER__) -#if !defined(__PRE_RAM__) -#if !defined(__SIMPLE_DEVICE__) -#include "chip.h" -void pch_enable(struct device *dev); -#endif int pch_silicon_revision(void); int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -#if CONFIG(ELOG) -void pch_log_state(void); -#endif -#else /* __PRE_RAM__ */ void enable_smbus(void); void enable_usb_bar(void); + +#if ENV_ROMSTAGE int smbus_read_byte(unsigned device, unsigned address); int smbus_write_byte(unsigned device, unsigned address, u8 data); int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf); int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf); +#endif + void early_thermal_init(void); void southbridge_configure_default_intmap(void); -#endif + +#ifndef __ROMCC__ +#include <device/device.h> +void pch_enable(struct device *dev); #endif #define MAINBOARD_POWER_OFF 0 diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index e03f8b5..c99e944 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -25,6 +25,7 @@ #include <acpi/sata.h> #include <types.h> +#include "chip.h" #include "pch.h" typedef struct southbridge_intel_ibexpeak_config config_t; diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index b91ab15..e56b32b 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -117,6 +117,5 @@ bool docking_supported; }; -extern struct chip_operations southbridge_intel_lynxpoint_ops; #endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H */ diff --git a/src/southbridge/intel/lynxpoint/lp_gpio.c b/src/southbridge/intel/lynxpoint/lp_gpio.c index e3d8f02..bc8d8a1 100644 --- a/src/southbridge/intel/lynxpoint/lp_gpio.c +++ b/src/southbridge/intel/lynxpoint/lp_gpio.c @@ -24,7 +24,7 @@ static u16 get_gpio_base(void) { -#if defined(__PRE_RAM__) || defined(__SMM__) +#ifdef __SIMPLE_DEVICE__ return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; #else return pci_read_config16(pcidev_on_root(0x1f, 0), diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 84032ca..28e3544 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -30,6 +30,7 @@ #include <cpu/x86/smm.h> #include <cbmem.h> #include <string.h> +#include "chip.h" #include "nvs.h" #include "pch.h" #include <arch/acpigen.h> diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h index 775b4ec..3b4bd51 100644 --- a/src/southbridge/intel/lynxpoint/me.h +++ b/src/southbridge/intel/lynxpoint/me.h @@ -326,17 +326,13 @@ /* Defined in me_status.c for both romstage and ramstage */ void intel_me_status(struct me_hfs *hfs, struct me_hfs2 *hfs2); -#ifdef __PRE_RAM__ void intel_early_me_status(void); int intel_early_me_init(void); int intel_early_me_uma_size(void); int intel_early_me_init_done(u8 status); -#endif -#ifdef __SMM__ void intel_me_finalize_smm(void); void intel_me8_finalize_smm(void); -#endif /* * ME to BIOS Payload Datastructures and definitions. The ordering of the diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 09eeff2..8d86e68 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -35,6 +35,7 @@ #include <elog.h> #include <halt.h> +#include "chip.h" #include "me.h" #include "pch.h" diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 540a4d3..3f37887 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -88,13 +88,10 @@ #ifndef __ACPI__ -#if defined(__SMM__) && !defined(__ASSEMBLER__) void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ); void usb_ehci_disable(pci_devfn_t dev); void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ); void usb_xhci_route_all(void); -#endif - /* State Machine configuration. */ #define RCBA_REG_SIZE_MASK 0x8000 @@ -135,7 +132,6 @@ u32 or_value; }; -#if !defined(__ASSEMBLER__) void pch_config_rcba(const struct rcba_config_instruction *rcba_config); int pch_silicon_revision(void); int pch_silicon_id(void); @@ -169,30 +165,26 @@ void enable_gpe(u32 mask); void disable_gpe(u32 mask); -#if !defined(__PRE_RAM__) && !defined(__SMM__) -#include <device/device.h> -#include "chip.h" void pch_enable(struct device *dev); void pch_disable_devfn(struct device *dev); u32 pch_iobp_read(u32 address); void pch_iobp_write(u32 address, u32 data); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -#if CONFIG(ELOG) void pch_log_state(void); -#endif void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); -#else void enable_smbus(void); -void enable_usb_bar(void); + +#if ENV_ROMSTAGE int smbus_read_byte(unsigned device, unsigned address); +#endif + +void enable_usb_bar(void); int early_pch_init(const void *gpio_map, const struct rcba_config_instruction *rcba_config); void pch_enable_lpc(void); void mainboard_config_superio(void); -#endif /* !__PRE_RAM__ && !__SMM__ */ -#endif /* __ASSEMBLER__ */ #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 2a8b44e..a3b2e09 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -26,6 +26,7 @@ #include <southbridge/intel/common/gpio.h> #include <stddef.h> #include <stdint.h> +#include "chip.h" #define MAX_NUM_ROOT_PORTS 8 diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index fd611ea..aae48e7 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -21,6 +21,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <delay.h> +#include "chip.h" #include "pch.h" typedef struct southbridge_intel_lynxpoint_config config_t; diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 23d8125..b5ccfa6 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -22,6 +22,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <stdlib.h> +#include "chip.h" #include "pch.h" #include "nvs.h" diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index ddba351..686e06a 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -21,6 +21,7 @@ #include <arch/io.h> #include <device/mmio.h> #include <device/pci_ops.h> +#include "chip.h" #include "pch.h" typedef struct southbridge_intel_lynxpoint_config config_t; -- To view, visit https://review.coreboot.org/c/coreboot/+/34980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52a7b39566acd64ac21a345046675e05649a40f5 Gerrit-Change-Number: 34980 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 11

Change in coreboot[master]: samsung/exynos,qualcomm/ipq: Avoid conflicting DRAM_START
by Kyösti Mälkki (Code Review) 21 Aug '19

21 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35012 ) Change subject: samsung/exynos,qualcomm/ipq: Avoid conflicting DRAM_START ...................................................................... samsung/exynos,qualcomm/ipq: Avoid conflicting DRAM_START There is duplicate definition in <memlayout.h> that gets indirectly included with followup work. Change-Id: I1c41052542b215de8af3be858ca7a229e4206ecf Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/daisy/mainboard.c M src/mainboard/google/gale/mmu.c M src/mainboard/google/peach_pit/mainboard.c M src/mainboard/google/storm/mmu.c 4 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/35012/1 diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c index 46939b7..0a1701c 100644 --- a/src/mainboard/google/daisy/mainboard.c +++ b/src/mainboard/google/daisy/mainboard.c @@ -37,6 +37,9 @@ #define MMC0_GPIO_PIN (58) +/* Conflicting definition from <memlayout.h> we do not need here. */ +#undef DRAM_START + /* convenient shorthand (in MB) */ #define DRAM_START ((uintptr_t)_dram/MiB) #define DRAM_SIZE CONFIG_DRAM_SIZE_MB diff --git a/src/mainboard/google/gale/mmu.c b/src/mainboard/google/gale/mmu.c index bf46f7a..d178295 100644 --- a/src/mainboard/google/gale/mmu.c +++ b/src/mainboard/google/gale/mmu.c @@ -15,6 +15,9 @@ #include <soc/soc_services.h> #include "mmu.h" +/* Conflicting definition from <memlayout.h> we do not need here. */ +#undef DRAM_START + #define WIFI_IMEM_0_START ((uintptr_t)_wifi_imem_0 / KiB) #define WIFI_IMEM_0_END ((uintptr_t)_ewifi_imem_0 / KiB) #define WIFI_IMEM_1_START ((uintptr_t)_wifi_imem_1 / KiB) diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c index ecd2260..86d18a0 100644 --- a/src/mainboard/google/peach_pit/mainboard.c +++ b/src/mainboard/google/peach_pit/mainboard.c @@ -38,6 +38,9 @@ #include <symbols.h> #include <vbe.h> +/* Conflicting definition from <memlayout.h> we do not need here. */ +#undef DRAM_START + /* convenient shorthand (in MB) */ #define DRAM_START ((uintptr_t)_dram/MiB) #define DRAM_SIZE CONFIG_DRAM_SIZE_MB diff --git a/src/mainboard/google/storm/mmu.c b/src/mainboard/google/storm/mmu.c index 9750cc1..91976e7 100644 --- a/src/mainboard/google/storm/mmu.c +++ b/src/mainboard/google/storm/mmu.c @@ -15,6 +15,9 @@ #include <symbols.h> #include "mmu.h" +/* Conflicting definition from <memlayout.h> we do not need here. */ +#undef DRAM_START + /* convenient shorthand (in MB) */ #define RPM_START ((uintptr_t)_rpm / KiB) #define RPM_END ((uintptr_t)_erpm / KiB) -- To view, visit https://review.coreboot.org/c/coreboot/+/35012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c41052542b215de8af3be858ca7a229e4206ecf Gerrit-Change-Number: 35012 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 5

Change in ...coreboot[master]: vboot: use vboot2 API to set initial secdatak value
by Joel Kitching (Code Review) 21 Aug '19

21 Aug '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33386 Change subject: vboot: use vboot2 API to set initial secdatak value ...................................................................... vboot: use vboot2 API to set initial secdatak value Previously, the initial value for secdatak was embedded in secdata_tpm.c as a uint8_t array. Switch to using vb2api_secdatak_create instead, and write the value in ctx->secdatak. Remove an unnecessary call to vb2api_secdata_create in _factory_initialize_tpm. BUG=b:124141368 TEST=make clean && make test-abuild BRANCH=none Change-Id: I74261453df6cc55ef3f38d8fb922bcc604084c0a Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/security/vboot/secdata_tpm.c 1 file changed, 9 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/33386/1 diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 39cd614..ff62185 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -149,18 +149,6 @@ } /* - * This is derived from rollback_index.h of vboot_reference. see struct - * RollbackSpaceKernel for details. - */ -static const uint8_t secdata_kernel[] = { - 0x02, - 0x4C, 0x57, 0x52, 0x47, - 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, - 0xE8, -}; - -/* * This is used to initialize the TPM space for recovery hash after defining * it. Since there is no data available to calculate hash at the point where TPM * space is defined, initialize it to all 0s. @@ -241,7 +229,7 @@ static uint32_t set_kernel_space(const void *kernel_blob) { return set_space("kernel", KERNEL_NV_INDEX, kernel_blob, - sizeof(secdata_kernel), rw_space_attributes, NULL, 0); + VB2_SECDATAK_SIZE, rw_space_attributes, NULL, 0); } static uint32_t set_rec_hash_space(const uint8_t *data) @@ -262,7 +250,7 @@ * indication that TPM factory initialization was successfully * completed. */ - RETURN_ON_FAILURE(set_kernel_space(secdata_kernel)); + RETURN_ON_FAILURE(set_kernel_space(ctx->secdatak)); if (CONFIG(VBOOT_HAS_REC_HASH_SPACE)) RETURN_ON_FAILURE(set_rec_hash_space(rec_hash_data)); @@ -366,16 +354,15 @@ VBDEBUG("TPM: Clearing owner\n"); RETURN_ON_FAILURE(tpm_clear_and_reenable()); - /* Define and initialize the kernel space */ + /* Define and write secdatak kernel space. */ RETURN_ON_FAILURE(safe_define_space(KERNEL_NV_INDEX, TPM_NV_PER_PPWRITE, - sizeof(secdata_kernel))); + VB2_SECDATAK_SIZE)); RETURN_ON_FAILURE(write_secdata(KERNEL_NV_INDEX, - secdata_kernel, - sizeof(secdata_kernel))); + ctx->secdatak, + VB2_SECDATAK_SIZE)); - /* Defines and sets vb2 secdata space */ - vb2api_secdata_create(ctx); + /* Define and write secdata firmware space. */ RETURN_ON_FAILURE(safe_define_space(FIRMWARE_NV_INDEX, TPM_NV_PER_GLOBALLOCK | TPM_NV_PER_PPWRITE, @@ -417,8 +404,9 @@ { uint32_t result; - /* Defines and sets vb2 secdata space */ + /* Set initial values of secdata and secdatak spaces. */ vb2api_secdata_create(ctx); + vb2api_secdatak_create(ctx); VBDEBUG("TPM: factory initialization\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/33386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74261453df6cc55ef3f38d8fb922bcc604084c0a Gerrit-Change-Number: 33386 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

2 7

Change in coreboot[master]: mb/google/kahlee/treeya: Update Raydium TS device ACPI nodes
by chris wang (Code Review) 21 Aug '19

21 Aug '19

Hello Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34987 to review the following change. Change subject: mb/google/kahlee/treeya: Update Raydium TS device ACPI nodes ...................................................................... mb/google/kahlee/treeya: Update Raydium TS device ACPI nodes Update I2C irq to EDGE trigger for Raydium TS. BUG=b:135551210 BRANCH=master TEST=emerge-grunt coreboot Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: Ic0a00a31eefa756b6e4ee9aac8d25c1be5ac9195 --- M src/mainboard/google/kahlee/variants/grunt/devicetree.cb M src/mainboard/google/kahlee/variants/treeya/devicetree.cb 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/34987/1 diff --git a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb index d73c47c..a0a1876 100644 --- a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb @@ -146,7 +146,7 @@ register "hid" = ""RAYD0001"" register "desc" = ""Raydium Touchscreen"" register "probed" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_11)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" register "reset_delay_ms" = "20" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" diff --git a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb index d73c47c..a0a1876 100644 --- a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb @@ -146,7 +146,7 @@ register "hid" = ""RAYD0001"" register "desc" = ""Raydium Touchscreen"" register "probed" = "1" - register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_11)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" register "reset_delay_ms" = "20" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" -- To view, visit https://review.coreboot.org/c/coreboot/+/34987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0a00a31eefa756b6e4ee9aac8d25c1be5ac9195 Gerrit-Change-Number: 34987 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/google/kahlee/treeya: remove keyboard backlight support
by chris wang (Code Review) 21 Aug '19

21 Aug '19

Hello Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34903 to review the following change. Change subject: mb/google/kahlee/treeya: remove keyboard backlight support ...................................................................... mb/google/kahlee/treeya: remove keyboard backlight support Treeya doesn't support the keyboard backlight. BUG=b:135551210 BRANCH=grunt TEST=emerge-grunt coreboot Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: I02dfc77d3cb7ac00b3f10d577d92775db99c1bdf --- M src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/34903/1 diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h b/src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h index 4a1c7fc..2d48018 100644 --- a/src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h @@ -15,9 +15,6 @@ #include <baseboard/ec.h> -/* Enable EC backed Keyboard Backlight in ACPI */ -#define EC_ENABLE_KEYBOARD_BACKLIGHT - /* Enable Tablet switch */ #define EC_ENABLE_TBMC_DEVICE -- To view, visit https://review.coreboot.org/c/coreboot/+/34903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02dfc77d3cb7ac00b3f10d577d92775db99c1bdf Gerrit-Change-Number: 34903 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/google/kahlee/treeya: Use GPIO_10 for EC_SYNC_IRQ
by chris wang (Code Review) 21 Aug '19

21 Aug '19

Hello Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34902 to review the following change. Change subject: mb/google/kahlee/treeya: Use GPIO_10 for EC_SYNC_IRQ ...................................................................... mb/google/kahlee/treeya: Use GPIO_10 for EC_SYNC_IRQ Use AGPIO 10 as the EC sync interrupt for MKBP events for sensor data. Reference to Aleena project. BUG=b:135551210 BRANCH=grunt TEST=emerge-grunt coreboot Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: Ie0b719ebce90710bca2109b7ff255e19329f9cac --- M src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h M src/mainboard/google/kahlee/variants/treeya/include/variant/gpio.h 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/34902/1 diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h b/src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h index 73e07ae..4a1c7fc 100644 --- a/src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h @@ -20,3 +20,9 @@ /* Enable Tablet switch */ #define EC_ENABLE_TBMC_DEVICE + +/* + * Enable EC sync interrupt via GPIO controller, EC_SYNC_IRQ is defined in + * variant/gpio.h + */ +#define EC_ENABLE_SYNC_IRQ_GPIO diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/treeya/include/variant/gpio.h index 5a6b540..3ddabb1 100644 --- a/src/mainboard/google/kahlee/variants/treeya/include/variant/gpio.h +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/gpio.h @@ -14,3 +14,6 @@ */ #include <baseboard/gpio.h> + +/* EC sync irq is AGPIO 10 */ +#define EC_SYNC_IRQ 10 -- To view, visit https://review.coreboot.org/c/coreboot/+/34902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0b719ebce90710bca2109b7ff255e19329f9cac Gerrit-Change-Number: 34902 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/google/kahlee/treeya: Add EC_ENABLE_TBMC_DEVICE
by chris wang (Code Review) 21 Aug '19

21 Aug '19

Hello Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34899 to review the following change. Change subject: mb/google/kahlee/treeya: Add EC_ENABLE_TBMC_DEVICE ...................................................................... mb/google/kahlee/treeya: Add EC_ENABLE_TBMC_DEVICE Enable ACPI TBMC notification on tablet mode change to support convertible treeya devices. BUG=b:135551210 BRANCH=grunt TEST=emerge-grunt coreboot Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Change-Id: Id0618c8df66267b88008dc5057892de6b530629f --- M src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/34899/1 diff --git a/src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h b/src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h index 96388ae..73e07ae 100644 --- a/src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h +++ b/src/mainboard/google/kahlee/variants/treeya/include/variant/ec.h @@ -1,4 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #include <baseboard/ec.h> /* Enable EC backed Keyboard Backlight in ACPI */ #define EC_ENABLE_KEYBOARD_BACKLIGHT + +/* Enable Tablet switch */ +#define EC_ENABLE_TBMC_DEVICE -- To view, visit https://review.coreboot.org/c/coreboot/+/34899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0618c8df66267b88008dc5057892de6b530629f Gerrit-Change-Number: 34899 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: mb/google/kahlee/treeya: Enable Synaptics touchpad and Synaptics touc...
by Peichao Li (Code Review) 21 Aug '19

21 Aug '19

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35000 ) Change subject: mb/google/kahlee/treeya: Enable Synaptics touchpad and Synaptics touchscreen ...................................................................... mb/google/kahlee/treeya: Enable Synaptics touchpad and Synaptics touchscreen BUG=b:139699619 TEST=emerge-grunt coreboot chromeos-bootimage flash bios image to DUT and make sure the touchpad and touchscreen can work Signed-off-by: Peichao.Wang <peichao.wang(a)bitland.corp-partner.google.com> Change-Id: I002badd49e678e1c32c802352923ca51efb45cef --- M src/mainboard/google/kahlee/variants/treeya/devicetree.cb 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/35000/1 diff --git a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb index d73c47c..81f4002 100644 --- a/src/mainboard/google/kahlee/variants/treeya/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/treeya/devicetree.cb @@ -138,10 +138,33 @@ register "desc" = ""ELAN Touchpad"" register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" register "wake" = "7" + register "probed" = "1" device i2c 15 on end end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" + register "generic.wake" = "7" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x2c on end + end end device mmio 0xfedc5000 on + chip drivers/i2c/hid + register "generic.hid" = ""SYTS7817"" + register "generic.desc" = ""Synaptics Touchscreen"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + register "generic.reset_delay_ms" = "45" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 20 on end + end chip drivers/i2c/generic register "hid" = ""RAYD0001"" register "desc" = ""Raydium Touchscreen"" -- To view, visit https://review.coreboot.org/c/coreboot/+/35000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I002badd49e678e1c32c802352923ca51efb45cef Gerrit-Change-Number: 35000 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload: usbmsc: Factor out usb_msc_force_init() function
by Julius Werner (Code Review) 21 Aug '19

21 Aug '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34227 ) Change subject: libpayload: usbmsc: Factor out usb_msc_force_init() function ...................................................................... Patch Set 3: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/34227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I50392128409cb2a879954f234149a5e3b060a229 Gerrit-Change-Number: 34227 Gerrit-PatchSet: 3 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 21 Aug 2019 00:07:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit August 2019