coreboot-gerrit August 2019

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Change in ...coreboot[master]: mb/{asrock,intel,purism}: Copy channel arrays separately
by Jacob Garber (Code Review) 20 Aug '19

20 Aug '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33135 Change subject: mb/{asrock,intel,purism}: Copy channel arrays separately ...................................................................... mb/{asrock,intel,purism}: Copy channel arrays separately DqByteMapCh0 and DqByteMapCh1 are declared adjacently in the FSP_M_CONFIG struct, so it is tempting to begin memcpy at the address of the first array and overwrite both of them at once. However, FSP_M_CONFIG is not declared with the packed attribute, so this is not guaranteed to work and is undefined behaviour to boot. It is cleaner and less tricky to copy them independently. The same is true for DqsMapCpu2DramCh0 and DqsMapCpu2DramCh1, so we change those as well. Change-Id: Ic6bb2bd5773af24329575926dbc70e0211f29051 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Found-by: Coverity CID 136538{8,9}, 140134{1,4} --- M src/mainboard/asrock/h110m/romstage.c M src/mainboard/intel/kblrvp/romstage.c M src/mainboard/intel/kblrvp/spd/spd.h M src/mainboard/intel/kblrvp/spd/spd_util.c M src/mainboard/intel/kunimitsu/romstage.c M src/mainboard/intel/kunimitsu/romstage_fsp20.c M src/mainboard/intel/kunimitsu/spd/spd.h M src/mainboard/intel/kunimitsu/spd/spd_util.c M src/mainboard/intel/saddlebrook/romstage.c M src/mainboard/intel/saddlebrook/spd/spd.h M src/mainboard/intel/saddlebrook/spd/spd_util.c M src/mainboard/purism/librem_skl/romstage.c 12 files changed, 60 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/33135/1 diff --git a/src/mainboard/asrock/h110m/romstage.c b/src/mainboard/asrock/h110m/romstage.c index 4961a79..6df4539 100644 --- a/src/mainboard/asrock/h110m/romstage.c +++ b/src/mainboard/asrock/h110m/romstage.c @@ -20,7 +20,7 @@ #define RCOMP_TARGET_PARAMS 0x5 -static void mainboard_fill_dq_map_data(void *dq_map_ptr) +static void mainboard_fill_dq_map_data(u8 *dq_map_ch0, u8 *dq_map_ch1) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -28,16 +28,18 @@ 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; - memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); + memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0])); + memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1])); } -static void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +static void mainboard_fill_dqs_map_data(u8 *dqs_map_ch0, u8 *dqs_map_ch1) { /* DQS CPU<>DRAM map */ const u8 dqs_map[2][8] = { { 0, 1, 3, 2, 4, 5, 6, 7 }, { 1, 0, 4, 5, 2, 3, 6, 7 } }; - memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); + memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0])); + memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1])); } static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) @@ -64,8 +66,10 @@ }; mem_cfg = &mupd->FspmConfig; - mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); - mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, + &mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, + &mem_cfg->DqsMapCpu2DramCh1); mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c index 1a483bd..3f52a13 100644 --- a/src/mainboard/intel/kblrvp/romstage.c +++ b/src/mainboard/intel/kblrvp/romstage.c @@ -36,8 +36,10 @@ printk(BIOS_INFO, "SPD index %d\n", spd_index); - mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); - mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, + &mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, + &mem_cfg->DqsMapCpu2DramCh1); mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); diff --git a/src/mainboard/intel/kblrvp/spd/spd.h b/src/mainboard/intel/kblrvp/spd/spd.h index c24baa0..8164ddb 100644 --- a/src/mainboard/intel/kblrvp/spd/spd.h +++ b/src/mainboard/intel/kblrvp/spd/spd.h @@ -22,8 +22,8 @@ #define RCOMP_TARGET_PARAMS 0x5 -void mainboard_fill_dq_map_data(void *dq_map_ptr); -void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_dq_map_data(u8 *dq_map_ch0, u8 *dq_map_ch1); +void mainboard_fill_dqs_map_data(u8 *dqs_map_ch0, u8 *dqs_map_ch1); void mainboard_fill_rcomp_res_data(void *rcomp_ptr); void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); #endif diff --git a/src/mainboard/intel/kblrvp/spd/spd_util.c b/src/mainboard/intel/kblrvp/spd/spd_util.c index f22dcaa..0218ae1 100644 --- a/src/mainboard/intel/kblrvp/spd/spd_util.c +++ b/src/mainboard/intel/kblrvp/spd/spd_util.c @@ -20,7 +20,7 @@ #include "../board_id.h" #include "spd.h" -void mainboard_fill_dq_map_data(void *dq_map_ptr) +void mainboard_fill_dq_map_data(u8 *dq_map_ch0, u8 *dq_map_ch1) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -28,16 +28,18 @@ 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; - memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); + memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0])); + memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1])); } -void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +void mainboard_fill_dqs_map_data(u8 *dqs_map_ch0, u8 *dqs_map_ch1) { /* DQS CPU<>DRAM map */ const u8 dqs_map[2][8] = { { 0, 1, 3, 2, 4, 5, 6, 7 }, { 1, 0, 4, 5, 2, 3, 6, 7 } }; - memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); + memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0])); + memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1])); } void mainboard_fill_rcomp_res_data(void *rcomp_ptr) diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c index f900ca3..0312ad1 100644 --- a/src/mainboard/intel/kunimitsu/romstage.c +++ b/src/mainboard/intel/kunimitsu/romstage.c @@ -24,8 +24,10 @@ MEMORY_INIT_UPD *memory_params) { spd_memory_init_params(memory_params); - mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0); - mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0); + mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0, + &memory_params->DqByteMapCh1); + mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0, + &memory_params->DqsMapCpu2DramCh1); mainboard_fill_rcomp_res_data(&memory_params->RcompResistor); mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget); memory_params->MemorySpdDataLen = SPD_LEN; diff --git a/src/mainboard/intel/kunimitsu/romstage_fsp20.c b/src/mainboard/intel/kunimitsu/romstage_fsp20.c index ee1ddd5..6141f2b 100644 --- a/src/mainboard/intel/kunimitsu/romstage_fsp20.c +++ b/src/mainboard/intel/kunimitsu/romstage_fsp20.c @@ -26,8 +26,10 @@ FSP_M_CONFIG *mem_cfg; mem_cfg = &mupd->FspmConfig; - mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); - mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, + &mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, + &mem_cfg->DqsMapCpu2DramCh1); mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); diff --git a/src/mainboard/intel/kunimitsu/spd/spd.h b/src/mainboard/intel/kunimitsu/spd/spd.h index 22d371f..dd1fa41 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd.h +++ b/src/mainboard/intel/kunimitsu/spd/spd.h @@ -55,8 +55,8 @@ return (gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios))); } void spd_memory_init_params(MEMORY_INIT_UPD *memory_params); -void mainboard_fill_dq_map_data(void *dq_map_ptr); -void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_dq_map_data(u8 *dq_map_ch0, u8 *dq_map_ch1); +void mainboard_fill_dqs_map_data(u8 *dqs_map_ch0, u8 *dqs_map_ch1); void mainboard_fill_rcomp_res_data(void *rcomp_ptr); void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); uintptr_t mainboard_get_spd_data(void); diff --git a/src/mainboard/intel/kunimitsu/spd/spd_util.c b/src/mainboard/intel/kunimitsu/spd/spd_util.c index b173628..aaa617d 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd_util.c +++ b/src/mainboard/intel/kunimitsu/spd/spd_util.c @@ -20,7 +20,7 @@ #include "boardid.h" #include "spd.h" -void mainboard_fill_dq_map_data(void *dq_map_ptr) +void mainboard_fill_dq_map_data(u8 *dq_map_ch0, u8 *dq_map_ch1) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -28,16 +28,18 @@ 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; - memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); + memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0])); + memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1])); } -void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +void mainboard_fill_dqs_map_data(u8 *dqs_map_ch1, u8 *dqs_map_ch1) { /* DQS CPU<>DRAM map */ const u8 dqs_map[2][8] = { { 0, 1, 3, 2, 6, 5, 4, 7 }, { 2, 3, 0, 1, 6, 7, 4, 5 } }; - memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); + memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0])); + memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1])); } void mainboard_fill_rcomp_res_data(void *rcomp_ptr) diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c index 82b85fd..de4d78c 100644 --- a/src/mainboard/intel/saddlebrook/romstage.c +++ b/src/mainboard/intel/saddlebrook/romstage.c @@ -57,8 +57,10 @@ * should be set in the FSP flash image and should not need to be * changed. */ - mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0); - mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0); + mainboard_fill_dq_map_data(&memory_params->DqByteMapCh0, + &memory_params->DqByteMapCh1); + mainboard_fill_dqs_map_data(&memory_params->DqsMapCpu2DramCh0, + &memory_params->DqsMapCpu2DramCh1); mainboard_fill_rcomp_res_data(&memory_params->RcompResistor); mainboard_fill_rcomp_strength_data(&memory_params->RcompTarget); diff --git a/src/mainboard/intel/saddlebrook/spd/spd.h b/src/mainboard/intel/saddlebrook/spd/spd.h index a5f1af3..be468c5 100644 --- a/src/mainboard/intel/saddlebrook/spd/spd.h +++ b/src/mainboard/intel/saddlebrook/spd/spd.h @@ -19,8 +19,8 @@ #define RCOMP_TARGET_PARAMS 0x5 -void mainboard_fill_dq_map_data(void *dq_map_ptr); -void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_dq_map_data(u8 *dq_map_ch0, u8 *dq_map_ch1); +void mainboard_fill_dqs_map_data(u8 *dqs_map_ch0, u8 *dqs_map_ch1); void mainboard_fill_rcomp_res_data(void *rcomp_ptr); void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); diff --git a/src/mainboard/intel/saddlebrook/spd/spd_util.c b/src/mainboard/intel/saddlebrook/spd/spd_util.c index 5055d9a..b9addb6 100644 --- a/src/mainboard/intel/saddlebrook/spd/spd_util.c +++ b/src/mainboard/intel/saddlebrook/spd/spd_util.c @@ -17,7 +17,7 @@ #include <string.h> #include "spd.h" -void mainboard_fill_dq_map_data(void *dq_map_ptr) +void mainboard_fill_dq_map_data(u8 *dq_map_ch0, u8 *dq_map_ch1) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -25,16 +25,18 @@ 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; - memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); + memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0])); + memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1])); } -void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +void mainboard_fill_dqs_map_data(u8 *dqs_map_ch0, u8 *dqs_map_ch1) { /* DQS CPU<>DRAM map */ const u8 dqs_map[2][8] = { { 0, 1, 3, 2, 4, 5, 6, 7 }, { 1, 0, 4, 5, 2, 3, 6, 7 } }; - memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); + memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0])); + memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1])); } void mainboard_fill_rcomp_res_data(void *rcomp_ptr) diff --git a/src/mainboard/purism/librem_skl/romstage.c b/src/mainboard/purism/librem_skl/romstage.c index faf4090..999463c 100644 --- a/src/mainboard/purism/librem_skl/romstage.c +++ b/src/mainboard/purism/librem_skl/romstage.c @@ -21,7 +21,7 @@ #include <spd_bin.h> #include <string.h> -static void mainboard_fill_dq_map_data(void *dq_map_ptr) +static void mainboard_fill_dq_map_data(u8 *dq_map_ch0, u8 *dq_map_ch1) { /* DQ byte map */ const u8 dq_map[2][12] = { @@ -29,16 +29,18 @@ 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; - memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); + memcpy(dq_map_ch0, dq_map[0], sizeof(dq_map[0])); + memcpy(dq_map_ch1, dq_map[1], sizeof(dq_map[1])); } -static void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +static void mainboard_fill_dqs_map_data(u8 *dqs_map_ch0, u8 *dqs_map_ch1) { /* DQS CPU<>DRAM map */ const u8 dqs_map[2][8] = { { 0, 1, 3, 2, 4, 5, 6, 7 }, { 1, 0, 4, 5, 2, 3, 6, 7 } }; - memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); + memcpy(dqs_map_ch0, dqs_map[0], sizeof(dqs_map[0])); + memcpy(dqs_map_ch1, dqs_map[1], sizeof(dqs_map[1])); } static void mainboard_fill_rcomp_res_data(void *rcomp_ptr) @@ -68,8 +70,10 @@ dump_spd_info(&blk); assert(blk.spd_array[0][0] != 0); - mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); - mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0, + &mem_cfg->DqByteMapCh1); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0, + &mem_cfg->DqsMapCpu2DramCh1); mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); -- To view, visit https://review.coreboot.org/c/coreboot/+/33135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6bb2bd5773af24329575926dbc70e0211f29051 Gerrit-Change-Number: 33135 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/{eve,glados}: Copy channel arrays separately
by Jacob Garber (Code Review) 20 Aug '19

20 Aug '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33066 Change subject: mb/google/{eve,glados}: Copy channel arrays separately ...................................................................... mb/google/{eve,glados}: Copy channel arrays separately DqByteMapCh0 and DqByteMapCh1 are declared adjacently in the FSP_M_CONFIG struct, so it is tempting to begin memcpy at the address of the first array and overwrite both of them at once. However, FSP_M_CONFIG is not declared with the packed attribute, so this is not guaranteed to work and is undefined behaviour to boot. It is cleaner and less tricky to copy them independently. The same is true for DqsMapCpu2DramCh0 and DqsMapCpu2DramCh1, so we change those as well. Change-Id: If394f14c4a39d6787ae31868241229646c26be7a Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Found-by: Coverity CID 136538{8,9}, 1365730, 140134{0,2,3} --- M src/mainboard/google/eve/romstage.c M src/mainboard/google/glados/variants/asuka/variant.c M src/mainboard/google/glados/variants/caroline/variant.c M src/mainboard/google/glados/variants/cave/variant.c M src/mainboard/google/glados/variants/chell/variant.c M src/mainboard/google/glados/variants/glados/variant.c M src/mainboard/google/glados/variants/lars/variant.c M src/mainboard/google/glados/variants/sentry/variant.c 8 files changed, 60 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/33066/1 diff --git a/src/mainboard/google/eve/romstage.c b/src/mainboard/google/eve/romstage.c index 975eea5..7114715 100644 --- a/src/mainboard/google/eve/romstage.c +++ b/src/mainboard/google/eve/romstage.c @@ -40,8 +40,10 @@ /* Rcomp target */ const u16 rcomp_target[] = { 100, 40, 40, 23, 40 }; - memcpy(&mem_cfg->DqByteMapCh0, dq_map, sizeof(dq_map)); - memcpy(&mem_cfg->DqsMapCpu2DramCh0, dqs_map, sizeof(dqs_map)); + memcpy(&mem_cfg->DqByteMapCh0, dq_map[0], sizeof(dq_map[0])); + memcpy(&mem_cfg->DqByteMapCh1, dq_map[1], sizeof(dq_map[1])); + memcpy(&mem_cfg->DqsMapCpu2DramCh0, dqs_map[0], sizeof(dqs_map[0])); + memcpy(&mem_cfg->DqsMapCpu2DramCh1, dqs_map[1], sizeof(dqs_map[1])); memcpy(&mem_cfg->RcompResistor, rcomp_resistor, sizeof(rcomp_resistor)); memcpy(&mem_cfg->RcompTarget, rcomp_target, sizeof(rcomp_target)); diff --git a/src/mainboard/google/glados/variants/asuka/variant.c b/src/mainboard/google/glados/variants/asuka/variant.c index 4c77897..fdef81c 100644 --- a/src/mainboard/google/glados/variants/asuka/variant.c +++ b/src/mainboard/google/glados/variants/asuka/variant.c @@ -39,10 +39,14 @@ /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(memory_params->DqByteMapCh0, dq_map, - sizeof(memory_params->DqByteMapCh0) * 2); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, - sizeof(memory_params->DqsMapCpu2DramCh0) * 2); + memcpy(memory_params->DqByteMapCh0, dq_map[0], + sizeof(memory_params->DqByteMapCh0)); + memcpy(memory_params->DqByteMapCh1, dq_map[1], + sizeof(memory_params->DqByteMapCh1)); + memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0], + sizeof(memory_params->DqsMapCpu2DramCh0)); + memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1], + sizeof(memory_params->DqsMapCpu2DramCh1)); memcpy(memory_params->RcompResistor, RcompResistor, sizeof(memory_params->RcompResistor)); memcpy(memory_params->RcompTarget, RcompTarget, diff --git a/src/mainboard/google/glados/variants/caroline/variant.c b/src/mainboard/google/glados/variants/caroline/variant.c index d61a538..ab6bd2c 100644 --- a/src/mainboard/google/glados/variants/caroline/variant.c +++ b/src/mainboard/google/glados/variants/caroline/variant.c @@ -41,10 +41,14 @@ /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(memory_params->DqByteMapCh0, dq_map, - sizeof(memory_params->DqByteMapCh0) * 2); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, - sizeof(memory_params->DqsMapCpu2DramCh0) * 2); + memcpy(memory_params->DqByteMapCh0, dq_map[0], + sizeof(memory_params->DqByteMapCh0)); + memcpy(memory_params->DqByteMapCh1, dq_map[1], + sizeof(memory_params->DqByteMapCh1)); + memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0], + sizeof(memory_params->DqsMapCpu2DramCh0)); + memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1], + sizeof(memory_params->DqsMapCpu2DramCh1)); memcpy(memory_params->RcompResistor, RcompResistor, sizeof(memory_params->RcompResistor)); memcpy(memory_params->RcompTarget, RcompTarget, diff --git a/src/mainboard/google/glados/variants/cave/variant.c b/src/mainboard/google/glados/variants/cave/variant.c index fc27fb4..d63a298 100644 --- a/src/mainboard/google/glados/variants/cave/variant.c +++ b/src/mainboard/google/glados/variants/cave/variant.c @@ -41,10 +41,14 @@ /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(memory_params->DqByteMapCh0, dq_map, - sizeof(memory_params->DqByteMapCh0) * 2); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, - sizeof(memory_params->DqsMapCpu2DramCh0) * 2); + memcpy(memory_params->DqByteMapCh0, dq_map[0], + sizeof(memory_params->DqByteMapCh0)); + memcpy(memory_params->DqByteMapCh1, dq_map[1], + sizeof(memory_params->DqByteMapCh1)); + memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0], + sizeof(memory_params->DqsMapCpu2DramCh0)); + memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1], + sizeof(memory_params->DqsMapCpu2DramCh1)); memcpy(memory_params->RcompResistor, RcompResistor, sizeof(memory_params->RcompResistor)); memcpy(memory_params->RcompTarget, RcompTarget, diff --git a/src/mainboard/google/glados/variants/chell/variant.c b/src/mainboard/google/glados/variants/chell/variant.c index 2d1b363..3e8503f 100644 --- a/src/mainboard/google/glados/variants/chell/variant.c +++ b/src/mainboard/google/glados/variants/chell/variant.c @@ -41,10 +41,14 @@ /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(memory_params->DqByteMapCh0, dq_map, - sizeof(memory_params->DqByteMapCh0) * 2); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, - sizeof(memory_params->DqsMapCpu2DramCh0) * 2); + memcpy(memory_params->DqByteMapCh0, dq_map[0], + sizeof(memory_params->DqByteMapCh0)); + memcpy(memory_params->DqByteMapCh1, dq_map[1], + sizeof(memory_params->DqByteMapCh1)); + memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0], + sizeof(memory_params->DqsMapCpu2DramCh0)); + memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1], + sizeof(memory_params->DqsMapCpu2DramCh1)); memcpy(memory_params->RcompResistor, RcompResistor, sizeof(memory_params->RcompResistor)); memcpy(memory_params->RcompTarget, RcompTarget, diff --git a/src/mainboard/google/glados/variants/glados/variant.c b/src/mainboard/google/glados/variants/glados/variant.c index fc27fb4..d63a298 100644 --- a/src/mainboard/google/glados/variants/glados/variant.c +++ b/src/mainboard/google/glados/variants/glados/variant.c @@ -41,10 +41,14 @@ /* Rcomp target */ const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 }; - memcpy(memory_params->DqByteMapCh0, dq_map, - sizeof(memory_params->DqByteMapCh0) * 2); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, - sizeof(memory_params->DqsMapCpu2DramCh0) * 2); + memcpy(memory_params->DqByteMapCh0, dq_map[0], + sizeof(memory_params->DqByteMapCh0)); + memcpy(memory_params->DqByteMapCh1, dq_map[1], + sizeof(memory_params->DqByteMapCh1)); + memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0], + sizeof(memory_params->DqsMapCpu2DramCh0)); + memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1], + sizeof(memory_params->DqsMapCpu2DramCh1)); memcpy(memory_params->RcompResistor, RcompResistor, sizeof(memory_params->RcompResistor)); memcpy(memory_params->RcompTarget, RcompTarget, diff --git a/src/mainboard/google/glados/variants/lars/variant.c b/src/mainboard/google/glados/variants/lars/variant.c index cff0096..37860c3 100644 --- a/src/mainboard/google/glados/variants/lars/variant.c +++ b/src/mainboard/google/glados/variants/lars/variant.c @@ -58,10 +58,14 @@ if (spd_index == K4E6E304EB_MEM_ID) targeted_rcomp = StrengthendRcompTarget; - memcpy(params->DqByteMapCh0, dq_map, - sizeof(params->DqByteMapCh0) * 2); - memcpy(params->DqsMapCpu2DramCh0, dqs_map, - sizeof(params->DqsMapCpu2DramCh0) * 2); + memcpy(params->DqByteMapCh0, dq_map[0], + sizeof(params->DqByteMapCh0)); + memcpy(params->DqByteMapCh1, dq_map[1], + sizeof(params->DqByteMapCh1)); + memcpy(params->DqsMapCpu2DramCh0, dqs_map[0], + sizeof(params->DqsMapCpu2DramCh0)); + memcpy(params->DqsMapCpu2DramCh1, dqs_map[1], + sizeof(params->DqsMapCpu2DramCh1)); memcpy(params->RcompResistor, RcompResistor, sizeof(params->RcompResistor)); memcpy(params->RcompTarget, targeted_rcomp, diff --git a/src/mainboard/google/glados/variants/sentry/variant.c b/src/mainboard/google/glados/variants/sentry/variant.c index 4c7fa23..101be2a 100644 --- a/src/mainboard/google/glados/variants/sentry/variant.c +++ b/src/mainboard/google/glados/variants/sentry/variant.c @@ -51,10 +51,14 @@ if (spd_index == K4E6E304EE_MEM_ID) targeted_rcomp = StrengthendRcompTarget; - memcpy(memory_params->DqByteMapCh0, dq_map, - sizeof(memory_params->DqByteMapCh0) * 2); - memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map, - sizeof(memory_params->DqsMapCpu2DramCh0) * 2); + memcpy(memory_params->DqByteMapCh0, dq_map[0], + sizeof(memory_params->DqByteMapCh0)); + memcpy(memory_params->DqByteMapCh1, dq_map[1], + sizeof(memory_params->DqByteMapCh1)); + memcpy(memory_params->DqsMapCpu2DramCh0, dqs_map[0], + sizeof(memory_params->DqsMapCpu2DramCh0)); + memcpy(memory_params->DqsMapCpu2DramCh1, dqs_map[1], + sizeof(memory_params->DqsMapCpu2DramCh1)); memcpy(memory_params->RcompResistor, RcompResistor, sizeof(memory_params->RcompResistor)); memcpy(memory_params->RcompTarget, targeted_rcomp, -- To view, visit https://review.coreboot.org/c/coreboot/+/33066 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If394f14c4a39d6787ae31868241229646c26be7a Gerrit-Change-Number: 33066 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: mb/asus/kfsn4-dre: Return early if CK804 not found
by Jacob Garber (Code Review) 20 Aug '19

20 Aug '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34573 ) Change subject: mb/asus/kfsn4-dre: Return early if CK804 not found ...................................................................... mb/asus/kfsn4-dre: Return early if CK804 not found It probably doesn't make sense to continue if the CK804 isn't found, and doing so would perform uninitialized reads of the busn and io_base arrays anyway, so let's return early. Change-Id: I13c663314496caf51a57da7f27f9ea24e3d7fcbd Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Found-by: Coverity CID 1370586 --- M src/mainboard/asus/kfsn4-dre/romstage.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/34573/1 diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 7b20243..22eb115 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -132,8 +132,10 @@ } } - if (ck804_num < 1) + if (ck804_num < 1) { printk(BIOS_WARNING, "CK804 not found at device base unit id %02x!\n", bus_unit_id); + return; + } ck804_early_set_port(ck804_num, busn, io_base); -- To view, visit https://review.coreboot.org/c/coreboot/+/34573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I13c663314496caf51a57da7f27f9ea24e3d7fcbd Gerrit-Change-Number: 34573 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

3 4

Change in coreboot[master]: rmodule: Add R_386_16 to valid reloc
by Marshall Dawson (Code Review) 20 Aug '19

20 Aug '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34912 ) Change subject: rmodule: Add R_386_16 to valid reloc ...................................................................... rmodule: Add R_386_16 to valid reloc Prepare for a relocatable module that will rely on the x86 sequenced files of prologue.inc, entry16.inc, reset.inc, entry32.inc. This generates type 20 R_386_16. Change-Id: I56df52cb5626b99b39fa170d65920e71cafff569 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M util/cbfstool/rmodule.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/34912/1 diff --git a/util/cbfstool/rmodule.c b/util/cbfstool/rmodule.c index 80e8911..c79029d 100644 --- a/util/cbfstool/rmodule.c +++ b/util/cbfstool/rmodule.c @@ -31,7 +31,7 @@ type = ELF64_R_TYPE(rel->r_info); /* Only these 2 relocations are expected to be found. */ - return (type == R_386_32 || type == R_386_PC32); + return (type == R_386_32 || type == R_386_PC32 || type == R_386_16); } static int should_emit_386(Elf64_Rela *rel) -- To view, visit https://review.coreboot.org/c/coreboot/+/34912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I56df52cb5626b99b39fa170d65920e71cafff569 Gerrit-Change-Number: 34912 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

3 11

Change in coreboot[master]: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
by Patrick Rudolph (Code Review) 20 Aug '19

20 Aug '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32734 ) Change subject: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF ...................................................................... Patch Set 74: (1 comment) https://review.coreboot.org/c/coreboot/+/32734/72/src/mainboard/supermicro/… File src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb: https://review.coreboot.org/c/coreboot/+/32734/72/src/mainboard/supermicro/… PS72, Line 234: ca2.0 > How did you determine this value? it's the default IPMI I/O KCS port. Have a look at dmidecode or ACPI tables to find this value. -- To view, visit https://review.coreboot.org/c/coreboot/+/32734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 Gerrit-Change-Number: 32734 Gerrit-PatchSet: 74 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Keno Fischer <keno(a)alumni.harvard.edu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Name of user not set #1002358 Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: T. Hudson <trammell.hudson(a)gmail.com> Gerrit-Reviewer: Trammell Hudson <hudson(a)trmm.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Michael Niewöhner Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 20 Aug 2019 14:05:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
by Christoph Pomaska (Code Review) 20 Aug '19

20 Aug '19

Christoph Pomaska has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32734 ) Change subject: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF ...................................................................... Patch Set 74: (1 comment) https://review.coreboot.org/c/coreboot/+/32734/72/src/mainboard/supermicro/… File src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb: https://review.coreboot.org/c/coreboot/+/32734/72/src/mainboard/supermicro/… PS72, Line 234: ca2.0 How did you determine this value? -- To view, visit https://review.coreboot.org/c/coreboot/+/32734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 Gerrit-Change-Number: 32734 Gerrit-PatchSet: 74 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Keno Fischer <keno(a)alumni.harvard.edu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Name of user not set #1002358 Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: T. Hudson <trammell.hudson(a)gmail.com> Gerrit-Reviewer: Trammell Hudson <hudson(a)trmm.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Michael Niewöhner Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 20 Aug 2019 13:57:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: src/ec: Drop __PRE_RAM__ and __SMM__ guards
by Kyösti Mälkki (Code Review) 20 Aug '19

20 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34940 ) Change subject: src/ec: Drop __PRE_RAM__ and __SMM__ guards ...................................................................... src/ec: Drop __PRE_RAM__ and __SMM__ guards For files built in ramstage and smm -classes, testing for !__PRE_RAM__ is redundant. All chip_operations are exluded with use of DEVTREE_EARLY in static devicetree, so garbage collection will take care of the !__SMM__ cases. Change-Id: Id7219848d6f5c41c4a9724a72204fa5ef9458e43 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/ec/acpi/ec.c M src/ec/compal/ene932/ec.c M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec_i2c.c M src/ec/google/chromeec/ec_spi.c M src/ec/quanta/ene_kb3940q/ec.c M src/ec/quanta/it8518/ec.c 7 files changed, 3 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/34940/1 diff --git a/src/ec/acpi/ec.c b/src/ec/acpi/ec.c index 61cad65..dd91fab 100644 --- a/src/ec/acpi/ec.c +++ b/src/ec/acpi/ec.c @@ -20,17 +20,8 @@ #include <delay.h> #include "ec.h" -#ifdef __PRE_RAM__ - -static const int ec_cmd_reg = EC_SC; -static const int ec_data_reg = EC_DATA; - -#else - -static int ec_cmd_reg = EC_SC; -static int ec_data_reg = EC_DATA; - -#endif +static DEVTREE_CONST int ec_cmd_reg = EC_SC; +static DEVTREE_CONST int ec_data_reg = EC_DATA; int send_ec_command(u8 command) { @@ -162,18 +153,14 @@ ec_write(addr, ec_read(addr) & ~(1 << bit)); } -#ifndef __PRE_RAM__ - +#if !DEVTREE_EARLY void ec_set_ports(u16 cmd_reg, u16 data_reg) { ec_cmd_reg = cmd_reg; ec_data_reg = data_reg; } - #endif -#if !defined(__SMM__) && !defined(__PRE_RAM__) struct chip_operations ec_acpi_ops = { CHIP_NAME("ACPI Embedded Controller") }; -#endif diff --git a/src/ec/compal/ene932/ec.c b/src/ec/compal/ene932/ec.c index cfabd8d..5bade10 100644 --- a/src/ec/compal/ene932/ec.c +++ b/src/ec/compal/ene932/ec.c @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -#ifndef __PRE_RAM__ - #include <console/console.h> #include <device/device.h> #include <device/pnp.h> @@ -125,7 +123,6 @@ } */ -#ifndef __SMM__ static void ene932_init(struct device *dev) { if (!dev->enabled) @@ -155,5 +152,3 @@ CHIP_NAME("COMPAL ENE932 EC") .enable_dev = enable_dev }; -#endif /* ! __SMM__ */ -#endif /* ! __PRE_RAM__ */ diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 5a2630e..ed53c61 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -719,8 +719,6 @@ return cec_cmd.cmd_code; } -#ifndef __PRE_RAM__ - int google_chromeec_i2c_xfer(uint8_t chip, uint8_t addr, int alen, uint8_t *buffer, int len, int is_read) { @@ -1109,8 +1107,6 @@ return (ec_image_type == EC_IMAGE_RO); } -#endif /* ! __PRE_RAM__ */ - /** * Check if EC/TCPM is in an alternate mode or not. * diff --git a/src/ec/google/chromeec/ec_i2c.c b/src/ec/google/chromeec/ec_i2c.c index c3e1968..dc012fc 100644 --- a/src/ec/google/chromeec/ec_i2c.c +++ b/src/ec/google/chromeec/ec_i2c.c @@ -252,10 +252,8 @@ #endif /* CONFIG_EC_GOOGLE_CHROMEEC_I2C_PROTO3 */ -#ifndef __PRE_RAM__ u8 google_chromeec_get_event(void) { printk(BIOS_ERR, "%s: Not supported.\n", __func__); return 0; } -#endif diff --git a/src/ec/google/chromeec/ec_spi.c b/src/ec/google/chromeec/ec_spi.c index 3611814..c47d419 100644 --- a/src/ec/google/chromeec/ec_spi.c +++ b/src/ec/google/chromeec/ec_spi.c @@ -115,10 +115,8 @@ return crosec_command_proto(cec_command, crosec_spi_io, &slave); } -#ifndef __PRE_RAM__ u8 google_chromeec_get_event(void) { printk(BIOS_ERR, "%s: Not supported.\n", __func__); return 0; } -#endif diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c index 1f8e36c..4fc38da 100644 --- a/src/ec/quanta/ene_kb3940q/ec.c +++ b/src/ec/quanta/ene_kb3940q/ec.c @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -#ifndef __PRE_RAM__ - #include <arch/io.h> #include <console/console.h> #include <device/device.h> @@ -125,7 +123,6 @@ return; } -#ifndef __SMM__ static void ene_kb3940q_log_events(void) { #if CONFIG(ELOG) @@ -165,5 +162,3 @@ CHIP_NAME("QUANTA EnE KB3940Q EC") .enable_dev = enable_dev }; -#endif /* ! __SMM__ */ -#endif /* ! __PRE_RAM__ */ diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c index 5b9ba9f..4853eb3 100644 --- a/src/ec/quanta/it8518/ec.c +++ b/src/ec/quanta/it8518/ec.c @@ -124,7 +124,6 @@ ec_write_ib(data); } -#ifndef __PRE_RAM__ u8 ec_it8518_get_event(void) { @@ -149,7 +148,6 @@ ec_write(EC_WAKE_SRC_ENABLE, reg8 | EC_LID_WAKE_ENABLE); } -#ifndef __SMM__ static void it8518_init(struct device *dev) { if (!dev->enabled) @@ -178,5 +176,3 @@ CHIP_NAME("QUANTA IT8518 EC") .enable_dev = enable_dev }; -#endif /* ! __SMM__ */ -#endif /* ! __PRE_RAM__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7219848d6f5c41c4a9724a72204fa5ef9458e43 Gerrit-Change-Number: 34940 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: device/pnp.h: Move __SIMPLE_DEVICE__ guards
by Kyösti Mälkki (Code Review) 20 Aug '19

20 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34943 ) Change subject: device/pnp.h: Move __SIMPLE_DEVICE__ guards ...................................................................... device/pnp.h: Move __SIMPLE_DEVICE__ guards Some files under src/ec are built for both ramstage and SMM. This change provides declarations of the required struct to have __SMM__ guards removed from those files. Change-Id: Ic0c01a11f29381153f19378d5bc4559db8126e00 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/include/device/pnp.h 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/34943/1 diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index bc6391f..ee92a32 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -18,6 +18,8 @@ void pnp_set_irq(struct device *dev, u8 index, u8 irq); void pnp_set_drq(struct device *dev, u8 index, u8 drq); +#endif /* __SIMPLE_DEVICE */ + /* PNP device operations */ void pnp_read_resources(struct device *dev); void pnp_set_resources(struct device *dev); @@ -108,5 +110,4 @@ outb(value, port + 1); } -#endif /* ! __SIMPLE_DEVICE__ */ #endif /* DEVICE_PNP_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/34943 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0c01a11f29381153f19378d5bc4559db8126e00 Gerrit-Change-Number: 34943 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: src/soc/intel/cannonlake: [TEST_ONLY] Disable HECI device
by Aamir Bohra (Code Review) 20 Aug '19

20 Aug '19

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32801 Change subject: src/soc/intel/cannonlake: [TEST_ONLY] Disable HECI device ...................................................................... src/soc/intel/cannonlake: [TEST_ONLY] Disable HECI device Change-Id: Ifaa09ef0cee77a15c33dc415f465ac735c0dce2b Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/32801/1 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index cc01d10..a2c29b9 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -338,6 +338,10 @@ params->FastPkgCRampDisableSa = config->FastPkgCRampDisableSa; params->FastPkgCRampDisableFivr = config->FastPkgCRampDisableFivr; +#if CONFIG(SOC_INTEL_COMETLAKE) + params->Heci1Disabled = 1; +#endif + /* Power Optimizer */ params->PchPwrOptEnable = config->dmipwroptimize; params->SataPwrOptEnable = config->satapwroptimize; -- To view, visit https://review.coreboot.org/c/coreboot/+/32801 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifaa09ef0cee77a15c33dc415f465ac735c0dce2b Gerrit-Change-Number: 32801 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: AGESA,binaryPI: Replace use of __PRE_RAM__
by Kyösti Mälkki (Code Review) 20 Aug '19

20 Aug '19

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34997 ) Change subject: AGESA,binaryPI: Replace use of __PRE_RAM__ ...................................................................... AGESA,binaryPI: Replace use of __PRE_RAM__ Change-Id: Id878fd33ec3d2de640d9a488058a805be3ccd223 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34997 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/drivers/amd/agesa/def_callouts.c M src/mainboard/amd/bettong/BiosCallOuts.c M src/mainboard/bap/ode_e20XX/BiosCallOuts.c M src/mainboard/bap/ode_e21XX/BiosCallOuts.c M src/mainboard/pcengines/apu1/BiosCallOuts.c M src/mainboard/pcengines/apu2/BiosCallOuts.c M src/northbridge/amd/agesa/family12/northbridge.c M src/northbridge/amd/agesa/family14/northbridge.c M src/northbridge/amd/pi/agesawrapper.c M src/southbridge/amd/agesa/hudson/hudson.h M src/southbridge/amd/agesa/hudson/imc.c M src/southbridge/amd/cimx/sb800/fan.h M src/southbridge/amd/cimx/sb900/cfg.c M src/southbridge/amd/common/amd_pci_util.c M src/southbridge/amd/common/amd_pci_util.h M src/southbridge/amd/pi/hudson/hudson.h M src/southbridge/amd/pi/hudson/imc.c M src/vendorcode/amd/agesa/common/agesa-entry-cfg.h 18 files changed, 40 insertions(+), 76 deletions(-) Approvals: build bot (Jenkins): Verified Marshall Dawson: Looks good to me, approved diff --git a/src/drivers/amd/agesa/def_callouts.c b/src/drivers/amd/agesa/def_callouts.c index fa41500..d247e51 100644 --- a/src/drivers/amd/agesa/def_callouts.c +++ b/src/drivers/amd/agesa/def_callouts.c @@ -160,18 +160,19 @@ AGESA_STATUS agesa_ReadSpd (UINT32 Func, UINTN Data, VOID *ConfigPtr) { - AGESA_STATUS Status = AGESA_UNSUPPORTED; -#ifdef __PRE_RAM__ - Status = AmdMemoryReadSPD (Func, Data, ConfigPtr); -#endif - return Status; + if (!ENV_ROMSTAGE) + return AGESA_UNSUPPORTED; + + return AmdMemoryReadSPD (Func, Data, ConfigPtr); } AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr) { - AGESA_STATUS Status = AGESA_UNSUPPORTED; -#ifdef __PRE_RAM__ AGESA_READ_SPD_PARAMS *info = ConfigPtr; + + if (!ENV_ROMSTAGE) + return AGESA_UNSUPPORTED; + if (info->MemChannelId > 0) return AGESA_UNSUPPORTED; if (info->SocketId != 0) @@ -183,9 +184,7 @@ if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, 0) < 0) die("No SPD data\n"); - Status = AGESA_SUCCESS; -#endif - return Status; + return AGESA_SUCCESS; } #if HAS_AGESA_FCH_OEM_CALLOUT diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c index d318d0c..e983690 100644 --- a/src/mainboard/amd/bettong/BiosCallOuts.c +++ b/src/mainboard/amd/bettong/BiosCallOuts.c @@ -117,9 +117,11 @@ static AGESA_STATUS board_ReadSpd(UINT32 Func, UINTN Data, VOID *ConfigPtr) { -#ifdef __PRE_RAM__ - int spdAddress; AGESA_READ_SPD_PARAMS *info = ConfigPtr; + int spdAddress; + + if (!ENV_ROMSTAGE) + return AGESA_UNSUPPORTED; DEVTREE_CONST struct device *dev = pcidev_on_root(0x18, 2); @@ -154,6 +156,6 @@ int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 128); if (err) return AGESA_ERROR; -#endif + return AGESA_SUCCESS; } diff --git a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c index 4f5ab88..abe300e 100644 --- a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c @@ -191,11 +191,12 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr) { - AGESA_STATUS Status = AGESA_UNSUPPORTED; -#ifdef __PRE_RAM__ AGESA_READ_SPD_PARAMS *info = ConfigPtr; u8 index; + if (!ENV_ROMSTAGE) + return AGESA_UNSUPPORTED; + if (CONFIG(BAP_E20_DDR3_1066)) index = 1; else /* CONFIG_BAP_E20_DDR3_800 */ @@ -212,7 +213,5 @@ if (read_ddr3_spd_from_cbfs((u8 *)info->Buffer, index) < 0) die("No SPD data\n"); - Status = AGESA_SUCCESS; -#endif - return Status; + return AGESA_SUCCESS; } diff --git a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c index 6458b97..6ff38cb 100644 --- a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c @@ -299,11 +299,12 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr) { - AGESA_STATUS Status = AGESA_UNSUPPORTED; -#ifdef __PRE_RAM__ AGESA_READ_SPD_PARAMS *info = ConfigPtr; u8 index; + if (!ENV_ROMSTAGE) + return AGESA_UNSUPPORTED; + if (CONFIG(BAP_E21_DDR3_1066)) index = 1; else if (CONFIG(BAP_E21_DDR3_1333)) @@ -322,7 +323,5 @@ if (read_ddr3_spd_from_cbfs((u8 *)info->Buffer, index) < 0) die("No SPD data\n"); - Status = AGESA_SUCCESS; -#endif - return Status; + return AGESA_SUCCESS; } diff --git a/src/mainboard/pcengines/apu1/BiosCallOuts.c b/src/mainboard/pcengines/apu1/BiosCallOuts.c index df5f037..caaa1f4 100644 --- a/src/mainboard/pcengines/apu1/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu1/BiosCallOuts.c @@ -50,9 +50,11 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr) { - AGESA_STATUS Status = AGESA_UNSUPPORTED; -#ifdef __PRE_RAM__ AGESA_READ_SPD_PARAMS *info = ConfigPtr; + + if (!ENV_ROMSTAGE) + return AGESA_UNSUPPORTED; + u8 index = get_spd_offset(); if (info->MemChannelId > 0) @@ -66,7 +68,5 @@ if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, index) < 0) die("No SPD data\n"); - Status = AGESA_SUCCESS; -#endif - return Status; + return AGESA_SUCCESS; } diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index edacb22..dff346e 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -130,9 +130,11 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr) { - AGESA_STATUS Status = AGESA_UNSUPPORTED; -#ifdef __PRE_RAM__ AGESA_READ_SPD_PARAMS *info = ConfigPtr; + + if (!ENV_ROMSTAGE) + return AGESA_UNSUPPORTED; + u8 index = get_spd_offset(); if (info->MemChannelId > 0) @@ -146,7 +148,5 @@ if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, index) < 0) die("No SPD data\n"); - Status = AGESA_SUCCESS; -#endif - return Status; + return AGESA_SUCCESS; } diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 290ab16..ab17d89 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -54,11 +54,7 @@ { struct device *dev; struct dram_base_mask_t d; -#if defined(__PRE_RAM__) - dev = PCI_DEV(0, DEV_CDB, 1); -#else dev = __f1_dev[0]; -#endif // defined(__PRE_RAM__) u32 temp; temp = pci_read_config32(dev, 0x44); //[39:24] at [31:16] diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index a52f7ec..83329a2 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -52,11 +52,7 @@ { struct device *dev; struct dram_base_mask_t d; -#if defined(__PRE_RAM__) - dev = PCI_DEV(0, DEV_CDB, 1); -#else dev = __f1_dev[0]; -#endif // defined(__PRE_RAM__) u32 temp; temp = pci_read_config32(dev, 0x44); //[39:24] at [31:16] diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index 1563216..e3bfd90 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -248,13 +248,15 @@ return status; } -#ifndef __PRE_RAM__ AGESA_STATUS agesawrapper_amdinitlate(void) { AGESA_STATUS Status; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_LATE_PARAMS *AmdLateParams; + if (!ENV_RAMSTAGE) + return AGESA_UNSUPPORTED; + LibAmdMemFill (&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), @@ -289,7 +291,6 @@ /* No AmdReleaseStruct(&AmdParamStruct), we need AmdLateParams later. */ return Status; } -#endif /* #ifndef __PRE_RAM__ */ const void *agesawrapper_locate_module (const CHAR8 name[8]) { diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index 5d9d849..21a2129 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -61,14 +61,11 @@ return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3); } -#ifndef __SMM__ - void pm_write8(u8 reg, u8 value); u8 pm_read8(u8 reg); void pm_write16(u8 reg, u16 value); u16 pm_read16(u16 reg); -#ifdef __SIMPLE_DEVICE__ void hudson_lpc_port80(void); void hudson_pci_port80(void); void hudson_clk_output_48Mhz(void); @@ -76,10 +73,6 @@ int s3_save_nvram_early(u32 dword, int size, int nvram_pos); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); -#else void hudson_enable(struct device *dev); -#endif /* __PRE_RAM__ */ -#endif /* __SMM__ */ - #endif /* HUDSON_H */ diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c index 9ba0731..1d63c1e 100644 --- a/src/southbridge/amd/agesa/hudson/imc.c +++ b/src/southbridge/amd/agesa/hudson/imc.c @@ -54,7 +54,6 @@ #endif } -#ifndef __PRE_RAM__ void enable_imc_thermal_zone(void) { AMD_CONFIG_PARAMS StdHeader; @@ -83,4 +82,3 @@ WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader); // function number WaitForEcLDN9MailboxCmdAck(&StdHeader); } -#endif diff --git a/src/southbridge/amd/cimx/sb800/fan.h b/src/southbridge/amd/cimx/sb800/fan.h index f31e486..3734da1 100644 --- a/src/southbridge/amd/cimx/sb800/fan.h +++ b/src/southbridge/amd/cimx/sb800/fan.h @@ -16,10 +16,10 @@ #ifndef _SB800_FAN_H_ #define _SB800_FAN_H_ -#ifndef __PRE_RAM__ +#include <device/device.h> + void init_sb800_IMC_fans(struct device *dev); void init_sb800_MANUAL_fans(struct device *dev); -#endif /* Fan Register Definitions */ #define FAN_0_OFFSET 0x00 diff --git a/src/southbridge/amd/cimx/sb900/cfg.c b/src/southbridge/amd/cimx/sb900/cfg.c index 353d577..2e4173f 100644 --- a/src/southbridge/amd/cimx/sb900/cfg.c +++ b/src/southbridge/amd/cimx/sb900/cfg.c @@ -243,15 +243,13 @@ sb_config->PciClks = SB_PCI_CLOCK_RESERVED; sb_config->hwm.hwmEnable = 0x0; -#ifndef __PRE_RAM__ /* ramstage cimx config here */ - if (!sb_config->StdHeader.CALLBACK.CalloutPtr) { + if (ENV_RAMSTAGE && !sb_config->StdHeader.CALLBACK.CalloutPtr) { sb_config->StdHeader.CALLBACK.CalloutPtr = sb900_callout_entry; } //sb_config-> -#endif //!__PRE_RAM__ - printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - End.\n"); + printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - End.\n"); } void SbPowerOnInit_Config(AMDSBCFG *sb_config) diff --git a/src/southbridge/amd/common/amd_pci_util.c b/src/southbridge/amd/common/amd_pci_util.c index f10a459..b6d6308 100644 --- a/src/southbridge/amd/common/amd_pci_util.c +++ b/src/southbridge/amd/common/amd_pci_util.c @@ -22,8 +22,6 @@ #include "amd_pci_int_defs.h" #include "amd_pci_int_types.h" -#ifndef __PRE_RAM__ - const struct pirq_struct * pirq_data_ptr = NULL; u32 pirq_data_size = 0; const u8 *intr_data_ptr = NULL; @@ -195,4 +193,3 @@ } /* for (dev = all_devices) */ printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); } -#endif /* __PRE_RAM__ */ diff --git a/src/southbridge/amd/common/amd_pci_util.h b/src/southbridge/amd/common/amd_pci_util.h index 9a4695e..0a3ce23 100644 --- a/src/southbridge/amd/common/amd_pci_util.h +++ b/src/southbridge/amd/common/amd_pci_util.h @@ -23,8 +23,6 @@ #define PCI_INTR_INDEX 0xc00 #define PCI_INTR_DATA 0xc01 -#ifndef __PRE_RAM__ - struct pirq_struct { u8 devfn; u8 PIN[4]; /* PINA/B/C/D are index 0/1/2/3 */ @@ -39,6 +37,5 @@ void write_pci_int_idx(u8 index, int mode, u8 data); void write_pci_cfg_irqs(void); void write_pci_int_table (void); -#endif /* __PRE_RAM */ #endif /* AMD_PCI_UTIL_H */ diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 99e3721..9511a6a 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -169,14 +169,11 @@ return (CONFIG_HUDSON_SATA_MODE == 0) || (CONFIG_HUDSON_SATA_MODE == 3); } -#ifndef __SMM__ - void pm_write8(u8 reg, u8 value); u8 pm_read8(u8 reg); void pm_write16(u8 reg, u16 value); u16 pm_read16(u16 reg); -#ifdef __PRE_RAM__ void hudson_lpc_port80(void); void hudson_lpc_decode(void); void hudson_pci_port80(void); @@ -190,15 +187,9 @@ void hudson_tpm_decode_spi(void); int s3_save_nvram_early(u32 dword, int size, int nvram_pos); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); -#if CONFIG(HUDSON_UART) void configure_hudson_uart(void); -#endif -#else void hudson_enable(struct device *dev); void s3_resume_init_data(void *FchParams); -#endif /* __PRE_RAM__ */ -#endif /* __SMM__ */ - #endif /* HUDSON_H */ diff --git a/src/southbridge/amd/pi/hudson/imc.c b/src/southbridge/amd/pi/hudson/imc.c index 9ea8172..6a01a76 100644 --- a/src/southbridge/amd/pi/hudson/imc.c +++ b/src/southbridge/amd/pi/hudson/imc.c @@ -51,7 +51,6 @@ pci_write_config8(PCI_DEV(0, 0x18, 0x3), 0x1E4, reg8); } -#ifndef __PRE_RAM__ void enable_imc_thermal_zone(void) { AMD_CONFIG_PARAMS StdHeader; @@ -80,4 +79,3 @@ WriteECmsg(MSG_SYS_TO_IMC, AccessWidth8, &FunNum, &StdHeader); WaitForEcLDN9MailboxCmdAck(&StdHeader); } -#endif diff --git a/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h index f787014..b1a346a 100644 --- a/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h +++ b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h @@ -2,7 +2,7 @@ #define AGESA_ENTRY_CFG_H -#if defined(__PRE_RAM__) +#if ENV_ROMSTAGE #define AGESA_ENTRY_INIT_RESET TRUE #define AGESA_ENTRY_INIT_EARLY TRUE -- To view, visit https://review.coreboot.org/c/coreboot/+/34997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id878fd33ec3d2de640d9a488058a805be3ccd223 Gerrit-Change-Number: 34997 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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coreboot-gerrit August 2019