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Change in coreboot[master]: AGESA,binaryPI: Replace use of __PRE_RAM__
by Marshall Dawson (Code Review) 20 Aug '19

20 Aug '19

1 0

Change in coreboot[master]: AGESA,binaryPI: Replace use of __PRE_RAM__
by Kyösti Mälkki (Code Review) 20 Aug '19

20 Aug '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34997 ) Change subject: AGESA,binaryPI: Replace use of __PRE_RAM__ ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/c/coreboot/+/34997/1/src/southbridge/amd/cimx/s… File src/southbridge/amd/cimx/sb800/fan.h: https://review.coreboot.org/c/coreboot/+/34997/1/src/southbridge/amd/cimx/s… PS1, Line 19: #include <device/device.h> > Was this intentional? Two lines below want struct device, although anonymous. -- To view, visit https://review.coreboot.org/c/coreboot/+/34997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id878fd33ec3d2de640d9a488058a805be3ccd223 Gerrit-Change-Number: 34997 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Tue, 20 Aug 2019 02:08:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: AGESA,binaryPI: Replace use of __PRE_RAM__
by Marshall Dawson (Code Review) 20 Aug '19

20 Aug '19

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34997 ) Change subject: AGESA,binaryPI: Replace use of __PRE_RAM__ ...................................................................... Patch Set 1: (5 comments) https://review.coreboot.org/c/coreboot/+/34997/1/src/drivers/amd/agesa/def_… File src/drivers/amd/agesa/def_callouts.c: https://review.coreboot.org/c/coreboot/+/34997/1/src/drivers/amd/agesa/def_… PS1, Line 166: return AmdMemoryReadSPD (Func, Data, ConfigPtr); > space prohibited between function name and open parenthesis '(' Ack https://review.coreboot.org/c/coreboot/+/34997/1/src/southbridge/amd/agesa/… File src/southbridge/amd/agesa/hudson/hudson.h: https://review.coreboot.org/c/coreboot/+/34997/1/src/southbridge/amd/agesa/… PS1, Line 63: ugh, this file! https://review.coreboot.org/c/coreboot/+/34997/1/src/southbridge/amd/cimx/s… File src/southbridge/amd/cimx/sb800/fan.h: https://review.coreboot.org/c/coreboot/+/34997/1/src/southbridge/amd/cimx/s… PS1, Line 19: #include <device/device.h> Was this intentional? https://review.coreboot.org/c/coreboot/+/34997/1/src/southbridge/amd/cimx/s… File src/southbridge/amd/cimx/sb900/cfg.c: https://review.coreboot.org/c/coreboot/+/34997/1/src/southbridge/amd/cimx/s… PS1, Line 247: if (ENV_RAMSTAGE && !sb_config->StdHeader.CALLBACK.CalloutPtr) { > braces {} are not necessary for single statement blocks Ack https://review.coreboot.org/c/coreboot/+/34997/1/src/southbridge/amd/cimx/s… PS1, Line 252: printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - End.\n"); > Prefer using '"%s... […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/34997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id878fd33ec3d2de640d9a488058a805be3ccd223 Gerrit-Change-Number: 34997 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Tue, 20 Aug 2019 02:05:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/kohaku: Use level trigger for touchscreen interrupt
by shkim (Code Review) 20 Aug '19

20 Aug '19

Hello Seunghwan Kim, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34898 to review the following change. Change subject: mb/google/kohaku: Use level trigger for touchscreen interrupt ...................................................................... mb/google/kohaku: Use level trigger for touchscreen interrupt Level trigger is recommended setting for touchscreen interrupt of kohaku, so we would change it as the recommedation. BUG=b:139179200 BRANCH=none TEST=Verified pen works on kohaku Change-Id: Ibbcdbe3ab555d014048f66ff527e539c5b566187 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.com> --- M src/mainboard/google/hatch/variants/kohaku/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/34898/1 diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 1d4c1c3..9e33bac 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -89,7 +89,7 @@ register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""atmel,maxtouch"" register "desc" = ""Atmel Touchscreen"" - register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D16_IRQ)" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "reset_delay_ms" = "91" # 90.5 ms register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C12)" -- To view, visit https://review.coreboot.org/c/coreboot/+/34898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibbcdbe3ab555d014048f66ff527e539c5b566187 Gerrit-Change-Number: 34898 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Seunghwan Kim <sh_.kim(a)samsung.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: AGESA: Define extra CFLAGS just once
by Kyösti Mälkki (Code Review) 20 Aug '19

20 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34798 ) Change subject: AGESA: Define extra CFLAGS just once ...................................................................... AGESA: Define extra CFLAGS just once Change-Id: I91d5a0fa0b5e4575d03eb083fade43f6dbb94c77 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/vendorcode/amd/agesa/Makefile.inc M src/vendorcode/amd/agesa/f12/Makefile.inc M src/vendorcode/amd/agesa/f14/Makefile.inc M src/vendorcode/amd/agesa/f15tn/Makefile.inc M src/vendorcode/amd/agesa/f16kb/Makefile.inc 5 files changed, 5 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/34798/1 diff --git a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc index df34330..d672cf4 100644 --- a/src/vendorcode/amd/agesa/Makefile.inc +++ b/src/vendorcode/amd/agesa/Makefile.inc @@ -12,6 +12,11 @@ libagesa-generic-ccopts += -D__LIBAGESA__ libagesa-generic-ccopts += $(AGESA_INC) $(AGESA_AUTOINCLUDES) +AGESA_CFLAGS := -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing + +CFLAGS_x86_32 += $(AGESA_CFLAGS) +CFLAGS_x86_64 += $(AGESA_CFLAGS) + ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) $(eval $(call create_class_compiler,libagesa,x86_32)) else diff --git a/src/vendorcode/amd/agesa/f12/Makefile.inc b/src/vendorcode/amd/agesa/f12/Makefile.inc index 9bc3c26..d53b3a3 100644 --- a/src/vendorcode/amd/agesa/f12/Makefile.inc +++ b/src/vendorcode/amd/agesa/f12/Makefile.inc @@ -40,9 +40,6 @@ BUILDOPTS_INCLUDES = -I$(AGESA_ROOT)/Config $(AGESA_INC) $(AGESA_AUTOINCLUDES) -CFLAGS_x86_32 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing -CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing - CPPFLAGS_x86_32 += $(AGESA_INC) CPPFLAGS_x86_64 += $(AGESA_INC) diff --git a/src/vendorcode/amd/agesa/f14/Makefile.inc b/src/vendorcode/amd/agesa/f14/Makefile.inc index da79a39..9726345 100644 --- a/src/vendorcode/amd/agesa/f14/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Makefile.inc @@ -40,9 +40,6 @@ BUILDOPTS_INCLUDES = -I$(AGESA_ROOT)/Config $(AGESA_INC) $(AGESA_AUTOINCLUDES) -CFLAGS_x86_32 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing -CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing - CPPFLAGS_x86_32 += $(AGESA_INC) CPPFLAGS_x86_64 += $(AGESA_INC) diff --git a/src/vendorcode/amd/agesa/f15tn/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Makefile.inc index 1c5dc18..24528da 100644 --- a/src/vendorcode/amd/agesa/f15tn/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Makefile.inc @@ -40,9 +40,6 @@ BUILDOPTS_INCLUDES = -I$(AGESA_ROOT)/Config $(AGESA_INC) $(AGESA_AUTOINCLUDES) -CFLAGS_x86_32 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing -CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing - # These are invalid, coreboot proper should not require # use of AGESA internal header files. CPPFLAGS_x86_ANY = diff --git a/src/vendorcode/amd/agesa/f16kb/Makefile.inc b/src/vendorcode/amd/agesa/f16kb/Makefile.inc index c423cf2..ddd6d62 100644 --- a/src/vendorcode/amd/agesa/f16kb/Makefile.inc +++ b/src/vendorcode/amd/agesa/f16kb/Makefile.inc @@ -40,9 +40,6 @@ BUILDOPTS_INCLUDES = -I$(AGESA_ROOT)/Config $(AGESA_INC) $(AGESA_AUTOINCLUDES) -CFLAGS_x86_32 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing -CFLAGS_x86_64 += -march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing - # These are invalid, coreboot proper should not require # use of AGESA internal header files. CPPFLAGS_x86_ANY = -- To view, visit https://review.coreboot.org/c/coreboot/+/34798 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91d5a0fa0b5e4575d03eb083fade43f6dbb94c77 Gerrit-Change-Number: 34798 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: devicetree: Remove duplicate chip_ops declarations
by Kyösti Mälkki (Code Review) 20 Aug '19

20 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34979 ) Change subject: devicetree: Remove duplicate chip_ops declarations ...................................................................... devicetree: Remove duplicate chip_ops declarations These are only referenced inside auto-generated static.c files, and util/sconfig also generates the declarations automatically from source file pathnames. Change-Id: Id324790755095c36fbeb73a4d8f9d01cdf6409cb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/haswell/chip.h M src/ec/compal/ene932/chip.h M src/ec/google/chromeec/chip.h M src/ec/google/wilco/chip.h M src/ec/quanta/ene_kb3940q/chip.h M src/ec/quanta/it8518/chip.h M src/ec/roda/it8518/chip.h M src/northbridge/intel/haswell/chip.h M src/soc/intel/baytrail/chip.h M src/soc/intel/braswell/chip.h M src/soc/intel/broadwell/chip.h M src/soc/intel/denverton_ns/chip.h M src/soc/intel/fsp_baytrail/chip.h M src/soc/intel/fsp_broadwell_de/chip.h M src/soc/intel/quark/chip.h M src/soc/intel/skylake/chip.h 16 files changed, 0 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/34979/1 diff --git a/src/cpu/intel/haswell/chip.h b/src/cpu/intel/haswell/chip.h index cd9ec5d..b2cb33b 100644 --- a/src/cpu/intel/haswell/chip.h +++ b/src/cpu/intel/haswell/chip.h @@ -13,8 +13,6 @@ * GNU General Public License for more details. */ -extern struct chip_operations cpu_intel_haswell_ops; - /* Magic value used to locate this chip in the device tree */ #define SPEEDSTEP_APIC_MAGIC 0xACAC diff --git a/src/ec/compal/ene932/chip.h b/src/ec/compal/ene932/chip.h index c7e4f8d..94f9752 100644 --- a/src/ec/compal/ene932/chip.h +++ b/src/ec/compal/ene932/chip.h @@ -17,11 +17,6 @@ #ifndef _EC_COMPAL_ENE932_CHIP_H #define _EC_COMPAL_ENE932_CHIP_H -#include <device/device.h> - -struct chip_operations; -extern struct chip_operations ec_compal_ene932_ops; - struct ec_compal_ene932_config { }; diff --git a/src/ec/google/chromeec/chip.h b/src/ec/google/chromeec/chip.h index 4eada16..1c9a7f5 100644 --- a/src/ec/google/chromeec/chip.h +++ b/src/ec/google/chromeec/chip.h @@ -16,9 +16,6 @@ #ifndef EC_GOOGLE_CHROMEEC_CHIP_H #define EC_GOOGLE_CHROMEEC_CHIP_H -#include <device/device.h> - -extern struct chip_operations ec_google_chromeec_ops; struct ec_google_chromeec_config { }; diff --git a/src/ec/google/wilco/chip.h b/src/ec/google/wilco/chip.h index 9b02ee3..06d889c 100644 --- a/src/ec/google/wilco/chip.h +++ b/src/ec/google/wilco/chip.h @@ -16,10 +16,6 @@ #ifndef EC_GOOGLE_WILCO_CHIP_H #define EC_GOOGLE_WILCO_CHIP_H -#include <device/device.h> - -extern struct chip_operations ec_google_wilco_ops; - struct ec_google_wilco_config { }; diff --git a/src/ec/quanta/ene_kb3940q/chip.h b/src/ec/quanta/ene_kb3940q/chip.h index 8348cc0..b812a18 100644 --- a/src/ec/quanta/ene_kb3940q/chip.h +++ b/src/ec/quanta/ene_kb3940q/chip.h @@ -17,11 +17,6 @@ #ifndef _EC_QUANTA_ENE_KB3940Q_CHIP_H #define _EC_QUANTA_ENE_KB3940Q_CHIP_H -#include <device/device.h> - -struct chip_operations; -extern struct chip_operations ec_quanta_ene_kb3940q_ops; - struct ec_quanta_ene_kb3940q_config { }; diff --git a/src/ec/quanta/it8518/chip.h b/src/ec/quanta/it8518/chip.h index ea9b4ac..5dd14f6 100644 --- a/src/ec/quanta/it8518/chip.h +++ b/src/ec/quanta/it8518/chip.h @@ -17,11 +17,6 @@ #ifndef _EC_QUANTA_IT8518_CHIP_H #define _EC_QUANTA_IT8518_CHIP_H -#include <device/device.h> - -struct chip_operations; -extern struct chip_operations ec_quanta_it8518_ops; - struct ec_quanta_it8518_config { }; diff --git a/src/ec/roda/it8518/chip.h b/src/ec/roda/it8518/chip.h index 44891e8..8091525 100644 --- a/src/ec/roda/it8518/chip.h +++ b/src/ec/roda/it8518/chip.h @@ -16,11 +16,6 @@ #ifndef _EC_RODA_IT8518_CHIP_H #define _EC_RODA_IT8518_CHIP_H -#include <device/device.h> - -struct chip_operations; -extern struct chip_operations ec_roda_it8518_ops; - struct ec_roda_it8518_config { u8 cpuhot_limit; /* temperature in °C which asserts PROCHOT# */ }; diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index fdabc3f..506aaa5 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -45,6 +45,4 @@ struct i915_gpu_controller_info gfx; }; -extern struct chip_operations northbridge_intel_haswell_ops; - #endif /* NORTHBRIDGE_INTEL_HASWELL_CHIP_H */ diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h index 00e7fd6..f153913 100644 --- a/src/soc/intel/baytrail/chip.h +++ b/src/soc/intel/baytrail/chip.h @@ -87,5 +87,4 @@ int disable_ddr_2x_refresh_rate; }; -extern struct chip_operations soc_intel_baytrail_ops; #endif /* _BAYTRAIL_CHIP_H_ */ diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 5a00328..747b941 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -171,6 +171,4 @@ UINT8 I2C6Frequency; }; -extern struct chip_operations soc_intel_braswell_ops; - #endif /* _SOC_CHIP_H_ */ diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 0885c2d..456a435 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -164,6 +164,4 @@ typedef struct soc_intel_broadwell_config config_t; -extern struct chip_operations soc_ops; - #endif diff --git a/src/soc/intel/denverton_ns/chip.h b/src/soc/intel/denverton_ns/chip.h index f2a67dd..53e86f9 100644 --- a/src/soc/intel/denverton_ns/chip.h +++ b/src/soc/intel/denverton_ns/chip.h @@ -72,8 +72,6 @@ uint32_t ipc3; }; -extern struct chip_operations soc_intel_denverton_ns_ops; - typedef struct soc_intel_denverton_ns_config config_t; #endif /* SOC_INTEL_FSP_DENVERTON_NS_CHIP_H */ diff --git a/src/soc/intel/fsp_baytrail/chip.h b/src/soc/intel/fsp_baytrail/chip.h index 156a084..b73aa14 100644 --- a/src/soc/intel/fsp_baytrail/chip.h +++ b/src/soc/intel/fsp_baytrail/chip.h @@ -353,5 +353,4 @@ }; -extern struct chip_operations soc_intel_fsp_baytrail_ops; #endif /* _FSP_BAYTRAIL_CHIP_H_ */ diff --git a/src/soc/intel/fsp_broadwell_de/chip.h b/src/soc/intel/fsp_broadwell_de/chip.h index b7f59f7..bf28962 100644 --- a/src/soc/intel/fsp_broadwell_de/chip.h +++ b/src/soc/intel/fsp_broadwell_de/chip.h @@ -29,5 +29,4 @@ typedef struct soc_intel_fsp_broadwell_de_config config_t; -extern struct chip_operations soc_intel_fsp_broadwell_de_ops; #endif /* _SOC_CHIP_H_ */ diff --git a/src/soc/intel/quark/chip.h b/src/soc/intel/quark/chip.h index 25d734a..4e57273 100644 --- a/src/soc/intel/quark/chip.h +++ b/src/soc/intel/quark/chip.h @@ -113,6 +113,4 @@ uint8_t SmmTsegSize; /* SMM size in MiB */ }; -extern struct chip_operations soc_ops; - #endif diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 6c105ce..1313dc1 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -591,6 +591,4 @@ typedef struct soc_intel_skylake_config config_t; -extern struct chip_operations soc_ops; - #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/34979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id324790755095c36fbeb73a4d8f9d01cdf6409cb Gerrit-Change-Number: 34979 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: google/stout: Use MAYBE_STATIC
by Kyösti Mälkki (Code Review) 20 Aug '19

20 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34924 ) Change subject: google/stout: Use MAYBE_STATIC ...................................................................... google/stout: Use MAYBE_STATIC Change-Id: I11027acb11a4656536384134d0caebd14b63770c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/stout/chromeos.c 1 file changed, 8 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/34924/1 diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index ff247da..f186f83 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -71,10 +71,9 @@ */ int get_recovery_mode_switch(void) { -#ifndef __PRE_RAM__ - static int ec_in_rec_mode = 0; - static int ec_rec_flag_good = 0; -#endif + MAYBE_STATIC int ec_in_rec_mode = 0; + MAYBE_STATIC int ec_rec_flag_good = 0; + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); u8 reg8 = pci_s_read_config8(dev, GEN_PMCON_3); @@ -83,17 +82,13 @@ printk(BIOS_SPEW,"%s: EC status:%#x RTC_BAT: %x\n", __func__, ec_status, reg8 & RTC_BATTERY_DEAD); -#ifdef __PRE_RAM__ - return (((reg8 & RTC_BATTERY_DEAD) != 0) && - ((ec_status & 0x3) == EC_IN_RECOVERY_MODE)); -#else - if (!ec_rec_flag_good) { - ec_in_rec_mode = (((reg8 & RTC_BATTERY_DEAD) != 0) && + if (ec_rec_flag_good) + return ec_in_rec_mode; + + ec_in_rec_mode = (((reg8 & RTC_BATTERY_DEAD) != 0) && ((ec_status & 0x3) == EC_IN_RECOVERY_MODE)); - ec_rec_flag_good = 1; - } + ec_rec_flag_good = 1; return ec_in_rec_mode; -#endif } static const struct cros_gpio cros_gpios[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/34924 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11027acb11a4656536384134d0caebd14b63770c Gerrit-Change-Number: 34924 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: google/butterfly: Replace use of #ifndef __PRE_RAM__
by Kyösti Mälkki (Code Review) 20 Aug '19

20 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34926 ) Change subject: google/butterfly: Replace use of #ifndef __PRE_RAM__ ...................................................................... google/butterfly: Replace use of #ifndef __PRE_RAM__ Change-Id: Iae944b589d587b30826e935feae029aa8d07d5d9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/butterfly/chromeos.c 1 file changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/34926/1 diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c index 2825aae..1a1a2e1 100644 --- a/src/mainboard/google/butterfly/chromeos.c +++ b/src/mainboard/google/butterfly/chromeos.c @@ -71,13 +71,12 @@ return 1; #endif + if (ENV_RAMSTAGE) { + if (ec_mem_read(EC_CODE_STATE) == EC_COS_EC_RO) + ec_rec_mode = 1; -#ifndef __PRE_RAM__ - if (ec_mem_read(EC_CODE_STATE) == EC_COS_EC_RO) { - ec_rec_mode = 1; + printk(BIOS_DEBUG,"RECOVERY MODE FROM EC: %x\n", ec_rec_mode); } - printk(BIOS_DEBUG,"RECOVERY MODE FROM EC: %x\n", ec_rec_mode); -#endif return ec_rec_mode; } -- To view, visit https://review.coreboot.org/c/coreboot/+/34926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae944b589d587b30826e935feae029aa8d07d5d9 Gerrit-Change-Number: 34926 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/non-x86: Replace uses of __PRE_RAM__
by Kyösti Mälkki (Code Review) 20 Aug '19

20 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34921 ) Change subject: arch/non-x86: Replace uses of __PRE_RAM__ ...................................................................... arch/non-x86: Replace uses of __PRE_RAM__ Since there is no __SMM__ to worry about, !defined(__PRE_RAM__) becomes just ENV_RAMSTAGE. Change-Id: Id8918f40572497b068509b5d5a490de0435ad50b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/arm/include/armv7/arch/cpu.h M src/arch/arm64/include/armv8/arch/cpu.h M src/arch/mips/include/arch/cpu.h M src/arch/ppc64/include/arch/cpu.h M src/arch/riscv/include/arch/cpu.h M src/arch/riscv/include/arch/memlayout.h M src/cpu/ti/am335x/uart.c M src/drivers/uart/pl011.c M src/drivers/uart/sifive.c M src/mainboard/emulation/qemu-power8/uart.c M src/soc/imgtec/pistachio/uart.c M src/soc/mediatek/common/uart.c M src/soc/nvidia/tegra/dc.h M src/soc/nvidia/tegra124/uart.c M src/soc/nvidia/tegra210/uart.c M src/soc/qualcomm/ipq40xx/uart.c M src/soc/qualcomm/ipq806x/uart.c M src/soc/qualcomm/qcs405/uart.c M src/soc/samsung/exynos5250/uart.c M src/soc/samsung/exynos5420/alternate_cbfs.c M src/soc/samsung/exynos5420/uart.c 21 files changed, 24 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/34921/1 diff --git a/src/arch/arm/include/armv7/arch/cpu.h b/src/arch/arm/include/armv7/arch/cpu.h index 22b3fb4..52bfe11 100644 --- a/src/arch/arm/include/armv7/arch/cpu.h +++ b/src/arch/arm/include/armv7/arch/cpu.h @@ -20,7 +20,7 @@ #define asmlinkage -#if !defined(__PRE_RAM__) +#if ENV_RAMSTAGE #include <device/device.h> struct cpu_driver { diff --git a/src/arch/arm64/include/armv8/arch/cpu.h b/src/arch/arm64/include/armv8/arch/cpu.h index 6e096cc..e1b5647 100644 --- a/src/arch/arm64/include/armv8/arch/cpu.h +++ b/src/arch/arm64/include/armv8/arch/cpu.h @@ -21,7 +21,7 @@ static inline unsigned int smp_processor_id(void) { return 0; } -#if !defined(__PRE_RAM__) +#if ENV_RAMSTAGE struct cpu_driver { }; #endif diff --git a/src/arch/mips/include/arch/cpu.h b/src/arch/mips/include/arch/cpu.h index 8e35908..8290c1a 100644 --- a/src/arch/mips/include/arch/cpu.h +++ b/src/arch/mips/include/arch/cpu.h @@ -18,7 +18,7 @@ #define asmlinkage -#ifndef __PRE_RAM__ +#if ENV_RAMSTAGE #include <device/device.h> @@ -34,7 +34,7 @@ unsigned long index; }; -#endif /* !__PRE_RAM__ */ +#endif /* ENV_RAMSTAGE */ /*************************************************************************** * The following section was copied from arch/mips/include/asm/mipsregs.h in diff --git a/src/arch/ppc64/include/arch/cpu.h b/src/arch/ppc64/include/arch/cpu.h index 1e13528..c80f65e 100644 --- a/src/arch/ppc64/include/arch/cpu.h +++ b/src/arch/ppc64/include/arch/cpu.h @@ -18,7 +18,7 @@ #define asmlinkage -#if !defined(__PRE_RAM__) +#if ENV_RAMSTAGE #include <device/device.h> struct cpu_driver { diff --git a/src/arch/riscv/include/arch/cpu.h b/src/arch/riscv/include/arch/cpu.h index 547cb76..529daa0 100644 --- a/src/arch/riscv/include/arch/cpu.h +++ b/src/arch/riscv/include/arch/cpu.h @@ -20,7 +20,7 @@ #define asmlinkage -#if !defined(__PRE_RAM__) +#if ENV_RAMSTAGE #include <device/device.h> struct cpu_driver { diff --git a/src/arch/riscv/include/arch/memlayout.h b/src/arch/riscv/include/arch/memlayout.h index 7baab76..d1e9673 100644 --- a/src/arch/riscv/include/arch/memlayout.h +++ b/src/arch/riscv/include/arch/memlayout.h @@ -20,7 +20,7 @@ #define STACK(addr, size) REGION(stack, addr, size, 4096) -#if defined(__PRE_RAM__) +#if !ENV_RAMSTAGE #define CAR_STACK(addr, size) \ REGION(car_stack, addr, size, 4K) \ ALIAS_REGION(car_stack, stack) diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index 4e9d012..f42b946 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -182,7 +182,7 @@ { } -#ifndef __PRE_RAM__ +#if ENV_RAMSTAGE void uart_fill_lb(void *data) { struct lb_serial serial; diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index 4e3af52..1764f15 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -49,7 +49,7 @@ return read8(&regs->dr); } -#ifndef __PRE_RAM__ +#if ENV_RAMSTAGE void uart_fill_lb(void *data) { struct lb_serial serial; diff --git a/src/drivers/uart/sifive.c b/src/drivers/uart/sifive.c index 1b0f75e..9ca669a 100644 --- a/src/drivers/uart/sifive.c +++ b/src/drivers/uart/sifive.c @@ -113,7 +113,7 @@ return 1; } -#ifndef __PRE_RAM__ +#if ENV_RAMSTAGE void uart_fill_lb(void *data) { /* TODO */ diff --git a/src/mainboard/emulation/qemu-power8/uart.c b/src/mainboard/emulation/qemu-power8/uart.c index 9548b7c..76c8afc 100644 --- a/src/mainboard/emulation/qemu-power8/uart.c +++ b/src/mainboard/emulation/qemu-power8/uart.c @@ -41,7 +41,7 @@ { } -#ifndef __PRE_RAM__ +#if ENV_RAMSTAGE void uart_fill_lb(void *data) { struct lb_serial serial; diff --git a/src/soc/imgtec/pistachio/uart.c b/src/soc/imgtec/pistachio/uart.c index a39f2ec..9d15237 100644 --- a/src/soc/imgtec/pistachio/uart.c +++ b/src/soc/imgtec/pistachio/uart.c @@ -143,7 +143,7 @@ uart8250_mem_tx_flush(CONFIG_CONSOLE_SERIAL_UART_ADDRESS); } -#ifndef __PRE_RAM__ +#if ENV_RAMSTAGE void uart_fill_lb(void *data) { struct lb_serial serial; diff --git a/src/soc/mediatek/common/uart.c b/src/soc/mediatek/common/uart.c index 8905c55..c1b4616 100644 --- a/src/soc/mediatek/common/uart.c +++ b/src/soc/mediatek/common/uart.c @@ -172,7 +172,7 @@ mtk_uart_tx_flush(); } -#ifndef __PRE_RAM__ +#if ENV_RAMSTAGE void uart_fill_lb(void *data) { struct lb_serial serial; diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h index a9061f8..da296da 100644 --- a/src/soc/nvidia/tegra/dc.h +++ b/src/soc/nvidia/tegra/dc.h @@ -515,7 +515,7 @@ unsigned long READL(void *p); void WRITEL(unsigned long value, void *p); -#ifndef __PRE_RAM__ +#if ENV_RAMSTAGE void display_startup(struct device *dev); #endif void dp_init(void *_config); diff --git a/src/soc/nvidia/tegra124/uart.c b/src/soc/nvidia/tegra124/uart.c index c9514ac..923fdd7 100644 --- a/src/soc/nvidia/tegra124/uart.c +++ b/src/soc/nvidia/tegra124/uart.c @@ -128,7 +128,7 @@ tegra124_uart_tx_flush(uart_ptr); } -#ifndef __PRE_RAM__ +#if ENV_RAMSTAGE void uart_fill_lb(void *data) { struct lb_serial serial; diff --git a/src/soc/nvidia/tegra210/uart.c b/src/soc/nvidia/tegra210/uart.c index a91818c..3d8e53e 100644 --- a/src/soc/nvidia/tegra210/uart.c +++ b/src/soc/nvidia/tegra210/uart.c @@ -115,7 +115,7 @@ return tegra210_uart_rx_byte(); } -#ifndef __PRE_RAM__ +#if ENV_RAMSTAGE void uart_fill_lb(void *data) { struct lb_serial serial; diff --git a/src/soc/qualcomm/ipq40xx/uart.c b/src/soc/qualcomm/ipq40xx/uart.c index eb3731b..6d3b72a 100644 --- a/src/soc/qualcomm/ipq40xx/uart.c +++ b/src/soc/qualcomm/ipq40xx/uart.c @@ -283,7 +283,7 @@ return byte; } -#ifndef __PRE_RAM__ +#if ENV_RAMSTAGE /* TODO: Implement function */ void uart_fill_lb(void *data) { diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c index 66c3103..7b70283 100644 --- a/src/soc/qualcomm/ipq806x/uart.c +++ b/src/soc/qualcomm/ipq806x/uart.c @@ -398,7 +398,7 @@ return byte; } -#ifndef __PRE_RAM__ +#if ENV_RAMSTAGE /* TODO: Implement fuction */ void uart_fill_lb(void *data) { diff --git a/src/soc/qualcomm/qcs405/uart.c b/src/soc/qualcomm/qcs405/uart.c index 4a43312..d7e3bcd 100644 --- a/src/soc/qualcomm/qcs405/uart.c +++ b/src/soc/qualcomm/qcs405/uart.c @@ -287,7 +287,7 @@ } #endif -#ifndef __PRE_RAM__ +#if ENV_RAMSTAGE void uart_fill_lb(void *data) { struct lb_serial serial; diff --git a/src/soc/samsung/exynos5250/uart.c b/src/soc/samsung/exynos5250/uart.c index 1b8e785..f2b4d82 100644 --- a/src/soc/samsung/exynos5250/uart.c +++ b/src/soc/samsung/exynos5250/uart.c @@ -185,7 +185,7 @@ exynos5_uart_tx_flush(uart); } -#ifndef __PRE_RAM__ +#if ENV_RAMSTAGE void uart_fill_lb(void *data) { struct lb_serial serial; diff --git a/src/soc/samsung/exynos5420/alternate_cbfs.c b/src/soc/samsung/exynos5420/alternate_cbfs.c index ba3f9a3..38e7cf9 100644 --- a/src/soc/samsung/exynos5420/alternate_cbfs.c +++ b/src/soc/samsung/exynos5420/alternate_cbfs.c @@ -37,11 +37,11 @@ * function is called a second time at the end of the romstage, and copied to * the romstage/ramstage CBFS cache in DRAM. It will reside there for the * rest of the firmware's lifetime and all subsequent stages (which will not - * have __PRE_RAM__ defined) can just directly reference it there. + * have !ENV_RAMSTAGE defined) can just directly reference it there. */ static int usb_cbfs_open(void) { -#ifdef __PRE_RAM__ +#ifdef !ENV_RAMSTAGE static int first_run = 1; int (*irom_load_usb)(void) = *irom_load_image_from_usb_ptr; @@ -79,7 +79,7 @@ */ static int sdmmc_cbfs_open(void) { -#ifdef __PRE_RAM__ +#ifdef !ENV_RAMSTAGE /* * In the bootblock, we just copy the small part that fits in the buffer * and hope that it's enough (since the romstage is currently always the diff --git a/src/soc/samsung/exynos5420/uart.c b/src/soc/samsung/exynos5420/uart.c index b2a0edd..9c78075 100644 --- a/src/soc/samsung/exynos5420/uart.c +++ b/src/soc/samsung/exynos5420/uart.c @@ -176,7 +176,7 @@ /* Exynos5250 implements this too. */ } -#ifndef __PRE_RAM__ +#if ENV_RAMSTAGE void uart_fill_lb(void *data) { struct lb_serial serial; -- To view, visit https://review.coreboot.org/c/coreboot/+/34921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8918f40572497b068509b5d5a490de0435ad50b Gerrit-Change-Number: 34921 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: rules: Add ability to disable ENV_CACHE_AS_RAM
by Marshall Dawson (Code Review) 20 Aug '19

20 Aug '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34913 ) Change subject: rules: Add ability to disable ENV_CACHE_AS_RAM ...................................................................... rules: Add ability to disable ENV_CACHE_AS_RAM Change-Id: I3acace92b39093cfb51f71f0dd39582c1e3c8c9a Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/Kconfig M src/include/rules.h 2 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/34913/1 diff --git a/src/Kconfig b/src/Kconfig index f051216..1bcca23 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -159,6 +159,12 @@ Select this option if the soc implements custom assembly entry code for early stages. +config NO_ENV_CACHE_AS_RAM + bool + depends on ARCH_X86 + help + Select this option if the soc doesn't use ENV_CACHE_AS_RAM. + config COMPRESS_BOOTBLOCK bool depends on HAVE_BOOTBLOCK diff --git a/src/include/rules.h b/src/include/rules.h index 10cd715..cda13bb 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -284,7 +284,7 @@ /* x86 specific. Indicates that the current stage is running with cache-as-ram * enabled from the beginning of the stage in C code. */ #if defined(__PRE_RAM__) -#define ENV_CACHE_AS_RAM CONFIG(ARCH_X86) +#define ENV_CACHE_AS_RAM (CONFIG(ARCH_X86) && !CONFIG(NO_ENV_CACHE_AS_RAM)) #else #define ENV_CACHE_AS_RAM 0 #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/34913 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3acace92b39093cfb51f71f0dd39582c1e3c8c9a Gerrit-Change-Number: 34913 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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