coreboot-gerrit August 2019

coreboot-gerrit@coreboot.org

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1942 discussions

Change in coreboot[master]: soc/amd/picasso: Create a hybrid romstage to begin in DRAM
by Marshall Dawson (Code Review) 20 Aug '19

20 Aug '19

Hello Edward O'Callaghan, Julius Werner, Richard Spiegel, build bot (Jenkins), Furquan Shaikh, Martin Roth, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/33759 to look at the new patch set (#12). Change subject: soc/amd/picasso: Create a hybrid romstage to begin in DRAM ...................................................................... soc/amd/picasso: Create a hybrid romstage to begin in DRAM Add the support files to begin execution in romstage and located in DRAM. Details for this implementation are found in Documentation/amd/picasso/family17.md. Combine steps typically found in bootblock, containing the reset vector and protected mode enable, with the parts of romstage that enable the console and cbmem. Duplicate the ROMSTAGE_ADDR and ROMSTAGE_MAX_SIZE items into Kconfig and give them safe default values in DRAM. The DCACHE values are kept and DRAM is used as a CAR substitute. Add a romstage.ld file that positions the reset vector and describes the additional items needed for the hybrid romstage. Change-Id: Id8c6175de34a0728ad41085e9c7cd310bd280976 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M 3rdparty/blobs M 3rdparty/fsp M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/include/soc/cpu.h M src/soc/amd/picasso/include/soc/romstage.h A src/soc/amd/picasso/include/soc/romstage.ld A src/soc/amd/picasso/reset_vector.S M src/soc/amd/picasso/romstage.c 9 files changed, 287 insertions(+), 75 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/33759/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/33759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8c6175de34a0728ad41085e9c7cd310bd280976 Gerrit-Change-Number: 33759 Gerrit-PatchSet: 12 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Aaron Durbin <adurbin(a)chromium.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: commonlib/region: Fix up overflow check in region_is_subregion()
by Julius Werner (Code Review) 19 Aug '19

19 Aug '19

Hello Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/34892 to review the following change. Change subject: commonlib/region: Fix up overflow check in region_is_subregion() ...................................................................... commonlib/region: Fix up overflow check in region_is_subregion() region_is_subregion() checks whether the size of the inner region is larger than the size of the outer region... which isn't really necessary because we're already checking the starts and ends of both regions. Maybe this was added to ensure the inner region doesn't overflow? But it's not guaranteed to catch that in all cases. Replace it with a proper overflow check. Change-Id: I9e442053584a479a323c1fa1c0591934ff83eb10 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M src/commonlib/region.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/34892/1 diff --git a/src/commonlib/region.c b/src/commonlib/region.c index 541a125..b5858f9 100644 --- a/src/commonlib/region.c +++ b/src/commonlib/region.c @@ -27,10 +27,10 @@ if (region_offset(c) < region_offset(p)) return 0; - if (region_sz(c) > region_sz(p)) + if (region_end(c) > region_end(p)) return 0; - if (region_end(c) > region_end(p)) + if (region_end(c) < region_offset(c)) return 0; return 1; -- To view, visit https://review.coreboot.org/c/coreboot/+/34892 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e442053584a479a323c1fa1c0591934ff83eb10 Gerrit-Change-Number: 34892 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
by Maxim Polyakov (Code Review) 19 Aug '19

19 Aug '19

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32734 ) Change subject: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF ...................................................................... Patch Set 71: (3 comments) https://review.coreboot.org/c/coreboot/+/32734/68/src/mainboard/supermicro/… File src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb: https://review.coreboot.org/c/coreboot/+/32734/68/src/mainboard/supermicro/… PS68, Line 28: register "SkipExtGfxScan" = "1" > Works without FSP knowing about that device as it only claims 16MiB BAR. Will the video also be output to Aspeed VGA If I install an external graphics card in the PEG port? https://review.coreboot.org/c/coreboot/+/32734/68/src/mainboard/supermicro/… PS68, Line 209: device pci 01.0 on end # PCI Slot > unused Sorry, it seemed to me that PEG0 is used for the NVMe M.2 https://review.coreboot.org/c/coreboot/+/32734/68/src/mainboard/supermicro/… PS68, Line 210: device pci 01.1 on > PEGx8 slot, […] - I think it would be better to use width limit. This allows SFP to do bus training only for the PCIe data lines that are used in the slot/connector. - In my case, PEG Gen3 only works with SRCCLKREQ/CLKSRC. -- To view, visit https://review.coreboot.org/c/coreboot/+/32734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 Gerrit-Change-Number: 32734 Gerrit-PatchSet: 71 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Keno Fischer <keno(a)alumni.harvard.edu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Name of user not set #1002358 Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: T. Hudson <trammell.hudson(a)gmail.com> Gerrit-Reviewer: Trammell Hudson <hudson(a)trmm.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Michael Niewöhner Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 19 Aug 2019 20:01:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: intel/fsp2_0: Add TS_BEFORE_RAMINIT and TS_AFTER_RAMINIT
by Kyösti Mälkki (Code Review) 19 Aug '19

19 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34971 ) Change subject: intel/fsp2_0: Add TS_BEFORE_RAMINIT and TS_AFTER_RAMINIT ...................................................................... intel/fsp2_0: Add TS_BEFORE_RAMINIT and TS_AFTER_RAMINIT Change-Id: I99dbef5d52e4fc6cde22876216052cbe998822cf Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/drivers/intel/fsp2_0/memory_init.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/34971/1 diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index f248a58..0797c2e 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -389,6 +389,8 @@ struct memranges memmap; struct range_entry freeranges[2]; + timestamp_add_now(TS_BEFORE_INITRAM); + if (CONFIG(ELOG_BOOT_COUNT) && !s3wake) boot_count_increment(); @@ -417,4 +419,6 @@ prog_segment_loaded(hdr.image_base, hdr.image_size, SEG_FINAL); do_fsp_memory_init(&hdr, s3wake, &memmap); + + timestamp_add_now(TS_AFTER_INITRAM); } -- To view, visit https://review.coreboot.org/c/coreboot/+/34971 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I99dbef5d52e4fc6cde22876216052cbe998822cf Gerrit-Change-Number: 34971 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: emulation/qemu-x86: Fix romstage stack alignment
by Kyösti Mälkki (Code Review) 19 Aug '19

19 Aug '19

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34975 ) Change subject: emulation/qemu-x86: Fix romstage stack alignment ...................................................................... emulation/qemu-x86: Fix romstage stack alignment Also tidy up some register usage. Change-Id: I5b4b4a29c854f4ca165cede4e9b6755a6c577e76 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34975 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/qemu-x86/cache_as_ram_bootblock.S 1 file changed, 10 insertions(+), 10 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/cpu/qemu-x86/cache_as_ram_bootblock.S b/src/cpu/qemu-x86/cache_as_ram_bootblock.S index 8e78aaa..f8dab1a 100644 --- a/src/cpu/qemu-x86/cache_as_ram_bootblock.S +++ b/src/cpu/qemu-x86/cache_as_ram_bootblock.S @@ -28,22 +28,22 @@ * initialization. */ - post_code(0x21) - - movl $_car_stack_end, %esp - /* Align the stack and keep aligned for call to bootblock_c_entry() */ - and $0xfffffff0, %esp - sub $12, %esp - /* Clear the cache memory region. This will also clear CAR GLOBAL */ - movl $_car_region_start, %esi - movl %esi, %edi + movl $_car_region_start, %edi movl $_car_region_end, %ecx - sub $_car_region_start, %ecx + sub %edi, %ecx shr $2, %ecx xorl %eax, %eax rep stosl + post_code(0x21) + + movl $_car_stack_end, %esp + + /* Align the stack and keep aligned for call to bootblock_c_entry() */ + and $0xfffffff0, %esp + sub $4, %esp + /* Restore the BIST result and timestamps. */ movd %mm0, %ebx movd %mm1, %eax -- To view, visit https://review.coreboot.org/c/coreboot/+/34975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b4b4a29c854f4ca165cede4e9b6755a6c577e76 Gerrit-Change-Number: 34975 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: google/rambi: Replace __PRE_RAM__ with ENV_ROMSTAGE
by Kyösti Mälkki (Code Review) 19 Aug '19

19 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34981 ) Change subject: google/rambi: Replace __PRE_RAM__ with ENV_ROMSTAGE ...................................................................... google/rambi: Replace __PRE_RAM__ with ENV_ROMSTAGE Change-Id: I9d86f8475221b52ccdb45cdeaf538e85ab7a17c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/google/rambi/chromeos.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/34981/1 diff --git a/src/mainboard/google/rambi/chromeos.c b/src/mainboard/google/rambi/chromeos.c index 859fb0b..3472b1c 100644 --- a/src/mainboard/google/rambi/chromeos.c +++ b/src/mainboard/google/rambi/chromeos.c @@ -41,9 +41,8 @@ * there is a 10K pullup. Disable the internal pull in romstage so that * there isn't any ambiguity in the reading. */ -#if defined(__PRE_RAM__) - ssus_disable_internal_pull(WP_STATUS_PAD); -#endif + if (ENV_ROMSTAGE) + ssus_disable_internal_pull(WP_STATUS_PAD); /* WP is enabled when the pin is reading high. */ return ssus_get_gpio(WP_STATUS_PAD); -- To view, visit https://review.coreboot.org/c/coreboot/+/34981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d86f8475221b52ccdb45cdeaf538e85ab7a17c0 Gerrit-Change-Number: 34981 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake/vr_config: Add support for KBL-H and KBL-S
by Philipp Deppenwiese (Code Review) 19 Aug '19

19 Aug '19

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34937 ) Change subject: soc/intel/skylake/vr_config: Add support for KBL-H and KBL-S ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/34937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I303c5dc8ed03e9a98a834a2acfb400022dfc2fde Gerrit-Change-Number: 34937 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Aug 2019 16:13:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake/vr_config: Get rid of static lookup table
by Philipp Deppenwiese (Code Review) 19 Aug '19

19 Aug '19

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34936 ) Change subject: soc/intel/skylake/vr_config: Get rid of static lookup table ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/34936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib11c3d6e1eb339a0c7358c312a32731d835e7c73 Gerrit-Change-Number: 34936 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Aug 2019 16:13:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
by Patrick Rudolph (Code Review) 19 Aug '19

19 Aug '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32734 ) Change subject: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF ...................................................................... Patch Set 71: (7 comments) https://review.coreboot.org/c/coreboot/+/32734/68//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/32734/68//COMMIT_MSG@12 PS68, Line 12: * SeaBios payload : * LinuxBoot payload > What version? master https://review.coreboot.org/c/coreboot/+/32734/68//COMMIT_MSG@25 PS68, Line 25: Please apply those patches as well for good user experience: : : I456be647b159f7a2ea7d94986a24424e56dcc8c4 : I22c6885eae6fd7c778ac37b18f95b8775e9064e3 : Ica0c20255f661dd61edc3a7d15646b7447c4658e > This should be a comment, and not in the commit message in my opinion. How do you add comments to the commit message? https://review.coreboot.org/c/coreboot/+/32734/68/src/mainboard/supermicro/… File src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb: https://review.coreboot.org/c/coreboot/+/32734/68/src/mainboard/supermicro/… PS68, Line 28: register "SkipExtGfxScan" = "1" > I think it would be better to set Aspeed VGA as primary: […] Works without FSP knowing about that device as it only claims 16MiB BAR. https://review.coreboot.org/c/coreboot/+/32734/68/src/mainboard/supermicro/… PS68, Line 146: 0x50 > May be better to use the macro VR_CFG_AMP() […] Done https://review.coreboot.org/c/coreboot/+/32734/68/src/mainboard/supermicro/… PS68, Line 209: device pci 01.0 on end # PCI Slot > Is this M.2 Interface or PEGx8 slot[1]? Please add more information to the comment. […] unused https://review.coreboot.org/c/coreboot/+/32734/68/src/mainboard/supermicro/… PS68, Line 210: device pci 01.1 on > register "Peg1MaxLinkWidth" = "Peg1_x8" if PEGx8 slot […] PEGx8 slot, No need to add additional register values. SRCCLKREQ isn't used. https://review.coreboot.org/c/coreboot/+/32734/68/src/mainboard/supermicro/… PS68, Line 211: 4X > X4 or X8??? X8 slot with X4 data width -- To view, visit https://review.coreboot.org/c/coreboot/+/32734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 Gerrit-Change-Number: 32734 Gerrit-PatchSet: 71 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Keno Fischer <keno(a)alumni.harvard.edu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Name of user not set #1002358 Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: T. Hudson <trammell.hudson(a)gmail.com> Gerrit-Reviewer: Trammell Hudson <hudson(a)trmm.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Michael Niewöhner Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 19 Aug 2019 14:03:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maxim Polyakov <max.senia.poliak(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
by Patrick Rudolph (Code Review) 19 Aug '19

19 Aug '19

Patrick Rudolph has uploaded a new patch set (#71) to the change originally created by Christian Walter. ( https://review.coreboot.org/c/coreboot/+/32734 ) Change subject: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF ...................................................................... mb/supermicro/x11ssh: Add Supermicro X11SSH-TF Add support for the X11SSH-TF which is based on Intel KBL. Working: * SeaBios payload * LinuxBoot payload * IPMI of BMC * PCIe, SATA, USB and M.2 ports * RS232 serial * Native graphics init Not working: * Tianocore doesn't work yet as the Aspeed NGI is text mode only. * Intel SGX, due to random crashes in soc/intel/common For more details have a look at the documentation. Please apply those patches as well for good user experience: I456be647b159f7a2ea7d94986a24424e56dcc8c4 I22c6885eae6fd7c778ac37b18f95b8775e9064e3 Ica0c20255f661dd61edc3a7d15646b7447c4658e Signed-off-by: Christian Walter <christian.walter(a)9elements.com> Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 --- M Documentation/mainboard/index.md A Documentation/mainboard/supermicro/x11ssh-tf.md A Documentation/mainboard/supermicro/x11ssh_flash.jpg A src/mainboard/supermicro/x11ssh/Kconfig A src/mainboard/supermicro/x11ssh/Kconfig.name A src/mainboard/supermicro/x11ssh/Makefile.inc A src/mainboard/supermicro/x11ssh/acpi/ec.asl A src/mainboard/supermicro/x11ssh/acpi/mainboard.asl A src/mainboard/supermicro/x11ssh/acpi/superio.asl A src/mainboard/supermicro/x11ssh/acpi_tables.c A src/mainboard/supermicro/x11ssh/board_info.txt A src/mainboard/supermicro/x11ssh/bootblock.c A src/mainboard/supermicro/x11ssh/cmos.layout A src/mainboard/supermicro/x11ssh/dsdt.asl A src/mainboard/supermicro/x11ssh/gpio.h A src/mainboard/supermicro/x11ssh/mainboard.c A src/mainboard/supermicro/x11ssh/ramstage.c A src/mainboard/supermicro/x11ssh/romstage.c A src/mainboard/supermicro/x11ssh/variants/tf/board_info.txt A src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb A src/mainboard/supermicro/x11ssh/vboot-ro-rwab.fmd 21 files changed, 1,020 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/32734/71 -- To view, visit https://review.coreboot.org/c/coreboot/+/32734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 Gerrit-Change-Number: 32734 Gerrit-PatchSet: 71 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Keno Fischer <keno(a)alumni.harvard.edu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Name of user not set #1002358 Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: T. Hudson <trammell.hudson(a)gmail.com> Gerrit-Reviewer: Trammell Hudson <hudson(a)trmm.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Michael Niewöhner Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit August 2019