coreboot-gerrit August 2019

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Change in coreboot[master]: AGESA,binaryPI: Fix use of chip.h
by Kyösti Mälkki (Code Review) 20 Aug '19

20 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34996 ) Change subject: AGESA,binaryPI: Fix use of chip.h ...................................................................... AGESA,binaryPI: Fix use of chip.h Change-Id: I123db3a51a8f354359e8ed5040d23111ea4eb8a4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/amd/agesa/hudson/hudson.h M src/southbridge/amd/agesa/hudson/sd.c M src/southbridge/amd/pi/hudson/hudson.h M src/southbridge/amd/pi/hudson/sd.c 4 files changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/34996/1 diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index bd49e8f..5d9d849 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -18,7 +18,6 @@ #define HUDSON_H #include <device/device.h> -#include "chip.h" /* Power management index/data registers */ #define BIOSRAM_INDEX 0xcd4 diff --git a/src/southbridge/amd/agesa/hudson/sd.c b/src/southbridge/amd/agesa/hudson/sd.c index cc9470e..25acf0c 100644 --- a/src/southbridge/amd/agesa/hudson/sd.c +++ b/src/southbridge/amd/agesa/hudson/sd.c @@ -18,18 +18,19 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> +#include "chip.h" #include "hudson.h" static void sd_init(struct device *dev) { - u32 stepping; + struct southbridge_amd_agesa_hudson_config *sd_chip = dev->chip_info; + u32 stepping = pci_read_config32(pcidev_on_root(0x18, 3), 0xFC); + u8 sd_mode = 0; - stepping = pci_read_config32(pcidev_on_root(0x18, 3), 0xFC); + if (sd_chip) + sd_mode = sd_chip->sd_mode; - struct southbridge_amd_agesa_hudson_config *sd_chip = - (struct southbridge_amd_agesa_hudson_config *)(dev->chip_info); - - if (sd_chip->sd_mode == 3) { /* SD 3.0 mode */ + if (sd_mode == 3) { /* SD 3.0 mode */ pci_write_config32(dev, 0xA4, 0x31FEC8B2); pci_write_config32(dev, 0xA8, 0x00002503); pci_write_config32(dev, 0xB0, 0x02180C19); diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 6afcc65..99e3721 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -19,7 +19,6 @@ #include <types.h> #include <device/device.h> -#include "chip.h" /* Offsets from ACPI_MMIO_BASE * This is defined by AGESA, but we don't include AGESA headers to avoid diff --git a/src/southbridge/amd/pi/hudson/sd.c b/src/southbridge/amd/pi/hudson/sd.c index e4ace38..c22b988 100644 --- a/src/southbridge/amd/pi/hudson/sd.c +++ b/src/southbridge/amd/pi/hudson/sd.c @@ -18,18 +18,19 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> +#include "chip.h" #include "hudson.h" static void sd_init(struct device *dev) { - u32 stepping; + struct southbridge_amd_pi_hudson_config *sd_chip = dev->chip_info; + u32 stepping = pci_read_config32(pcidev_on_root(0x18, 3), 0xFC); + u8 sd_mode = 0; - stepping = pci_read_config32(pcidev_on_root(0x18, 3), 0xFC); + if (sd_chip) + sd_mode = sd_chip->sd_mode; - struct southbridge_amd_pi_hudson_config *sd_chip = - (struct southbridge_amd_pi_hudson_config *)(dev->chip_info); - - if (sd_chip->sd_mode == 3) { /* SD 3.0 mode */ + if (sd_mode == 3) { /* SD 3.0 mode */ pci_write_config32(dev, 0xA4, 0x31FEC8B2); pci_write_config32(dev, 0xA8, 0x00002503); pci_write_config32(dev, 0xB0, 0x02180C19); -- To view, visit https://review.coreboot.org/c/coreboot/+/34996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I123db3a51a8f354359e8ed5040d23111ea4eb8a4 Gerrit-Change-Number: 34996 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake/vr_config: Add loadline defaults
by Patrick Rudolph (Code Review) 20 Aug '19

20 Aug '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34938 ) Change subject: soc/intel/skylake/vr_config: Add loadline defaults ...................................................................... soc/intel/skylake/vr_config: Add loadline defaults In addition to zero IccMax specified by mainboard with socketed CPU, allow a zero LoadLine default. The SoC code will fill in the default AC/DC LoadLine values are per datasheets: * "7th Generation Intel® Processor Families for H Platforms, Vol 2" Document Number: 335191-002 * "7th Generation Intel® Processor Families for S Platforms and Intel ®Core™ X-Series Processor Family, Vol 2" Document Number: 335196-003 The AC/DC LoadLine is CPU and board specific. TODO: Find out how to get the LoadLine from vendor firmware and find out how to map those to different CPU LoadLines. Change-Id: I849845ced094697e8700470b4af95ad0afb98e3e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/skylake/include/soc/vr_config.h M src/soc/intel/skylake/vr_config.c 2 files changed, 84 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/34938/1 diff --git a/src/soc/intel/skylake/include/soc/vr_config.h b/src/soc/intel/skylake/include/soc/vr_config.h index 465e248..aebbbdf 100644 --- a/src/soc/intel/skylake/include/soc/vr_config.h +++ b/src/soc/intel/skylake/include/soc/vr_config.h @@ -68,6 +68,7 @@ }; #define VR_CFG_AMP(i) ((i) * 4) +#define VR_CFG_MOHMS(i) (uint16_t)((i) * 100) #if CONFIG(PLATFORM_USES_FSP1_1) /* VrConfig Settings for 5 domains diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index 33ce54a..089dd5d 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -220,6 +220,81 @@ return 0; } +#if CONFIG(PLATFORM_USES_FSP2_0) +static uint16_t get_sku_ac_dc_loadline(const int domain) +{ + static uint16_t mch_id = 0, igd_id = 0; + if (!mch_id) { + struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); + mch_id = pci_read_config16(dev, PCI_DEVICE_ID); + } + if (!igd_id) { + struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); + if (dev) + igd_id = pci_read_config16(dev, PCI_DEVICE_ID); + else + igd_id = 0xffff; + } + + switch (mch_id) { + case PCI_DEVICE_ID_INTEL_KBL_ID_S: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_KBL_ID_DT: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_KBL_ID_DT_2: { + static const uint16_t loadline[NUM_VR_DOMAINS] = { + VR_CFG_MOHMS(0), /* Not specified */ + VR_CFG_MOHMS(2.1), + VR_CFG_MOHMS(3.1), + VR_CFG_MOHMS(3.1), + }; + + return loadline[domain]; + } + case PCI_DEVICE_ID_INTEL_KBL_ID_H: { + static const uint16_t loadline[NUM_VR_DOMAINS] = { + VR_CFG_MOHMS(10), + VR_CFG_MOHMS(1.8), + VR_CFG_MOHMS(2.65), + VR_CFG_MOHMS(2.65), + }; + + return loadline[domain]; + } + case PCI_DEVICE_ID_INTEL_KBL_ID_Y: { + uint16_t loadline[NUM_VR_DOMAINS] = { + VR_CFG_MOHMS(18), + VR_CFG_MOHMS(5.9), + VR_CFG_MOHMS(5.7), + VR_CFG_MOHMS(5.7), + }; + + if (igd_id == PCI_DEVICE_ID_INTEL_AML_GT2_ULX) + loadline[VR_IA_CORE] = VR_CFG_MOHMS(4); + + return loadline[domain]; + } + case PCI_DEVICE_ID_INTEL_KBL_U_R: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_KBL_ID_U: { + uint16_t loadline[NUM_VR_DOMAINS] = { + VR_CFG_MOHMS(10.3), + VR_CFG_MOHMS(2.4), + VR_CFG_MOHMS(3.1), + VR_CFG_MOHMS(3.1), + }; + + if (igd_id == PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM_HDCP22) { + loadline[VR_GT_UNSLICED] = VR_CFG_MOHMS(6); + loadline[VR_GT_SLICED] = VR_CFG_MOHMS(6); + } + + return loadline[domain]; + } + default: + printk(BIOS_ERR, "ERROR: Unknown MCH in VR-config\n"); + } + return 0; +} +#endif + void fill_vr_domain_config(void *params, int domain, const struct vr_config *chip_cfg) { @@ -251,7 +326,13 @@ vr_params->VrVoltageLimit[domain] = cfg->voltage_limit; #if CONFIG(PLATFORM_USES_FSP2_0) - vr_params->AcLoadline[domain] = cfg->ac_loadline; - vr_params->DcLoadline[domain] = cfg->dc_loadline; + if (cfg->ac_loadline) + vr_params->AcLoadline[domain] = cfg->ac_loadline; + else + vr_params->AcLoadline[domain] = get_sku_ac_dc_loadline(domain); + if (cfg->dc_loadline) + vr_params->DcLoadline[domain] = cfg->dc_loadline; + else + vr_params->DcLoadline[domain] = get_sku_ac_dc_loadline(domain); #endif } -- To view, visit https://review.coreboot.org/c/coreboot/+/34938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I849845ced094697e8700470b4af95ad0afb98e3e Gerrit-Change-Number: 34938 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: AGESA,binaryPI: Replace use of __PRE_RAM__
by Kyösti Mälkki (Code Review) 20 Aug '19

20 Aug '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34997 ) Change subject: AGESA,binaryPI: Replace use of __PRE_RAM__ ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/c/coreboot/+/34997/1/src/southbridge/amd/agesa/… File src/southbridge/amd/agesa/hudson/hudson.h: https://review.coreboot.org/c/coreboot/+/34997/1/src/southbridge/amd/agesa/… PS1, Line 63: > ugh, this file! Ack https://review.coreboot.org/c/coreboot/+/34997/1/src/southbridge/amd/cimx/s… File src/southbridge/amd/cimx/sb800/fan.h: https://review.coreboot.org/c/coreboot/+/34997/1/src/southbridge/amd/cimx/s… PS1, Line 19: #include <device/device.h> > Two lines below want struct device, although anonymous. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/34997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id878fd33ec3d2de640d9a488058a805be3ccd223 Gerrit-Change-Number: 34997 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 20 Aug 2019 11:05:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Comment-In-Reply-To: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake/vr_config: Add support for KBL-H and KBL-S
by Philipp Deppenwiese (Code Review) 20 Aug '19

20 Aug '19

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34937 ) Change subject: soc/intel/skylake/vr_config: Add support for KBL-H and KBL-S ...................................................................... soc/intel/skylake/vr_config: Add support for KBL-H and KBL-S Datasheets used: * "7th Generation Intel® Processor Families for H Platforms, Vol 1" Document Number: 335190-003 * "7th Generation Intel® Processor Families for S Platforms and Intel ®Core™ X-Series Processor Family, Vol 1" Document Number: 335195-003 This allows mainboards to specify a zero IccMax, which all mainboards with socketed CPU should do. Change-Id: I303c5dc8ed03e9a98a834a2acfb400022dfc2fde Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34937 Reviewed-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/skylake/vr_config.c 1 file changed, 74 insertions(+), 16 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved Maxim Polyakov: Looks good to me, approved diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index 5f7de44..33ce54a 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -20,6 +20,7 @@ #include <soc/ramstage.h> #include <soc/vr_config.h> #include <console/console.h> +#include <intelblocks/cpulib.h> /* Default values for domain configuration. PSI3 and PSI4 are disabled. */ static const struct vr_config default_configs[NUM_VR_DOMAINS] = { @@ -89,6 +90,8 @@ static uint16_t get_sku_icc_max(int domain) { + const uint16_t tdp = cpu_get_power_max(); + static uint16_t mch_id = 0, igd_id = 0, lpc_id = 0; if (!mch_id) { struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); @@ -96,7 +99,10 @@ } if (!igd_id) { struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); - igd_id = pci_read_config16(dev, PCI_DEVICE_ID); + if (dev) + igd_id = pci_read_config16(dev, PCI_DEVICE_ID); + else + igd_id = 0xffff; } if (!lpc_id) { struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); @@ -104,23 +110,75 @@ } /* - * Iccmax table from Doc #559100 Section 7.2 DC Specifications, the - * Iccmax is the same among KBL-Y but KBL-U/R. - * Addendum for AML-Y #594883, IccMax for IA core is 28A. - * +----------------+-------------+---------------+------+-----+ - * | Domain/Setting | SA | IA | GTUS | GTS | - * +----------------+-------------+---------------+------+-----+ - * | IccMax(KBL-U/R)| 6A(U42) | 64A(U42) | 31A | 31A | - * | | 4.5A(Others)| 29A(P/C) loadline| | | - * | | | 32A(i3/i5) | | | - * +----------------+-------------+---------------+------+-----+ - * | IccMax(KBL-Y) | 4.1A | 24A | 24A | 24A | - * +----------------+-------------+---------------+------+-----+ - * | IccMax(AML-Y) | 4.1A | 28A | 24A | 24A | - * +----------------+-------------+---------------+------+-----+ - */ + * Iccmax table from Doc #559100 Section 7.2 DC Specifications, the + * Iccmax is the same among KBL-Y but KBL-U/R. + * Addendum for AML-Y #594883, IccMax for IA core is 28A. + * KBL-S #335195, KBL-H #335190 + * +----------------+-------------+---------------+------+-----+ + * | Domain/Setting | SA | IA | GTUS | GTS | + * +----------------+-------------+---------------+------+-----+ + * | IccMax(KBL-S) | 11.1A | 100A | 45A | 45A | + * | | | ... | | | + * | | | 40A | | | + * +----------------+-------------+---------------+------+-----+ + * | IccMax(KBL-H) | 11.1A(45W) | 68A | 55A | 55A | + * | | 6.6A(Others)| 60A | | | + * +----------------+-------------+---------------+------+-----+ + * | IccMax(KBL-U/R)| 6A(U42) | 64A(U42) | 31A | 31A | + * | | 4.5A(Others)| 29A(P/C) | | | + * | | | 32A(i3/i5) | | | + * +----------------+-------------+---------------+------+-----+ + * | IccMax(KBL-Y) | 4.1A | 24A | 24A | 24A | + * +----------------+-------------+---------------+------+-----+ + * | IccMax(AML-Y) | 4.1A | 28A | 24A | 24A | + * +----------------+-------------+---------------+------+-----+ + */ switch (mch_id) { + case PCI_DEVICE_ID_INTEL_KBL_ID_S: { + uint16_t icc_max[NUM_VR_DOMAINS] = { + VR_CFG_AMP(11.1), + VR_CFG_AMP(40), + VR_CFG_AMP(45), + VR_CFG_AMP(45), + }; + if (tdp >= 54) + icc_max[VR_IA_CORE] = VR_CFG_AMP(58); + else if (tdp >= 51) + icc_max[VR_IA_CORE] = VR_CFG_AMP(45); + + return icc_max[domain]; + + } + case PCI_DEVICE_ID_INTEL_KBL_ID_DT_2: /* fallthrough */ + case PCI_DEVICE_ID_INTEL_KBL_ID_DT: { + uint16_t icc_max[NUM_VR_DOMAINS] = { + VR_CFG_AMP(11.1), + VR_CFG_AMP(66), + VR_CFG_AMP(55), + VR_CFG_AMP(55), + }; + if (tdp >= 91) + icc_max[VR_IA_CORE] = VR_CFG_AMP(100); + else if (tdp >= 65) + icc_max[VR_IA_CORE] = VR_CFG_AMP(79); + + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_KBL_ID_H: { + uint16_t icc_max[NUM_VR_DOMAINS] = { + VR_CFG_AMP(6.6), + VR_CFG_AMP(60), + VR_CFG_AMP(55), + VR_CFG_AMP(55), + }; + if (tdp >= 45) { + icc_max[VR_SYSTEM_AGENT] = VR_CFG_AMP(11.1); + icc_max[VR_IA_CORE] = VR_CFG_AMP(68); + } + + return icc_max[domain]; + } case PCI_DEVICE_ID_INTEL_KBL_U_R: { static const uint16_t icc_max[NUM_VR_DOMAINS] = { VR_CFG_AMP(6), -- To view, visit https://review.coreboot.org/c/coreboot/+/34937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I303c5dc8ed03e9a98a834a2acfb400022dfc2fde Gerrit-Change-Number: 34937 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/skylake/vr_config: Add support for KBL-H and KBL-S
by Maxim Polyakov (Code Review) 20 Aug '19

20 Aug '19

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34937 ) Change subject: soc/intel/skylake/vr_config: Add support for KBL-H and KBL-S ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/34937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I303c5dc8ed03e9a98a834a2acfb400022dfc2fde Gerrit-Change-Number: 34937 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 20 Aug 2019 09:47:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake/vr_config: Add support for KBL-H and KBL-S
by Maxim Polyakov (Code Review) 20 Aug '19

20 Aug '19

Maxim Polyakov has uploaded a new patch set (#4) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/34937 ) Change subject: soc/intel/skylake/vr_config: Add support for KBL-H and KBL-S ...................................................................... soc/intel/skylake/vr_config: Add support for KBL-H and KBL-S Datasheets used: * "7th Generation Intel® Processor Families for H Platforms, Vol 1" Document Number: 335190-003 * "7th Generation Intel® Processor Families for S Platforms and Intel ®Core™ X-Series Processor Family, Vol 1" Document Number: 335195-003 This allows mainboards to specify a zero IccMax, which all mainboards with socketed CPU should do. Change-Id: I303c5dc8ed03e9a98a834a2acfb400022dfc2fde Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/skylake/vr_config.c 1 file changed, 74 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/34937/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/34937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I303c5dc8ed03e9a98a834a2acfb400022dfc2fde Gerrit-Change-Number: 34937 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skylake/vr_config: Add support for KBL-H and KBL-S
by Philipp Deppenwiese (Code Review) 20 Aug '19

20 Aug '19

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34937 ) Change subject: soc/intel/skylake/vr_config: Add support for KBL-H and KBL-S ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/34937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I303c5dc8ed03e9a98a834a2acfb400022dfc2fde Gerrit-Change-Number: 34937 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 20 Aug 2019 09:41:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake/vr_config: Get rid of static lookup table
by Philipp Deppenwiese (Code Review) 20 Aug '19

20 Aug '19

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34936 ) Change subject: soc/intel/skylake/vr_config: Get rid of static lookup table ...................................................................... soc/intel/skylake/vr_config: Get rid of static lookup table Use a switch case to find the correct VR config. The following commit will add more entries for which a lookup table isn't the best solution. Change-Id: Ib11c3d6e1eb339a0c7358c312a32731d835e7c73 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34936 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/skylake/vr_config.c 1 file changed, 73 insertions(+), 112 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, but someone else must approve Maxim Polyakov: Looks good to me, approved diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index 128ba59..5f7de44 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -19,76 +19,7 @@ #include <fsp/api.h> #include <soc/ramstage.h> #include <soc/vr_config.h> - -enum kbl_sku { - KBL_Y_SKU, - KBL_R_SKU, - KBL_U_BASE_SKU, - KBL_U_PREMIUM_SKU, - AML_Y_SKU, -}; - -/* - * Iccmax table from Doc #559100 Section 7.2 DC Specifications, the - * Iccmax is the same among KBL-Y but KBL-U/R. - * Addendum for AML-Y #594883, IccMax for IA core is 28A. - * +----------------+-------------+---------------+------+-----+ - * | Domain/Setting | SA | IA | GTUS | GTS | - * +----------------+-------------+---------------+------+-----+ - * | IccMax(KBL-U/R)| 6A(U42) | 64A(U42) | 31A | 31A | - * | | 4.5A(Others)| 29A(P/C) | | | - * | | | 32A(i3/i5) | | | - * +----------------+-------------+---------------+------+-----+ - * | IccMax(KBL-Y) | 4.1A | 24A | 24A | 24A | - * +----------------+-------------+---------------+------+-----+ - * | IccMax(AML-Y) | 4.1A | 28A | 24A | 24A | - * +----------------+-------------+---------------+------+-----+ - */ - -static const struct { - uint16_t icc_max[NUM_VR_DOMAINS]; -}sku_icc_max_mapping[] = { - [KBL_Y_SKU] = { - .icc_max = { - VR_CFG_AMP(4.1), - VR_CFG_AMP(24), - VR_CFG_AMP(24), - VR_CFG_AMP(24), - } - }, - [KBL_R_SKU] = { - .icc_max = { - VR_CFG_AMP(6), - VR_CFG_AMP(64), - VR_CFG_AMP(31), - VR_CFG_AMP(31), - } - }, - [KBL_U_BASE_SKU] = { - .icc_max = { - VR_CFG_AMP(4.5), - VR_CFG_AMP(29), - VR_CFG_AMP(31), - VR_CFG_AMP(31), - } - }, - [KBL_U_PREMIUM_SKU] = { - .icc_max = { - VR_CFG_AMP(4.5), - VR_CFG_AMP(32), - VR_CFG_AMP(31), - VR_CFG_AMP(31), - } - }, - [AML_Y_SKU] = { - .icc_max = { - VR_CFG_AMP(4.1), - VR_CFG_AMP(28), - VR_CFG_AMP(24), - VR_CFG_AMP(24), - } - }, -}; +#include <console/console.h> /* Default values for domain configuration. PSI3 and PSI4 are disabled. */ static const struct vr_config default_configs[NUM_VR_DOMAINS] = { @@ -156,53 +87,79 @@ }, }; -static uint16_t get_dev_id(struct device *dev) +static uint16_t get_sku_icc_max(int domain) { - return pci_read_config16(dev, PCI_DEVICE_ID); -} + static uint16_t mch_id = 0, igd_id = 0, lpc_id = 0; + if (!mch_id) { + struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); + mch_id = pci_read_config16(dev, PCI_DEVICE_ID); + } + if (!igd_id) { + struct device *dev = pcidev_path_on_root(SA_DEVFN_IGD); + igd_id = pci_read_config16(dev, PCI_DEVICE_ID); + } + if (!lpc_id) { + struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC); + lpc_id = pci_read_config16(dev, PCI_DEVICE_ID); + } -static int get_kbl_sku(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - static int sku = -1; - uint16_t id; + /* + * Iccmax table from Doc #559100 Section 7.2 DC Specifications, the + * Iccmax is the same among KBL-Y but KBL-U/R. + * Addendum for AML-Y #594883, IccMax for IA core is 28A. + * +----------------+-------------+---------------+------+-----+ + * | Domain/Setting | SA | IA | GTUS | GTS | + * +----------------+-------------+---------------+------+-----+ + * | IccMax(KBL-U/R)| 6A(U42) | 64A(U42) | 31A | 31A | + * | | 4.5A(Others)| 29A(P/C) loadline| | | + * | | | 32A(i3/i5) | | | + * +----------------+-------------+---------------+------+-----+ + * | IccMax(KBL-Y) | 4.1A | 24A | 24A | 24A | + * +----------------+-------------+---------------+------+-----+ + * | IccMax(AML-Y) | 4.1A | 28A | 24A | 24A | + * +----------------+-------------+---------------+------+-----+ + */ - if (sku != -1) - return sku; + switch (mch_id) { + case PCI_DEVICE_ID_INTEL_KBL_U_R: { + static const uint16_t icc_max[NUM_VR_DOMAINS] = { + VR_CFG_AMP(6), + VR_CFG_AMP(64), + VR_CFG_AMP(31), + VR_CFG_AMP(31), + }; + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_KBL_ID_Y: { + uint16_t icc_max[NUM_VR_DOMAINS] = { + VR_CFG_AMP(4.1), + VR_CFG_AMP(24), + VR_CFG_AMP(24), + VR_CFG_AMP(24), + }; - id = get_dev_id(sa_dev); - if (id == PCI_DEVICE_ID_INTEL_KBL_U_R) - sku = KBL_R_SKU; - else if (id == PCI_DEVICE_ID_INTEL_KBL_ID_Y) { - struct device *igd_dev = pcidev_path_on_root(SA_DEVFN_IGD); - id = get_dev_id(igd_dev); - if (id == PCI_DEVICE_ID_INTEL_AML_GT2_ULX) - sku = AML_Y_SKU; - else - sku = KBL_Y_SKU; - } else if (id == PCI_DEVICE_ID_INTEL_KBL_ID_U) { - id = get_dev_id(PCH_DEV_LPC); - if (id == PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE_HDCP22) - sku = KBL_U_BASE_SKU; - else - sku = KBL_U_PREMIUM_SKU; - } else - /* Not one of the skus with available Icc max mapping. */ - sku = -2; - return sku; -} + if (igd_id == PCI_DEVICE_ID_INTEL_AML_GT2_ULX) + icc_max[VR_IA_CORE] = VR_CFG_AMP(28); -static uint16_t get_sku_icc_max(int domain, uint16_t board_icc_max) -{ - /* If board provided non-zero value, use it. */ - if (board_icc_max) - return board_icc_max; + return icc_max[domain]; + } + case PCI_DEVICE_ID_INTEL_KBL_ID_U: { + uint16_t icc_max[NUM_VR_DOMAINS] = { + VR_CFG_AMP(4.5), + VR_CFG_AMP(32), + VR_CFG_AMP(31), + VR_CFG_AMP(31), + }; - /* Check if this SKU has a mapping table entry. */ - int sku_id = get_kbl_sku(); - if (sku_id < 0) - return 0; - return sku_icc_max_mapping[sku_id].icc_max[domain]; + if (igd_id == PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE_HDCP22) + icc_max[VR_IA_CORE] = VR_CFG_AMP(29); + + return icc_max[domain]; + } + default: + printk(BIOS_ERR, "ERROR: Unknown MCH in VR-config\n"); + } + return 0; } void fill_vr_domain_config(void *params, @@ -228,7 +185,11 @@ vr_params->Psi4Enable[domain] = cfg->psi4enable; vr_params->ImonSlope[domain] = cfg->imon_slope; vr_params->ImonOffset[domain] = cfg->imon_offset; - vr_params->IccMax[domain] = get_sku_icc_max(domain, cfg->icc_max); + /* If board provided non-zero value, use it. */ + if (cfg->icc_max) + vr_params->IccMax[domain] = cfg->icc_max; + else + vr_params->IccMax[domain] = get_sku_icc_max(domain); vr_params->VrVoltageLimit[domain] = cfg->voltage_limit; #if CONFIG(PLATFORM_USES_FSP2_0) -- To view, visit https://review.coreboot.org/c/coreboot/+/34936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib11c3d6e1eb339a0c7358c312a32731d835e7c73 Gerrit-Change-Number: 34936 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/skylake/vr_config: Get rid of defines
by Patrick Rudolph (Code Review) 20 Aug '19

20 Aug '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34935 ) Change subject: soc/intel/skylake/vr_config: Get rid of defines ...................................................................... soc/intel/skylake/vr_config: Get rid of defines Get rid of defines and hardcode values directly. Just a cosmetic cleanup to make it more readable. Change-Id: I3eec44b38af356c3d87235740c65e2c2f6fc5876 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/skylake/vr_config.c 1 file changed, 20 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/34935/1 diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index c83e18d..128ba59 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -20,17 +20,6 @@ #include <soc/ramstage.h> #include <soc/vr_config.h> -#define KBLY_ICCMAX_SA VR_CFG_AMP(4.1) -#define KBLY_ICCMAX_CORE VR_CFG_AMP(24) -#define AMLY_ICCMAX_CORE VR_CFG_AMP(28) -#define KBLY_ICCMAX_GTS_GTUS VR_CFG_AMP(24) -#define KBLR_ICCMAX_SA_U42 VR_CFG_AMP(6) -#define KBLU_ICCMAX_SA_U22 VR_CFG_AMP(4.5) -#define KBLR_ICCMAX_CORE_U42 VR_CFG_AMP(64) -#define KBLU_ICCMAX_CORE_U22_PREMIUM VR_CFG_AMP(32) -#define KBLU_ICCMAX_CORE_U22_BASE VR_CFG_AMP(29) -#define KBLUR_ICCMAX_GTS_GTUS VR_CFG_AMP(31) - enum kbl_sku { KBL_Y_SKU, KBL_R_SKU, @@ -61,42 +50,42 @@ }sku_icc_max_mapping[] = { [KBL_Y_SKU] = { .icc_max = { - KBLY_ICCMAX_SA, - KBLY_ICCMAX_CORE, - KBLY_ICCMAX_GTS_GTUS, - KBLY_ICCMAX_GTS_GTUS + VR_CFG_AMP(4.1), + VR_CFG_AMP(24), + VR_CFG_AMP(24), + VR_CFG_AMP(24), } }, [KBL_R_SKU] = { .icc_max = { - KBLR_ICCMAX_SA_U42, - KBLR_ICCMAX_CORE_U42, - KBLUR_ICCMAX_GTS_GTUS, - KBLUR_ICCMAX_GTS_GTUS + VR_CFG_AMP(6), + VR_CFG_AMP(64), + VR_CFG_AMP(31), + VR_CFG_AMP(31), } }, [KBL_U_BASE_SKU] = { .icc_max = { - KBLU_ICCMAX_SA_U22, - KBLU_ICCMAX_CORE_U22_BASE, - KBLUR_ICCMAX_GTS_GTUS, - KBLUR_ICCMAX_GTS_GTUS + VR_CFG_AMP(4.5), + VR_CFG_AMP(29), + VR_CFG_AMP(31), + VR_CFG_AMP(31), } }, [KBL_U_PREMIUM_SKU] = { .icc_max = { - KBLU_ICCMAX_SA_U22, - KBLU_ICCMAX_CORE_U22_PREMIUM, - KBLUR_ICCMAX_GTS_GTUS, - KBLUR_ICCMAX_GTS_GTUS + VR_CFG_AMP(4.5), + VR_CFG_AMP(32), + VR_CFG_AMP(31), + VR_CFG_AMP(31), } }, [AML_Y_SKU] = { .icc_max = { - KBLY_ICCMAX_SA, - AMLY_ICCMAX_CORE, - KBLY_ICCMAX_GTS_GTUS, - KBLY_ICCMAX_GTS_GTUS + VR_CFG_AMP(4.1), + VR_CFG_AMP(28), + VR_CFG_AMP(24), + VR_CFG_AMP(24), } }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/34935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3eec44b38af356c3d87235740c65e2c2f6fc5876 Gerrit-Change-Number: 34935 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lenovo/pmh7: Remove use of #ifndef __PRE_RAM__
by Kyösti Mälkki (Code Review) 20 Aug '19

20 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34923 ) Change subject: lenovo/pmh7: Remove use of #ifndef __PRE_RAM__ ...................................................................... lenovo/pmh7: Remove use of #ifndef __PRE_RAM__ Change-Id: Ib74c5c8cb9197fa06b2972cb96337fedd7f85b5b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/ec/lenovo/pmh7/pmh7.c 1 file changed, 1 insertion(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/34923/1 diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index 30de6fe..9dd668f 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -115,11 +115,9 @@ outb(val, EC_LENOVO_PMH7_DATA); } -#ifndef __PRE_RAM__ -#ifndef __SMM__ static void enable_dev(struct device *dev) { - struct ec_lenovo_pmh7_config *conf = dev->chip_info; + const struct ec_lenovo_pmh7_config *conf = dev->chip_info; struct resource *resource; u8 val; @@ -150,5 +148,3 @@ CHIP_NAME("Lenovo Power Management Hardware Hub 7") .enable_dev = enable_dev, }; -#endif -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/34923 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib74c5c8cb9197fa06b2972cb96337fedd7f85b5b Gerrit-Change-Number: 34923 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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