coreboot-gerrit August 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: arch/x86: Add <arch/romstage.h>
by HAOUAS Elyes (Code Review) 19 Aug '19

19 Aug '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34911 ) Change subject: arch/x86: Add <arch/romstage.h> ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/34911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9aeef07f9009e44cc08927c85fe1862edf5c70dc Gerrit-Change-Number: 34911 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Aug 2019 13:57:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake/vr_config: Get rid of static lookup table
by Maxim Polyakov (Code Review) 19 Aug '19

19 Aug '19

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34936 ) Change subject: soc/intel/skylake/vr_config: Get rid of static lookup table ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/34936 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib11c3d6e1eb339a0c7358c312a32731d835e7c73 Gerrit-Change-Number: 34936 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Aug 2019 13:51:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake/vr_config: Add support for KBL-H and KBL-S
by Maxim Polyakov (Code Review) 19 Aug '19

19 Aug '19

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34937 ) Change subject: soc/intel/skylake/vr_config: Add support for KBL-H and KBL-S ...................................................................... Patch Set 1: Code-Review+1 (1 comment) The code looks good to me. This works well on an asrock-h110m board, even with "stress --cpu 4" utility. https://review.coreboot.org/c/coreboot/+/34937/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/34937/1//COMMIT_MSG@10 PS1, Line 10: Vol 2 I see the Iccmax values in the Vol 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/34937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I303c5dc8ed03e9a98a834a2acfb400022dfc2fde Gerrit-Change-Number: 34937 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Aug 2019 13:50:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: AGESA,binaryPI: Replace use of __PRE_RAM__
by build bot (Jenkins) (Code Review) 19 Aug '19

19 Aug '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34997 ) Change subject: AGESA,binaryPI: Replace use of __PRE_RAM__ ...................................................................... Patch Set 1: (3 comments) https://review.coreboot.org/c/coreboot/+/34997/1/src/drivers/amd/agesa/def_… File src/drivers/amd/agesa/def_callouts.c: https://review.coreboot.org/c/coreboot/+/34997/1/src/drivers/amd/agesa/def_… PS1, Line 166: return AmdMemoryReadSPD (Func, Data, ConfigPtr); space prohibited between function name and open parenthesis '(' https://review.coreboot.org/c/coreboot/+/34997/1/src/southbridge/amd/cimx/s… File src/southbridge/amd/cimx/sb900/cfg.c: https://review.coreboot.org/c/coreboot/+/34997/1/src/southbridge/amd/cimx/s… PS1, Line 247: if (ENV_RAMSTAGE && !sb_config->StdHeader.CALLBACK.CalloutPtr) { braces {} are not necessary for single statement blocks https://review.coreboot.org/c/coreboot/+/34997/1/src/southbridge/amd/cimx/s… PS1, Line 252: printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - End.\n"); Prefer using '"%s...", __func__' to using 'sb900_cimx_config', this function's name, in a string -- To view, visit https://review.coreboot.org/c/coreboot/+/34997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id878fd33ec3d2de640d9a488058a805be3ccd223 Gerrit-Change-Number: 34997 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 19 Aug 2019 12:13:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: util/superiotool: add IT8987 detection and register support
by Matt Parnell (Code Review) 19 Aug '19

19 Aug '19

Matt Parnell has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34888 ) Change subject: util/superiotool: add IT8987 detection and register support ...................................................................... util/superiotool: add IT8987 detection and register support Change-Id: I3674bc7035a28c4174a1bc1ee014c88e0ac96e8d --- M util/superiotool/ite.c 1 file changed, 163 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/34888/1 diff --git a/util/superiotool/ite.c b/util/superiotool/ite.c index 8f1e2ea..cb05019 100644 --- a/util/superiotool/ite.c +++ b/util/superiotool/ite.c @@ -219,7 +219,7 @@ {0x00,0x00,0x68,0x00,0x6c,0x01,0x03,EOT}}, {EOT}}}, {0x8513, "IT8513E/F/G", { - {EOT}}}, + {EOT}}}, {0x8516, "IT8516???", { {NOLDN, "Chip ID", {0x20,0x21, EOT}, @@ -1064,6 +1064,92 @@ {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,EOT}, {0x00,0x02,0xf8,0x03,0x00,0x50,0x00,EOT}}, {EOT}}}, + {0x8987, "IT8987", { + {NOLDN, "Chip ID", + {0x20,0x21, EOT}, + {0x89,0x87, EOT}}, + {NOLDN, "Chip Version", + {0x22,EOT}, + {0x03,EOT}}, + {NOLDN, "Super I/O Control Register (SIOCTRL)", + {0x23,EOT}, + {0x01,EOT}}, + {NOLDN, "Super I/O Configuration Register (SIOIRQ)", + {0x25,EOT}, + {0x00,EOT}}, + {NOLDN, "Super I/O General Purpose Register (SIOGP)", + {0x26,EOT}, + {0x00,EOT}}, + {NOLDN, "Super I/O Power Mode Register (SIOPWR)", + {0x2d,EOT}, + {0x00,EOT}}, + {NOLDN, "Depth 2 I/O Address (D2ADR)", + {0x2e,EOT}, + {0x00,EOT}}, + {NOLDN, "Depth 2 I/O Data (D2DAT)", + {0x2f,EOT}, + {0x00,EOT}}, + {NOLDN, "Logical Device Activate Register (LDA)", + {0x30,EOT}, + {0x00,EOT}}, + {NOLDN, "I/O Port Base Address for Descriptor 0 (IOBAD0)", + {0x60,0x61,EOT}, + {NANA,NANA,EOT}}, + {NOLDN, "I/O Port Base Address for Descriptor 1 (IOBAD1)", + {0x62,0x63,EOT}, + {NANA,NANA,EOT}}, + {NOLDN, "Interrupt Request Number and Wake-Up on IRQ Enable (IRQNUMX)", + {0x70,EOT}, + {NANA,EOT}}, + {NOLDN, "Interrupt Request Type Select (IRQTP)", + {0x71,EOT}, + {NANA,EOT}}, + {NOLDN, "DMA Channel Select 0 (DMAS0)", + {0x74,EOT}, + {0x04,EOT}}, + {NOLDN, "DMA Channel Select 1 (DMAS1)", + {0x75,EOT}, + {0x04,EOT}}, + {0x04, "System Wake-Up Control (SWUC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x01,EOT}}, + {0x05, "KBC/Mouse Interface", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x0c,0x01,EOT}}, + {0x06, "KBC/Keyboard Interface", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x60,0x00,0x64,0x01,0x01,EOT}}, + {0xa, "Consumer IR", + {0x30,0x60,0x61,0x70,0x71,EOT}, + {0x00,0x03,0x10,0x00,0x02,EOT}}, + {0x0f, "Shared Memory/Flash Interface (SMFI)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf4,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,NANA,EOT}}, + {0x10, "Real Time Clock (RTC)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,0xf0,0xf1,0xf2,EOT}, + {0x00,0x00,0x70,0x00,0x72,0x08,0x00,0x00,0x49,0x4a,EOT}}, + {0x11, "Power Management I/F Channel 1 (PMC1)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x62,0x00,0x66,0x01,0x01,EOT}}, + {0x12, "Power Management I/F Channel 2 (PMC2)", + {0x30,0x60,0x61,0x62,0x63,0x64,0x65,0x70,0x71,0xf0,EOT}, + {0x00,0x00,0x68,0x00,0x6c,0x00,0x00,0x01,0x01,NANA,EOT}}, + {0x13, "Serial Peripheral Interface (SSPI)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x03,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x14, "Platform Environment Control Interface (PECI)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x17, "Power Management I/F Channel 3 (PMC3)", + {0x30,0x60,0x61,0x62,0x63,0x70,0x71,EOT}, + {0x00,0x00,0x62,0x00,0x66,0x01,0x01,EOT}}, + {0x18, "Power Management I/F Channel 4 (PMC4)", + {0x30,0x60,0x61,0x62,0x63,0x64,0x65,0x70,0x71,0xf0,EOT}, + {0x00,0x00,0x68,0x00,0x6c,0x00,0x00,0x01,0x01,NANA,EOT}}, + {0x19, "Power Management I/F Channel 4 (PMC4)", + {0x30,0x60,0x61,0x62,0x63,0x64,0x65,0x70,0x71,0xf0,EOT}, + {0x00,0x00,0x68,0x00,0x6c,0x00,0x00,0x01,0x01,NANA,EOT}}, + {EOT}}}, {EOT} }; @@ -1280,6 +1366,68 @@ {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, {EOT}}}, +{0x8987, "IT8987", { + {NOLDN, NULL, + {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, + 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, + 0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27, + 0x28,0x29,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37, + 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x40,0x41,0x42,0x43,0x44,0x45,0x46,0x47, + 0x48,0x49,0x4a,0x4b,0x4c,0x4d,0x4e,0x4f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57, + 0x58,0x59,0x5a,0x5b,0x5c,0x5d,0x5e,0x5f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x60,0x61,0x62,0x63,0x64,0x65,0x66,0x67, + 0x68,0x69,0x6a,0x6b,0x6c,0x6d,0x6e,0x6f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x70,0x71,0x72,0x73,0x74,0x75,0x76,0x77, + 0x78,0x79,0x7a,0x7b,0x7c,0x7d,0x7e,0x7f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, + 0x88,0x89,0x8a,0x8b,0x8c,0x8d,0x8e,0x8f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97, + 0x98,0x99,0x9a,0x9b,0x9c,0x9d,0x9e,0x9f,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0xa0,0xa1,0xa2,0xa3,0xa4,0xa5,0xa6,0xa7, + 0xa8,0xa9,0xaa,0xab,0xac,0xad,0xae,0xaf,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {NOLDN, NULL, + {0xb0,0xb1,0xb2,0xb3,0xb4,0xb5,0xb6,0xb7, + 0xb8,0xb9,0xba,0xbb,0xbc,0xbd,0xbe,0xbf,EOT}, + {NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA, + NANA,NANA,NANA,NANA,NANA,NANA,NANA,NANA,EOT}}, + {EOT}}}, {EOT} }; @@ -1351,6 +1499,14 @@ OUTB((port == 0x2e) ? 0x55 : 0xaa, port); } +static void enter_conf_mode_ite_it8987e(uint16_t port) +{ + OUTB(0x89, port); + OUTB(0x87, port); + OUTB(0x55, port); + OUTB((port == 0x2e) ? 0x55 : 0xaa, port); +} + static void exit_conf_mode_ite(uint16_t port) { regwrite(port, 0x02, 0x02); @@ -1444,6 +1600,12 @@ if (chip_found_at_port) return; + enter_conf_mode_ite_it8987e(port); + probe_idregs_ite_helper("(init=it8987e) ", port); + exit_conf_mode_ite(port); + if (chip_found_at_port) + return; + enter_conf_mode_winbond_fintek_ite_8787(port); probe_idregs_ite_helper("(init=0x87,0x87) ", port); exit_conf_mode_winbond_fintek_ite_8787(port); -- To view, visit https://review.coreboot.org/c/coreboot/+/34888 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3674bc7035a28c4174a1bc1ee014c88e0ac96e8d Gerrit-Change-Number: 34888 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Parnell <mparnell(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/hatch/variants/helios: Update GPIO table for proto stage
by Frank Chu (Code Review) 19 Aug '19

19 Aug '19

Frank Chu has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/33826 ) Change subject: mb/google/hatch/variants/helios: Update GPIO table for proto stage ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/33826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I257a90a97e11651cdf5f85ca743e530ef5e61e56 Gerrit-Change-Number: 33826 Gerrit-PatchSet: 7 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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Change in coreboot[master]: mb/google/hatch/variants/helios: Update GPIO table for proto stage
by Frank Chu (Code Review) 19 Aug '19

19 Aug '19

Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33826 ) Change subject: mb/google/hatch/variants/helios: Update GPIO table for proto stage ...................................................................... Patch Set 7: CL duplicated, abandon this CL -- To view, visit https://review.coreboot.org/c/coreboot/+/33826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I257a90a97e11651cdf5f85ca743e530ef5e61e56 Gerrit-Change-Number: 33826 Gerrit-PatchSet: 7 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Philip Chen <philipchen(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 19 Aug 2019 08:49:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Add provision to skip postcar and load ramstage
by Subrata Banik (Code Review) 19 Aug '19

19 Aug '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34754 ) Change subject: soc/intel/cannonlake: Add provision to skip postcar and load ramstage ...................................................................... soc/intel/cannonlake: Add provision to skip postcar and load ramstage This patch adds required provision in soc code to pick ramstage directly from romstage and avoid postcar as intermediate stage for car tear down. Change-Id: I6f1d93ae0f8d957bf9c15e358bc13039a300c4ca Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/romstage/romstage.c 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/34754/1 diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index 94b9899..3aefb97 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -127,6 +127,23 @@ printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); } +#if !CONFIG(HAVE_POSTCAR) +/* + * Make sure we are enabling intermediate caching to speed up + * ramstage.elf loading and decompression as we are still in romstage + * and car tear down will be handled by ramstage at its entry. + */ +static void enable_ramstage_caching(uintptr_t base, size_t size) +{ + int mtrr = get_free_var_mtrr(); + + if (mtrr == -1) + return; + + set_var_mtrr(mtrr, base, size, MTRR_TYPE_WRPROT); +} +#endif + asmlinkage void car_stage_entry(void) { bool s3wake; @@ -164,5 +181,10 @@ /* Cache the ROM as WP just below 4GiB. */ postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT); +#if CONFIG(HAVE_POSTCAR) run_postcar_phase(&pcf); +#else + enable_ramstage_caching(top_of_ram, 16*MiB); + run_ramstage_phase(&pcf); +#endif } -- To view, visit https://review.coreboot.org/c/coreboot/+/34754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f1d93ae0f8d957bf9c15e358bc13039a300c4ca Gerrit-Change-Number: 34754 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
by Felix Held (Code Review) 19 Aug '19

19 Aug '19

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32734 ) Change subject: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF ...................................................................... Patch Set 70: (5 comments) https://review.coreboot.org/c/coreboot/+/32734/68/src/mainboard/supermicro/… File src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb: https://review.coreboot.org/c/coreboot/+/32734/68/src/mainboard/supermicro/… PS68, Line 74: Touch Pad > touch pad? this isn't a laptop. […] Done https://review.coreboot.org/c/coreboot/+/32734/68/src/mainboard/supermicro/… PS68, Line 95: M.2 WWAN > also likely incorrect comment Done https://review.coreboot.org/c/coreboot/+/32734/68/src/mainboard/supermicro/… PS68, Line 236: device pnp 2e.0 on > Yes, it will generate the container ACPI code please add a comment to this line to make clear what it does https://review.coreboot.org/c/coreboot/+/32734/68/src/mainboard/supermicro/… PS68, Line 265: 6 > at least that's what legacy machines used for that port. […] Done https://review.coreboot.org/c/coreboot/+/32734/68/src/mainboard/supermicro/… PS68, Line 269: 5 > IRQ 5 was used for the second and third parallel port and sound cards Done -- To view, visit https://review.coreboot.org/c/coreboot/+/32734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 Gerrit-Change-Number: 32734 Gerrit-PatchSet: 70 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Keno Fischer <keno(a)alumni.harvard.edu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Name of user not set #1002358 Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: T. Hudson <trammell.hudson(a)gmail.com> Gerrit-Reviewer: Trammell Hudson <hudson(a)trmm.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Michael Niewöhner Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 19 Aug 2019 03:55:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mediatek/mt8183: Use GPIO based CS for SPI0
by You-Cheng Syu (Code Review) 19 Aug '19

19 Aug '19

You-Cheng Syu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33166 Change subject: mediatek/mt8183: Use GPIO based CS for SPI0 ...................................................................... mediatek/mt8183: Use GPIO based CS for SPI0 Some boards (e.g., Kukui) needs GPIO based CS for SPI0. This CL changes the pinmux and binds the pin to SPI0. BUG=b:132311067 TEST=Verified that b/132311067 is irreproducible now. Change-Id: Id4248b3f146a1f1b44124f7a2671dbbc824eda01 --- M src/soc/mediatek/mt8183/spi.c 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/33166/1 diff --git a/src/soc/mediatek/mt8183/spi.c b/src/soc/mediatek/mt8183/spi.c index a79dafb..cb35c63 100644 --- a/src/soc/mediatek/mt8183/spi.c +++ b/src/soc/mediatek/mt8183/spi.c @@ -21,9 +21,12 @@ #include <soc/gpio.h> #include <soc/spi.h> +static gpio_t spi0_cs = GPIO(SPI_CSB); + struct mtk_spi_bus spi_bus[SPI_BUS_NUMBER] = { { .regs = (void *)SPI0_BASE, + .cs_gpio = &spi0_cs, }, { .regs = (void *)SPI1_BASE, @@ -52,7 +55,7 @@ static const struct pad_func pad0_funcs[SPI_BUS_NUMBER][4] = { { PAD_FUNC(SPI_MI, SPI0_MI), - PAD_FUNC(SPI_CSB, SPI0_CSB), + {PAD_SPI_CSB_ID, 0}, PAD_FUNC(SPI_MO, SPI0_MO), PAD_FUNC(SPI_CLK, SPI0_CLK), }, -- To view, visit https://review.coreboot.org/c/coreboot/+/33166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4248b3f146a1f1b44124f7a2671dbbc824eda01 Gerrit-Change-Number: 33166 Gerrit-PatchSet: 1 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-MessageType: newchange

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