coreboot-gerrit August 2019

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Change in coreboot[master]: emulation/qemu-x86: Fix romstage stack alignment
by Kyösti Mälkki (Code Review) 18 Aug '19

18 Aug '19

Hello Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/34975 to look at the new patch set (#3). Change subject: emulation/qemu-x86: Fix romstage stack alignment ...................................................................... emulation/qemu-x86: Fix romstage stack alignment Also tidy up some register usage. Change-Id: I5b4b4a29c854f4ca165cede4e9b6755a6c577e76 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/qemu-x86/cache_as_ram_bootblock.S 1 file changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/34975/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/34975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b4b4a29c854f4ca165cede4e9b6755a6c577e76 Gerrit-Change-Number: 34975 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mainboards: Remove floating __PRE_RAM__ comments
by Kyösti Mälkki (Code Review) 18 Aug '19

18 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34920 ) Change subject: mainboards: Remove floating __PRE_RAM__ comments ...................................................................... mainboards: Remove floating __PRE_RAM__ comments Change-Id: I110e54175a81b6a651213e0f18ddc1e3e71160cf Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/t400/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/x200/romstage.c M src/mainboard/lenovo/x201/romstage.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/z61t/romstage.c M src/mainboard/packardbell/ms2290/romstage.c M src/mainboard/roda/rk886ex/romstage.c M src/mainboard/roda/rk9/romstage.c 15 files changed, 0 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/34920/1 diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 1c84c84..e96de6f 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -15,8 +15,6 @@ * GNU General Public License for more details. */ -/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ - #include <stdint.h> #include <cf9_reset.h> #include <device/pci_ops.h> diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index b076b9d..4e17d34 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -15,8 +15,6 @@ * GNU General Public License for more details. */ -// __PRE_RAM__ means: use "unsigned" for device, not a struct. - #include <stdint.h> #include <cf9_reset.h> #include <device/pnp_ops.h> diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c index 2c7800f..bdb0a38 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -// __PRE_RAM__ means: use "unsigned" for device, not a struct. - #include <stdint.h> #include <device/pci_ops.h> #include <device/pci_def.h> diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index c98556c..ab8282c 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -13,8 +13,6 @@ * GNU General Public License for more details. */ -// __PRE_RAM__ means: use "unsigned" for device, not a struct. - #include <stdint.h> #include <cf9_reset.h> #include <device/pnp_ops.h> diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 15a00cf..32b9a9f 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -13,8 +13,6 @@ * GNU General Public License for more details. */ -// __PRE_RAM__ means: use "unsigned" for device, not a struct. - #include <stdint.h> #include <device/pci_def.h> #include <device/pci_ops.h> diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index b51e4b4..c940536 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -13,8 +13,6 @@ * GNU General Public License for more details. */ -/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ - #include <stdint.h> #include <cf9_reset.h> #include <delay.h> diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 43d6088..1b76318 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -// __PRE_RAM__ means: use "unsigned" for device, not a struct. - #include <device/pci_ops.h> #include <console/console.h> #include <southbridge/intel/i82801ix/i82801ix.h> diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index cfe2d23..2817023 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -15,8 +15,6 @@ * GNU General Public License for more details. */ -// __PRE_RAM__ means: use "unsigned" for device, not a struct. - #include <stdint.h> #include <cf9_reset.h> #include <delay.h> diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index afaa9aa..4382bc0 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -// __PRE_RAM__ means: use "unsigned" for device, not a struct. - #include <device/pci_ops.h> #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/i82801ix/i82801ix.h> diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index ae154e2..73f5bcc 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -16,8 +16,6 @@ * GNU General Public License for more details. */ -/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ - #include <stdint.h> #include <arch/io.h> #include <device/pci_ops.h> diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index fc0c678..590e786 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -15,8 +15,6 @@ * GNU General Public License for more details. */ -// __PRE_RAM__ means: use "unsigned" for device, not a struct. - #include <stdint.h> #include <cf9_reset.h> #include <delay.h> diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index c31301e..4c487c0 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -15,8 +15,6 @@ * GNU General Public License for more details. */ -// __PRE_RAM__ means: use "unsigned" for device, not a struct. - #include <stdint.h> #include <cf9_reset.h> #include <delay.h> diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 0ab5544..e2c5133 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -16,8 +16,6 @@ * GNU General Public License for more details. */ -/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ - #include <stdint.h> #include <arch/io.h> #include <device/pci_ops.h> diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index efd739c..02ee004 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ - #include <stdint.h> #include <arch/io.h> #include <cf9_reset.h> diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index eaddaf9..497828b 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -14,8 +14,6 @@ * GNU General Public License for more details. */ -/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ - #include <arch/io.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/34920 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I110e54175a81b6a651213e0f18ddc1e3e71160cf Gerrit-Change-Number: 34920 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: emulation/qemu-x86: Fix romstage stack alignment
by Arthur Heymans (Code Review) 18 Aug '19

18 Aug '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34975 ) Change subject: emulation/qemu-x86: Fix romstage stack alignment ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/34975/2/src/cpu/qemu-x86/cache_as_… File src/cpu/qemu-x86/cache_as_ram_bootblock.S: https://review.coreboot.org/c/coreboot/+/34975/2/src/cpu/qemu-x86/cache_as_… PS2, Line 41: tab? -- To view, visit https://review.coreboot.org/c/coreboot/+/34975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b4b4a29c854f4ca165cede4e9b6755a6c577e76 Gerrit-Change-Number: 34975 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sun, 18 Aug 2019 08:40:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: amdfam10-15: Rename DCACHE_BSP_STACK_SIZE
by Kyösti Mälkki (Code Review) 18 Aug '19

18 Aug '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34880 ) Change subject: amdfam10-15: Rename DCACHE_BSP_STACK_SIZE ...................................................................... amdfam10-15: Rename DCACHE_BSP_STACK_SIZE The original name DCACHE_BSP_STACK_SIZE will be exclusively used to define the fixed size of BSP stack when it is located near the beginning of CAR region. This implementation has the stack located at the very end of CAR region. Remove other fam10-15 exclusive configs from global space. Change-Id: I8b92891be2ed62944a9eddde39ed20a12f4875c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/Kconfig M src/cpu/amd/car/cache_as_ram.inc M src/cpu/amd/car/post_cache_as_ram.c M src/cpu/amd/family_10h-family_15h/Kconfig M src/cpu/amd/family_10h-family_15h/init_cpus.c 5 files changed, 19 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/34880/1 diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 69ceb64..3c0bf89 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -23,12 +23,6 @@ config DCACHE_BSP_STACK_SIZE hex -config DCACHE_BSP_STACK_SLUSH - hex - -config DCACHE_AP_STACK_SIZE - hex - config SMP bool default y if MAX_CPUS != 1 diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index f923a47..d923377 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -22,8 +22,8 @@ #define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase CONFIG_DCACHE_RAM_BASE -#define CacheSizeBSPStack CONFIG_DCACHE_BSP_STACK_SIZE -#define CacheSizeBSPSlush CONFIG_DCACHE_BSP_STACK_SLUSH +#define CacheSizeBSPStack CONFIG_DCACHE_BSP_TOP_STACK_SIZE +#define CacheSizeBSPSlush CONFIG_DCACHE_BSP_TOP_STACK_SLUSH /* For CAR with Fam10h. */ #define CacheSizeAPStack CONFIG_DCACHE_AP_STACK_SIZE diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 50ed657..aa8222b 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -131,9 +131,9 @@ * boundary during romstage execution */ volatile uint32_t *lower_stack_boundary; - lower_stack_boundary = - (void *)((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - - CONFIG_DCACHE_BSP_STACK_SIZE); + lower_stack_boundary = (void *)((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - + CONFIG_DCACHE_BSP_TOP_STACK_SIZE); + if ((*lower_stack_boundary) != 0xdeadbeef) printk(BIOS_WARNING, "BSP overran lower stack boundary. Undefined behaviour may result!\n"); diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig index 1039a8d..e9ee855 100644 --- a/src/cpu/amd/family_10h-family_15h/Kconfig +++ b/src/cpu/amd/family_10h-family_15h/Kconfig @@ -37,11 +37,11 @@ hex default 0x0c000 -config DCACHE_BSP_STACK_SIZE +config DCACHE_BSP_TOP_STACK_SIZE hex default 0x4000 -config DCACHE_BSP_STACK_SLUSH +config DCACHE_BSP_TOP_STACK_SLUSH hex default 0x4000 if USE_LARGE_DCACHE default 0x1000 diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index f416d9c..eebbc48 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -379,12 +379,19 @@ uint8_t fam15_bsp_core1_apicid; struct node_core_id id; - /* Please refer to the calculations and explaination in cache_as_ram.inc before modifying these values */ + /* Please refer to the calculations and explaination in cache_as_ram.inc + * before modifying these values */ uint32_t max_ap_stack_region_size = CONFIG_MAX_CPUS * CONFIG_DCACHE_AP_STACK_SIZE; - uint32_t max_bsp_stack_region_size = CONFIG_DCACHE_BSP_STACK_SIZE + CONFIG_DCACHE_BSP_STACK_SLUSH; - uint32_t bsp_stack_region_upper_boundary = CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE; - uint32_t bsp_stack_region_lower_boundary = bsp_stack_region_upper_boundary - max_bsp_stack_region_size; - void *lower_stack_region_boundary = (void *)(bsp_stack_region_lower_boundary - max_ap_stack_region_size); + uint32_t max_bsp_stack_region_size = CONFIG_DCACHE_BSP_TOP_STACK_SIZE + + CONFIG_DCACHE_BSP_TOP_STACK_SLUSH; + uint32_t bsp_stack_region_upper_boundary = CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE; + uint32_t bsp_stack_region_lower_boundary = bsp_stack_region_upper_boundary - + max_bsp_stack_region_size; + + void *lower_stack_region_boundary = (void *)(bsp_stack_region_lower_boundary - + max_ap_stack_region_size); + if (((void*)(sysinfo + 1)) > lower_stack_region_boundary) printk(BIOS_WARNING, "sysinfo extends into stack region (sysinfo range: [%p,%p] lower stack region boundary: %p)\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/34880 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b92891be2ed62944a9eddde39ed20a12f4875c0 Gerrit-Change-Number: 34880 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: emulation/qemu-x86: Fix romstage stack alignment
by Patrick Rudolph (Code Review) 18 Aug '19

18 Aug '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34975 ) Change subject: emulation/qemu-x86: Fix romstage stack alignment ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/34975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b4b4a29c854f4ca165cede4e9b6755a6c577e76 Gerrit-Change-Number: 34975 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 18 Aug 2019 07:54:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: Replace ENV_RAMSTAGE with ENV_PAYLOAD_LOADER
by Subrata Banik (Code Review) 17 Aug '19

17 Aug '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32725 Change subject: Replace ENV_RAMSTAGE with ENV_PAYLOAD_LOADER ...................................................................... Replace ENV_RAMSTAGE with ENV_PAYLOAD_LOADER This patch relying on new rule, ENV_PAYLOAD_LOADER which is set to ENV_RAMSTAGE. This approach will help to add future optimization (rampayload) in coreboot flow if required. Change-Id: Ib54ece7b9e5f281f8a092dc6f38c07406edfa5fa Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/include/arch/acpi.h M src/console/post.c M src/drivers/uart/uart8250io.c M src/drivers/uart/uart8250mem.c M src/include/memlayout.h M src/include/rules.h M src/include/stddef.h M src/lib/bootmode.c M src/lib/imd_cbmem.c M src/lib/memrange.c M src/lib/prog_loaders.c M src/lib/program.ld M src/lib/timestamp.c M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/i2c/i2c.c 15 files changed, 27 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/32725/1 diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 79feaad..26fa5da 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -838,7 +838,7 @@ unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t *ivrs_struct, unsigned long current)); -#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) +#if ENV_PAYLOAD_LOADER && !defined(__SIMPLE_DEVICE__) void acpi_create_hpet(acpi_hpet_t *hpet); unsigned long acpi_write_hpet(struct device *device, unsigned long start, acpi_rsdp_t *rsdp); diff --git a/src/console/post.c b/src/console/post.c index 236aa8c..dd39aad 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -44,7 +44,7 @@ DECLARE_SPIN_LOCK(cmos_post_lock) -#if ENV_RAMSTAGE +#if ENV_PAYLOAD_LOADER void cmos_post_log(void) { u8 code = 0; @@ -125,7 +125,7 @@ post_log_extra(0); } #endif /* CONFIG_CMOS_POST_EXTRA */ -#endif /* ENV_RAMSTAGE */ +#endif /* ENV_PAYLOAD_LOADER */ static void cmos_post_code(u8 value) { diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index 62671e2..85c01a4 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -124,7 +124,7 @@ uart8250_tx_flush(uart_platform_base(idx)); } -#if ENV_RAMSTAGE +#if ENV_PAYLOAD_LOADER void uart_fill_lb(void *data) { struct lb_serial serial; diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index c3dff6a..bc9717e 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -147,7 +147,7 @@ uart8250_mem_tx_flush(base); } -#if ENV_RAMSTAGE +#if ENV_PAYLOAD_LOADER void uart_fill_lb(void *data) { struct lb_serial serial; diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 273a80d..1e6207f 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -41,7 +41,8 @@ /* Default is that currently ramstage, smm, and rmodules have a heap. */ #ifndef ARCH_STAGE_HAS_HEAP_SECTION -#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM || ENV_RMODULE) +#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_PAYLOAD_LOADER || ENV_SMM || \ + ENV_RMODULE) #endif #define STR(x) #x diff --git a/src/include/rules.h b/src/include/rules.h index ce968f0..801a7fe 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -272,7 +272,7 @@ * be built with simple device model. */ -#if (defined(__PRE_RAM__) || ENV_SMM || ENV_POSTCAR) +#if (defined(__PRE_RAM__) || ENV_SMM || !ENV_PAYLOAD_LOADER) #define __SIMPLE_DEVICE__ #endif diff --git a/src/include/stddef.h b/src/include/stddef.h index 993d5f0..cd29e31 100644 --- a/src/include/stddef.h +++ b/src/include/stddef.h @@ -21,9 +21,11 @@ #define NULL ((void *)0) -/* The devicetree data structures are only mutable in ramstage. All other - stages have a constant devicetree. */ -#if !ENV_RAMSTAGE +/* + * The devicetree data structures are only mutable in ENV_PAYLOAD_LOADER + * All other stages have a constant devicetree. + */ +#if !ENV_PAYLOAD_LOADER #define DEVTREE_EARLY 1 #else #define DEVTREE_EARLY 0 diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index 18f6d5d..93f317d 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -17,7 +17,7 @@ #include <bootmode.h> #include <vendorcode/google/chromeos/chromeos.h> -#if ENV_RAMSTAGE +#if ENV_PAYLOAD_LOADER static int gfx_init_done = -1; int gfx_get_init_done(void) diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index 1a67ad5..b1b63f6 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -307,7 +307,7 @@ imd_region_used(cbmem_get_imd(), baseptr, size); } -#if ENV_RAMSTAGE || (CONFIG(EARLY_CBMEM_LIST) \ +#if ENV_PAYLOAD_LOADER || (CONFIG(EARLY_CBMEM_LIST) \ && (ENV_POSTCAR || ENV_ROMSTAGE)) /* * -fdata-sections doesn't work so well on read only strings. They all diff --git a/src/lib/memrange.c b/src/lib/memrange.c index 96d7524..79a1b0e 100644 --- a/src/lib/memrange.c +++ b/src/lib/memrange.c @@ -47,7 +47,7 @@ range_entry_unlink(&ranges->free_list, r); return r; } - if (ENV_RAMSTAGE) + if (ENV_PAYLOAD_LOADER) return malloc(sizeof(struct range_entry)); return NULL; } diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 3b77712..b73a61a 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -165,7 +165,7 @@ die("Ramstage was not loaded!\n"); } -#ifdef __RAMSTAGE__ // gc-sections should take care of this +#if ENV_PAYLOAD_LOADER // gc-sections should take care of this static struct prog global_payload = PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/payload"); diff --git a/src/lib/program.ld b/src/lib/program.ld index 851aa75..66421d1 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -55,7 +55,7 @@ KEEP(*(.rsbe_init)); _ersbe_init_begin = .; -#if ENV_RAMSTAGE +#if ENV_PAYLOAD_LOADER . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _pci_drivers = .; KEEP(*(.rodata.pci_driver)); diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index b6330fa..cf882b8 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -48,7 +48,7 @@ #endif /* The cache location will sit in BSS when in ramstage. */ -#define TIMESTAMP_CACHE_IN_BSS ENV_RAMSTAGE +#define TIMESTAMP_CACHE_IN_BSS ENV_PAYLOAD_LOADER #define HAS_CBMEM (ENV_ROMSTAGE || ENV_RAMSTAGE || ENV_POSTCAR) @@ -113,8 +113,11 @@ * based x86 platforms. */ static int timestamp_should_run(void) { - /* Only check boot_cpu() in other stages than ramstage on x86. */ - if ((!ENV_RAMSTAGE && CONFIG(ARCH_X86)) && !boot_cpu()) + /* + * Only check boot_cpu() in other stages than + * ENV_PAYLOAD_LOADER on x86. + */ + if ((!ENV_PAYLOAD_LOADER && CONFIG(ARCH_X86)) && !boot_cpu()) return 0; return 1; @@ -300,7 +303,7 @@ ts_cbmem_table->base_time = ts_cache_table->base_time; /* Seed the timestamp tick frequency in ramstage. */ - if (ENV_RAMSTAGE) + if (ENV_PAYLOAD_LOADER) ts_cbmem_table->tick_freq_mhz = timestamp_tick_freq_mhz(); /* Cache no longer required. */ diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 455b13c..0628aae 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -250,7 +250,7 @@ bios_size = ALIGN_UP(bios_size, alignment); base = 4ULL*GiB - bios_size; - if (ENV_RAMSTAGE) { + if (ENV_PAYLOAD_LOADER) { mtrr_use_temp_range(base, bios_size, type); } else { int mtrr = get_free_var_mtrr(); diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index a99dfea..d551c51 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -47,7 +47,7 @@ return EARLY_I2C_BASE(bus); } -#if !ENV_RAMSTAGE +#if !ENV_PAYLOAD_LOADER static int lpss_i2c_early_init_bus(unsigned int bus) { const struct dw_i2c_bus_config *config; -- To view, visit https://review.coreboot.org/c/coreboot/+/32725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib54ece7b9e5f281f8a092dc6f38c07406edfa5fa Gerrit-Change-Number: 32725 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

4 36

Change in coreboot[master]: arch/x86: Add <arch/romstage.h>
by Kyösti Mälkki (Code Review) 17 Aug '19

17 Aug '19

Hello Patrick Rudolph, build bot (Jenkins), Damien Zammit, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/34911 to look at the new patch set (#4). Change subject: arch/x86: Add <arch/romstage.h> ...................................................................... arch/x86: Add <arch/romstage.h> Start with moving all postcar_frame related function declarations here from <arch/cpu.h>. Change-Id: I9aeef07f9009e44cc08927c85fe1862edf5c70dc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/include/arch/cpu.h A src/arch/x86/include/arch/romstage.h M src/arch/x86/postcar.c M src/arch/x86/postcar_loader.c M src/cpu/intel/car/romstage.c M src/drivers/amd/agesa/mtrr_fixme.c M src/drivers/amd/agesa/romstage.c M src/drivers/intel/fsp1_1/car.c M src/drivers/intel/fsp2_0/temp_ram_exit.c M src/include/cpu/intel/romstage.h M src/mainboard/emulation/qemu-i440fx/romstage.c M src/mainboard/emulation/qemu-q35/romstage.c M src/northbridge/amd/agesa/agesa_helper.h M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/i440bx/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/nehalem/memmap.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/x4x/memmap.c M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/quark/romstage/fsp2_0.c M src/soc/intel/skylake/romstage/romstage_fsp20.c 32 files changed, 113 insertions(+), 80 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/34911/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/34911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9aeef07f9009e44cc08927c85fe1862edf5c70dc Gerrit-Change-Number: 34911 Gerrit-PatchSet: 4 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: arch/x86: Add <arch/romstage.h>
by Kyösti Mälkki (Code Review) 17 Aug '19

17 Aug '19

Hello Patrick Rudolph, build bot (Jenkins), Damien Zammit, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/34911 to look at the new patch set (#3). Change subject: arch/x86: Add <arch/romstage.h> ...................................................................... arch/x86: Add <arch/romstage.h> Start with moving all postcar_frame related function declarations here from <arch/cpu.h>. Change-Id: I9aeef07f9009e44cc08927c85fe1862edf5c70dc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/include/arch/cpu.h A src/arch/x86/include/arch/romstage.h M src/arch/x86/postcar.c M src/arch/x86/postcar_loader.c M src/cpu/intel/car/romstage.c M src/drivers/amd/agesa/mtrr_fixme.c M src/drivers/intel/fsp2_0/temp_ram_exit.c M src/include/cpu/intel/romstage.h M src/northbridge/amd/agesa/agesa_helper.h M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/i440bx/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/nehalem/memmap.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/x4x/memmap.c M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/broadwell/romstage/romstage.c 22 files changed, 103 insertions(+), 78 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/34911/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/34911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9aeef07f9009e44cc08927c85fe1862edf5c70dc Gerrit-Change-Number: 34911 Gerrit-PatchSet: 3 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: arch/x86: Add <arch/romstage.h>
by Kyösti Mälkki (Code Review) 17 Aug '19

17 Aug '19

Hello Patrick Rudolph, build bot (Jenkins), Damien Zammit, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/34911 to look at the new patch set (#2). Change subject: arch/x86: Add <arch/romstage.h> ...................................................................... arch/x86: Add <arch/romstage.h> Start with moving all postcar_frame related function declarations here from <arch/cpu.h>. Change-Id: I9aeef07f9009e44cc08927c85fe1862edf5c70dc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/include/arch/cpu.h A src/arch/x86/include/arch/romstage.h M src/arch/x86/postcar.c M src/arch/x86/postcar_loader.c M src/cpu/intel/car/romstage.c M src/drivers/amd/agesa/mtrr_fixme.c M src/drivers/intel/fsp2_0/temp_ram_exit.c M src/include/cpu/intel/romstage.h M src/northbridge/amd/agesa/agesa_helper.h M src/northbridge/intel/e7505/memmap.c M src/northbridge/intel/gm45/memmap.c M src/northbridge/intel/haswell/memmap.c M src/northbridge/intel/i440bx/memmap.c M src/northbridge/intel/i945/memmap.c M src/northbridge/intel/nehalem/memmap.c M src/northbridge/intel/pineview/memmap.c M src/northbridge/intel/sandybridge/memmap.c M src/northbridge/intel/x4x/memmap.c M src/soc/amd/picasso/romstage.c M src/soc/amd/stoneyridge/romstage.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/broadwell/romstage/romstage.c 22 files changed, 102 insertions(+), 79 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/34911/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/34911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9aeef07f9009e44cc08927c85fe1862edf5c70dc Gerrit-Change-Number: 34911 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF
by Patrick Rudolph (Code Review) 17 Aug '19

17 Aug '19

Patrick Rudolph has uploaded a new patch set (#69) to the change originally created by Christian Walter. ( https://review.coreboot.org/c/coreboot/+/32734 ) Change subject: mb/supermicro/x11ssh: Add Supermicro X11SSH-TF ...................................................................... mb/supermicro/x11ssh: Add Supermicro X11SSH-TF Add support for the X11SSH-TF which is based on Intel KBL. Working: * SeaBios payload * LinuxBoot payload * IPMI of BMC * PCIe, SATA, USB ports * RS232 serial * Native graphics init Not working: * Tianocore doesn't work yet as the Aspeed NGI is text mode only. * Intel SGX, due to random crashes in soc/intel/common For more details have a look at the documentation. Please apply those patches as well for good user experience: I456be647b159f7a2ea7d94986a24424e56dcc8c4 I22c6885eae6fd7c778ac37b18f95b8775e9064e3 Ica0c20255f661dd61edc3a7d15646b7447c4658e Signed-off-by: Christian Walter <christian.walter(a)9elements.com> Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 --- M Documentation/mainboard/index.md A Documentation/mainboard/supermicro/x11ssh-tf.md A Documentation/mainboard/supermicro/x11ssh_flash.jpg A src/mainboard/supermicro/x11ssh/Kconfig A src/mainboard/supermicro/x11ssh/Kconfig.name A src/mainboard/supermicro/x11ssh/Makefile.inc A src/mainboard/supermicro/x11ssh/acpi/ec.asl A src/mainboard/supermicro/x11ssh/acpi/mainboard.asl A src/mainboard/supermicro/x11ssh/acpi/superio.asl A src/mainboard/supermicro/x11ssh/acpi_tables.c A src/mainboard/supermicro/x11ssh/board_info.txt A src/mainboard/supermicro/x11ssh/bootblock.c A src/mainboard/supermicro/x11ssh/cmos.layout A src/mainboard/supermicro/x11ssh/dsdt.asl A src/mainboard/supermicro/x11ssh/gpio.h A src/mainboard/supermicro/x11ssh/mainboard.c A src/mainboard/supermicro/x11ssh/ramstage.c A src/mainboard/supermicro/x11ssh/romstage.c A src/mainboard/supermicro/x11ssh/variants/tf/board_info.txt A src/mainboard/supermicro/x11ssh/variants/tf/devicetree.cb A src/mainboard/supermicro/x11ssh/vboot-ro-rwab.fmd 21 files changed, 1,011 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/32734/69 -- To view, visit https://review.coreboot.org/c/coreboot/+/32734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323 Gerrit-Change-Number: 32734 Gerrit-PatchSet: 69 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Keno Fischer <keno(a)alumni.harvard.edu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Name of user not set #1002358 Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: T. Hudson <trammell.hudson(a)gmail.com> Gerrit-Reviewer: Trammell Hudson <hudson(a)trmm.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Michael Niewöhner Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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