coreboot-gerrit July 2019

coreboot-gerrit@coreboot.org

1 participants
1550 discussions

Change in ...coreboot[master]: src/arch: This is an upgrade of SMBIOS to latest version 3.2
by Francois Toguo Fotso (Code Review) 07 Aug '23

07 Aug '23

Francois Toguo Fotso has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32090 Change subject: src/arch: This is an upgrade of SMBIOS to latest version 3.2 ...................................................................... src/arch: This is an upgrade of SMBIOS to latest version 3.2 This is the second of 2 patches upgrading the SMBIOS interface to the latest 3.2 First patch is in mosys. Newer required fields are added to various types definitions BUG=NONE TEST=Boot to OS on GLK Sparky Change-Id: I1171c20ac85a2231d949d4ac1c3e3c544ba3e5ef Signed-off-by: Francois Toguo <francois.toguo.fotso(a)intel.com> --- M src/arch/x86/smbios.c M src/include/smbios.h 2 files changed, 71 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/32090/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 8cb59df..b82780d 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -328,6 +328,17 @@ t->handle = *handle; *handle += 1; t->length = sizeof(struct smbios_type17) - 2; + t->memory_technology = MEMORY_TECHNOLOGY_UNKNOWN; + t->operating_mode_capability = MEMORY_OPERATING_MODE_CAP_UNKNOWN; + t->fw_version = 0xff; + t->manufacturer_id = dimm->mod_id; + t->product_id = 0x0000; + t->sub_ctrl_manufacturer_id = 0x0000; + t->sub_ctrl_product_id = 0x0000; + t->non_volatile_size = 0xffffffffffffffff; + t->volatile_size = 0xffffffffffffffff; + t->cache_size = 0xffffffffffffffff; + t->logical_size = 0xffffffffffffffff; return t->length + smbios_string_table_len(t->eos); } @@ -547,9 +558,31 @@ return len; } +u16 __weak smbios_processor_core_thread_count(u16 level_type) +{ + u16 count = 0; + int ecx = 0; + + for (ecx = 0 ; ecx < 255 ; ecx++) { + struct cpuid_result leaf_b; + leaf_b = cpuid_ext(0xb, ecx); + if ((cpuid_eax(0) < 0xb) || + !(leaf_b.eax | leaf_b.ebx | leaf_b.ecx | leaf_b.edx)) + return (((cpuid(1).ebx) >> 16) & 0x00ff); + + if ((leaf_b.ecx & 0xff00) == level_type) { + count = leaf_b.ebx & 0xffff; + break; + } + } + + return count; +} + static int smbios_write_type4(unsigned long *current, int handle) { struct cpuid_result res; + u16 core_count = 0, thread_count = 0; struct smbios_type4 *t = (struct smbios_type4 *)*current; int len = sizeof(struct smbios_type4); @@ -570,7 +603,15 @@ t->processor_version = smbios_processor_name(t->eos); t->processor_family = (res.eax > 0) ? 0x0c : 0x6; t->processor_type = 3; /* System Processor */ - t->core_count = (res.ebx >> 16) & 0xff; + + core_count = smbios_processor_core_thread_count(PROC_CORE_TYPE); + thread_count = smbios_processor_core_thread_count(PROC_THREAD_TYPE); + t->core_count2 = core_count; + t->core_count = (core_count > BYTE_LIMIT) ? 0xff : core_count; + t->thread_count2 = thread_count; + t->thread_count = (thread_count > BYTE_LIMIT) ? 0xff : core_count; + t->core_enabled2 = core_count; + t->l1_cache_handle = 0xffff; t->l2_cache_handle = 0xffff; t->l3_cache_handle = 0xffff; diff --git a/src/include/smbios.h b/src/include/smbios.h index af83bfe..e1d71be 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -52,6 +52,10 @@ u8 smbios_mainboard_feature_flags(void); const char *smbios_mainboard_location_in_chassis(void); u8 smbios_mainboard_enclosure_type(void); +u16 smbios_processor_core_thread_count(u16 level_type); +#ifdef CONFIG_MAINBOARD_FAMILY +const char *smbios_mainboard_family(void); +#endif #define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) #define BIOS_CHARACTERISTICS_PC_CARD (1 << 8) @@ -100,6 +104,11 @@ #define MEMORY_OPERATING_MODE_CAP_BYTE_ACCESS_PERSISTENT (1 << 4) #define MEMORY_OPERATING_MODE_CAP_BLOCK_ACCESS_PERSISTENT (1 << 5) +#define PROC_THREAD_TYPE 0x1 +#define PROC_CORE_TYPE 0x2 + +#define BYTE_LIMIT 255 + typedef enum { MEMORY_BUS_WIDTH_8 = 0, MEMORY_BUS_WIDTH_16 = 1, @@ -299,6 +308,7 @@ u8 location_in_chassis; u16 chassis_handle; u8 board_type; + u8 num_cont_obj_handles; u8 eos[2]; } __packed; @@ -390,6 +400,9 @@ u8 thread_count; u16 processor_characteristics; u16 processor_family2; + u16 core_count2; + u16 core_enabled2; + u16 thread_count2; u8 eos[2]; } __packed; @@ -401,6 +414,11 @@ u8 eos[2]; } __packed; +typedef struct { + u8 type; + u8 format_descriptor; +} log_type_descriptor; + struct smbios_type15 { u8 type; u8 length; @@ -471,6 +489,17 @@ u16 minimum_voltage; u16 maximum_voltage; u16 configured_voltage; + u8 memory_technology; + u16 operating_mode_capability; + u8 fw_version; + u16 manufacturer_id; + u16 product_id; + u16 sub_ctrl_manufacturer_id; + u16 sub_ctrl_product_id; + u64 non_volatile_size; + u64 volatile_size; + u64 cache_size; + u64 logical_size; u8 eos[2]; } __packed; -- To view, visit https://review.coreboot.org/c/coreboot/+/32090 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1171c20ac85a2231d949d4ac1c3e3c544ba3e5ef Gerrit-Change-Number: 32090 Gerrit-PatchSet: 1 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-MessageType: newchange

8 52

Change in ...coreboot[master]: Documentation: Document PMH known registers
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32253 Change subject: Documentation: Document PMH known registers ...................................................................... Documentation: Document PMH known registers Document what is known of Lenovo's PMH. Change-Id: I1891a6370123d9ee29d9e37e4b7b78b677343aed Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/pmh.md 2 files changed, 70 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/32253/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index d94c23e..adfe877 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -54,6 +54,7 @@ - [Hardware Maintenance Manual of ThinkPads](lenovo/thinkpad_hmm.md) - [T4xx common](lenovo/t4xx_series.md) - [X2xx common](lenovo/x2xx_series.md) +- [PMH](lenovo/pmh.md) ### Sandy Bridge series diff --git a/Documentation/mainboard/lenovo/pmh.md b/Documentation/mainboard/lenovo/pmh.md new file mode 100644 index 0000000..06c595d --- /dev/null +++ b/Documentation/mainboard/lenovo/pmh.md @@ -0,0 +1,69 @@ +# Lenovo's Power Management Hub + +The *Power Management Hub* or *PMH* originally was a CPLD connected to the EC +to controll power rails and reset lines on the lenovo mainboard. +Starting with Ivy Bridge series, the CPLD was removed and an EC with higher +pincount does the same job. The IO space to configure the PMH is still +the same. + +## PMH access + +The PMH register can be accessed using the IO region: + + IO region address: 0x15e0 + IO region size: 16 + +The IO region has the following layout: + +```eval_rst ++-------------------+---------------------------------------+ +| Offset | Register function | ++-------------------+---------------------------------------+ +| 0xc | ADDR_L: Low address into PMH space | ++-------------------+---------------------------------------+ +| 0xd | ADDR_H: High address into PMH space | ++-------------------+---------------------------------------+ +| 0xe | DATA: The data to read/write in PMH | ++-------------------+---------------------------------------+ +``` + +The PMH register space allows to access 512bytes. +The following registers are known: + +```eval_rst ++-------------------+---------------------------------------+ +| Offset | Register function | ++-------------------+---------------------------------------+ +| 0x50 | BIT3: dGPU power enable | +| +---------------------------------------+ +| | BIT5: Backlight enable | +| +---------------------------------------+ +| | BIT7: dGPU !reset | ++-------------------+---------------------------------------+ +| 0x51 | BIT0: Trackpoint enable | +| +---------------------------------------+ +| | BIT2: Touchpad enable | ++-------------------+---------------------------------------+ +| 0x60 | BIT3: Dock event enable | ++-------------------+---------------------------------------+ +| 0x62 | BIT0: Ultrabay power enable | ++-------------------+---------------------------------------+ +| 0xc2 | ID: ID of PMH | ++-------------------+---------------------------------------+ +| 0xc3 | REV: Revision of PMH | ++-------------------+---------------------------------------+ +``` + +The revision at 0xc3 seems to increment over time: + +```eval_rst ++-------------------+---------------------------------------+ +| Revision | Mainboard generation | ++-------------------+---------------------------------------+ +| 4 | T520 and T420s | ++-------------------+---------------------------------------+ +| 5 | W530 | ++-------------------+---------------------------------------+ +| 6 | T470p | ++-------------------+---------------------------------------+ +``` -- To view, visit https://review.coreboot.org/c/coreboot/+/32253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1891a6370123d9ee29d9e37e4b7b78b677343aed Gerrit-Change-Number: 32253 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

6 13

Change in ...coreboot[master]: Supplement motherboard name for G41M-GS
by Pixie (Code Review) 07 Aug '23

07 Aug '23

Pixie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32372 Change subject: Supplement motherboard name for G41M-GS ...................................................................... Supplement motherboard name for G41M-GS A few months ago, Arthur Heymans rebased a few patches to add support for the G41M-GS to aid me in testing my G41M-S. The two boards are exact duplicates, save for the -GS having a gigabit LAN chip, and the G41M-S having a 100Mbit one. I did some scant testing, and it worked, but I had a lot of other projects ongoing. Now that I remembered thisagain, I'm here to commit the motherboard name. Signed-off-by: Cheetah Pixie <mayulithsv(a)gmail.com> Change-Id: I97f77ec2c8cbd9c2f13e6890257cb7c5b1c77311 --- M src/mainboard/asrock/g41c-gs/Kconfig.name 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/32372/1 diff --git a/src/mainboard/asrock/g41c-gs/Kconfig.name b/src/mainboard/asrock/g41c-gs/Kconfig.name index 86a41aa..1a090ff3 100644 --- a/src/mainboard/asrock/g41c-gs/Kconfig.name +++ b/src/mainboard/asrock/g41c-gs/Kconfig.name @@ -5,7 +5,7 @@ bool "G41C-GS / G41C-S" config BOARD_ASROCK_G41M_GS - bool "G41M-GS" + bool "G41M-GS / G41M-S" config BOARD_ASROCK_G41M_S3 bool "G41M-S3" -- To view, visit https://review.coreboot.org/c/coreboot/+/32372 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I97f77ec2c8cbd9c2f13e6890257cb7c5b1c77311 Gerrit-Change-Number: 32372 Gerrit-PatchSet: 1 Gerrit-Owner: Pixie <mayulithsv(a)gmail.com> Gerrit-MessageType: newchange

5 9

Change in ...coreboot[master]: CML: Enable UPDs for PCH SLP_S0 for S0ix entry
by Sumeet R Pawnikar (Code Review) 07 Aug '23

07 Aug '23

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32668 Change subject: CML: Enable UPDs for PCH SLP_S0 for S0ix entry ...................................................................... CML: Enable UPDs for PCH SLP_S0 for S0ix entry Enable PCH SLP S0 UPDs for S0ix entry. BUG=None BRANCH=None TEST=Built and tested on Hatch Change-Id: I57a15746705a726b402431321a45b3257d837faa --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/32668/1 diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index cc01d10..796b717 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -177,9 +177,9 @@ params->PchLanEnable = dev->enabled; if (config->s0ix_enable) { params->SlpS0WithGbeSupport = 1; - params->PchPmSlpS0VmRuntimeControl = 0; - params->PchPmSlpS0Vm070VSupport = 0; - params->PchPmSlpS0Vm075VSupport = 0; + params->PchPmSlpS0VmRuntimeControl = 1; + params->PchPmSlpS0Vm070VSupport = 1; + params->PchPmSlpS0Vm075VSupport = 1; ignore_gbe_ltr(); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/32668 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57a15746705a726b402431321a45b3257d837faa Gerrit-Change-Number: 32668 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

2 3

Change in ...coreboot[master]: WIP: google/flapjack: Add Panels support
by Jerry Han (Code Review) 07 Aug '23

07 Aug '23

Jerry Han has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32840 Change subject: WIP: google/flapjack: Add Panels support ...................................................................... WIP: google/flapjack: Add Panels support Add panel BOE_TV101WUM_NG0, BOE_TV080WUM_NG0, INX_OTA7290D10P, AUO_NT51021D8P for FLAPJACK. Change-Id: I3e50df59de3db9ed6efcccbd01b553c21f793a3f Signed-off-by: Jerry Han <hanxu5(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/kukui/Makefile.inc M src/mainboard/google/kukui/display.c M src/mainboard/google/kukui/display.h A src/mainboard/google/kukui/panel_flapjack.c 4 files changed, 1,112 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/32840/1 diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index 9576b7d..a91f91e7 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -25,6 +25,7 @@ ramstage-y += display.c ramstage-y += panel_kukui.c ramstage-y += panel_krane.c +ramstage-y += panel_flapjack.c ramstage-y += mainboard.c ramstage-y += memlayout.ld ramstage-y += reset.c diff --git a/src/mainboard/google/kukui/display.c b/src/mainboard/google/kukui/display.c index b0a5026..55e129b 100644 --- a/src/mainboard/google/kukui/display.c +++ b/src/mainboard/google/kukui/display.c @@ -99,6 +99,8 @@ return &kukui_display_intf; else if (CONFIG(BOARD_GOOGLE_KRANE)) return &krane_display_intf; + else if (CONFIG(BOARD_GOOGLE_FLAPJACK)) + return &flapjack_display_intf; else return NULL; } diff --git a/src/mainboard/google/kukui/display.h b/src/mainboard/google/kukui/display.h index 1b184af..bc26c69 100644 --- a/src/mainboard/google/kukui/display.h +++ b/src/mainboard/google/kukui/display.h @@ -41,10 +41,21 @@ PANEL_KRANE_UNINITIALIZED }; +enum flapjack_panel_id { + PANEL_FLAPJACK_FIRST = 0, + PANEL_FLAPJACK_BOE_TV101WUM_NG0, + PANEL_FLAPJACK_BOE_TV080WUM_NG0, + PANEL_FLAPJACK_INX_OTA7290D10P, + PANEL_FLAPJACK_AUO_NT51021D8P, + PANEL_FLAPJACK_UNKNOWN, + PANEL_FLAPJACK_COUNT, + PANEL_FLAPJACK_UNINITIALIZED +}; union panel_id { enum kukui_panel_id kukui_panel; enum krane_panel_id krane_panel; + enum flapjack_panel_id flapjack_panel; int value; }; @@ -100,5 +111,6 @@ */ extern struct board_display_intf kukui_display_intf; extern struct board_display_intf krane_display_intf; +extern struct board_display_intf flapjack_display_intf; #endif diff --git a/src/mainboard/google/kukui/panel_flapjack.c b/src/mainboard/google/kukui/panel_flapjack.c new file mode 100644 index 0000000..1b72e8a --- /dev/null +++ b/src/mainboard/google/kukui/panel_flapjack.c @@ -0,0 +1,1097 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Huaqin Telecom Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <edid.h> +#include <gpio.h> +#include <soc/auxadc.h> +#include <soc/ddp.h> +#include <soc/dsi.h> +#include <soc/gpio.h> +#include <boardid.h> + +#include "display.h" +#include "gpio.h" + +#define PP3300_LCM_EN GPIO(SIM2_SIO) +#define PP1800_LCM_EN GPIO(SIM2_SRST) + +#define FLAPJACK_PANEL_ADC_ID 2 +#define FLAPJACK_PANEL_ID_BIT_POSITION 16 + +const int tolerance = 30000; /* 30,000 uV */ + +static struct edid flapjack_boe_tv080wum_edid = { + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .name = "1200x1920@60Hz", + .pixel_clock = 159420, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1200, .hbl = 164, .hso = 80, .hspw = 24, .hborder = 0, + .va = 1920, .vbl = 28, .vso = 10, .vspw = 4, .vborder = 0, + .phsync = '-', .pvsync = '-', + .x_mm = 107, .y_mm = 132, + }, +}; + +static struct lcm_init_table boe_tv080wum_lcm_init_cmd[] = { + {INIT_CMD, 1, {0x10} }, + {DELAY_CMD, 0x22, {} }, + {INIT_CMD, 2, {0xB0, 0x05} }, + {INIT_CMD, 2, {0xB1, 0xE5} }, + {INIT_CMD, 2, {0xB3, 0x52} }, + {INIT_CMD, 2, {0xB0, 0x00} }, + {INIT_CMD, 2, {0xB3, 0x88} }, + {INIT_CMD, 2, {0xB0, 0x04} }, + {INIT_CMD, 2, {0xB8, 0x00} }, + {INIT_CMD, 2, {0xB0, 0x00} }, + {INIT_CMD, 2, {0xB2, 0x50} }, + {INIT_CMD, 2, {0xB6, 0x03} }, + {INIT_CMD, 2, {0xBA, 0x8B} }, + {INIT_CMD, 2, {0xBF, 0x15} }, + {INIT_CMD, 2, {0xC0, 0x0F} }, + {INIT_CMD, 2, {0xC2, 0x0C} }, + {INIT_CMD, 2, {0xC3, 0x02} }, + {INIT_CMD, 2, {0xC4, 0x0C} }, + {INIT_CMD, 2, {0xC5, 0x02} }, + {INIT_CMD, 2, {0xB0, 0x01} }, + {INIT_CMD, 2, {0xE0, 0x26} }, + {INIT_CMD, 2, {0xE1, 0x26} }, + {INIT_CMD, 2, {0xDC, 0x00} }, + {INIT_CMD, 2, {0xDD, 0x00} }, + {INIT_CMD, 2, {0xCC, 0x26} }, + {INIT_CMD, 2, {0xCD, 0x26} }, + {INIT_CMD, 2, {0xC8, 0x00} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xD2, 0x04} }, + {INIT_CMD, 2, {0xD3, 0x04} }, + {INIT_CMD, 2, {0xE6, 0x03} }, + {INIT_CMD, 2, {0xE7, 0x03} }, + {INIT_CMD, 2, {0xC4, 0x08} }, + {INIT_CMD, 2, {0xC5, 0x08} }, + {INIT_CMD, 2, {0xD8, 0x07} }, + {INIT_CMD, 2, {0xD9, 0x07} }, + {INIT_CMD, 2, {0xC2, 0x06} }, + {INIT_CMD, 2, {0xC3, 0x06} }, + {INIT_CMD, 2, {0xD6, 0x05} }, + {INIT_CMD, 2, {0xD7, 0x05} }, + {INIT_CMD, 2, {0xC0, 0x0C} }, + {INIT_CMD, 2, {0xC1, 0x0C} }, + {INIT_CMD, 2, {0xD4, 0x0B} }, + {INIT_CMD, 2, {0xD5, 0x0B} }, + {INIT_CMD, 2, {0xCA, 0x0A} }, + {INIT_CMD, 2, {0xCB, 0x0A} }, + {INIT_CMD, 2, {0xDE, 0x09} }, + {INIT_CMD, 2, {0xDF, 0x09} }, + {INIT_CMD, 2, {0xC6, 0x26} }, + {INIT_CMD, 2, {0xC7, 0x26} }, + {INIT_CMD, 2, {0xCE, 0x00} }, + {INIT_CMD, 2, {0xCF, 0x00} }, + {INIT_CMD, 2, {0xDA, 0x26} }, + {INIT_CMD, 2, {0xDB, 0x26} }, + {INIT_CMD, 2, {0xE2, 0x00} }, + {INIT_CMD, 2, {0xE3, 0x00} }, + {INIT_CMD, 2, {0xB0, 0x02} }, + {INIT_CMD, 2, {0xC0, 0x00} }, + {INIT_CMD, 2, {0xC1, 0x07} }, + {INIT_CMD, 2, {0xC2, 0x0D} }, + {INIT_CMD, 2, {0xC3, 0x18} }, + {INIT_CMD, 2, {0xC4, 0x27} }, + {INIT_CMD, 2, {0xC5, 0x28} }, + {INIT_CMD, 2, {0xC6, 0x30} }, + {INIT_CMD, 2, {0xC7, 0x2E} }, + {INIT_CMD, 2, {0xC8, 0x2F} }, + {INIT_CMD, 2, {0xC9, 0x1A} }, + {INIT_CMD, 2, {0xCA, 0x20} }, + {INIT_CMD, 2, {0xCB, 0x29} }, + {INIT_CMD, 2, {0xCC, 0x26} }, + {INIT_CMD, 2, {0xCD, 0x32} }, + {INIT_CMD, 2, {0xCE, 0x33} }, + {INIT_CMD, 2, {0xCF, 0x31} }, + {INIT_CMD, 2, {0xD0, 0x06} }, + {INIT_CMD, 2, {0xD2, 0x00} }, + {INIT_CMD, 2, {0xD3, 0x07} }, + {INIT_CMD, 2, {0xD4, 0x12} }, + {INIT_CMD, 2, {0xD5, 0x26} }, + {INIT_CMD, 2, {0xD6, 0x3D} }, + {INIT_CMD, 2, {0xD7, 0x3F} }, + {INIT_CMD, 2, {0xD8, 0x3F} }, + {INIT_CMD, 2, {0xD9, 0x3F} }, + {INIT_CMD, 2, {0xDA, 0x3F} }, + {INIT_CMD, 2, {0xDB, 0x3F} }, + {INIT_CMD, 2, {0xDC, 0x3F} }, + {INIT_CMD, 2, {0xDD, 0x3F} }, + {INIT_CMD, 2, {0xDE, 0x3F} }, + {INIT_CMD, 2, {0xDF, 0x3A} }, + {INIT_CMD, 2, {0xE0, 0x37} }, + {INIT_CMD, 2, {0xE1, 0x35} }, + {INIT_CMD, 2, {0xE2, 0x07} }, + {INIT_CMD, 2, {0xB0, 0x03} }, + {INIT_CMD, 2, {0xC8, 0x0B} }, + {INIT_CMD, 2, {0xC9, 0x07} }, + {INIT_CMD, 2, {0xC3, 0x00} }, + {INIT_CMD, 2, {0xE7, 0x00} }, + {INIT_CMD, 2, {0xC5, 0x2A} }, + {INIT_CMD, 2, {0xDE, 0x2A} }, + {INIT_CMD, 2, {0xCA, 0x43} }, + {INIT_CMD, 2, {0xC9, 0x07} }, + {INIT_CMD, 2, {0xE4, 0xC0} }, + {INIT_CMD, 2, {0xE5, 0x0D} }, + {INIT_CMD, 2, {0xCB, 0x00} }, + {INIT_CMD, 2, {0xB0, 0x06} }, + {INIT_CMD, 2, {0xB8, 0xA5} }, + {INIT_CMD, 2, {0xC0, 0xA5} }, + {INIT_CMD, 2, {0xC7, 0x0F} }, + {INIT_CMD, 2, {0xD5, 0x32} }, + {INIT_CMD, 2, {0xB8, 0x00} }, + {INIT_CMD, 2, {0xC0, 0x00} }, + {INIT_CMD, 2, {0xBC, 0x00} }, + {INIT_CMD, 2, {0xB0, 0x07} }, + {INIT_CMD, 2, {0xB1, 0x00} }, + {INIT_CMD, 2, {0xB2, 0x09} }, + {INIT_CMD, 2, {0xB3, 0x19} }, + {INIT_CMD, 2, {0xB4, 0x2F} }, + {INIT_CMD, 2, {0xB5, 0x44} }, + {INIT_CMD, 2, {0xB6, 0x52} }, + {INIT_CMD, 2, {0xB7, 0x6A} }, + {INIT_CMD, 2, {0xB8, 0x8A} }, + {INIT_CMD, 2, {0xB9, 0xCA} }, + {INIT_CMD, 2, {0xBA, 0x0C} }, + {INIT_CMD, 2, {0xBB, 0x87} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x06} }, + {INIT_CMD, 2, {0xBD, 0x0A} }, + {INIT_CMD, 2, {0xBE, 0x9B} }, + {INIT_CMD, 2, {0xBF, 0x0C} }, + {INIT_CMD, 2, {0xC0, 0x3D} }, + {INIT_CMD, 2, {0xC1, 0x71} }, + {INIT_CMD, 2, {0xC2, 0x90} }, + {INIT_CMD, 2, {0xC3, 0xA0} }, + {INIT_CMD, 2, {0xC4, 0xA8} }, + {INIT_CMD, 2, {0xC5, 0xB1} }, + {INIT_CMD, 2, {0xC6, 0xBB} }, + {INIT_CMD, 2, {0xC7, 0xC0} }, + {INIT_CMD, 2, {0xC8, 0xC4} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {INIT_CMD, 2, {0xB0, 0x08} }, + {INIT_CMD, 2, {0xB1, 0x04} }, + {INIT_CMD, 2, {0xB2, 0x08} }, + {INIT_CMD, 2, {0xB3, 0x19} }, + {INIT_CMD, 2, {0xB4, 0x31} }, + {INIT_CMD, 2, {0xB5, 0x46} }, + {INIT_CMD, 2, {0xB6, 0x55} }, + {INIT_CMD, 2, {0xB7, 0x6E} }, + {INIT_CMD, 2, {0xB8, 0x92} }, + {INIT_CMD, 2, {0xB9, 0xD4} }, + {INIT_CMD, 2, {0xBA, 0x1B} }, + {INIT_CMD, 2, {0xBB, 0x9B} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x28} }, + {INIT_CMD, 2, {0xBD, 0x2D} }, + {INIT_CMD, 2, {0xBE, 0xC3} }, + {INIT_CMD, 2, {0xBF, 0x2F} }, + {INIT_CMD, 2, {0xC0, 0x62} }, + {INIT_CMD, 2, {0xC1, 0x99} }, + {INIT_CMD, 2, {0xC2, 0xAB} }, + {INIT_CMD, 2, {0xC3, 0xBF} }, + {INIT_CMD, 2, {0xC4, 0xCF} }, + {INIT_CMD, 2, {0xC5, 0xDF} }, + {INIT_CMD, 2, {0xC6, 0xF0} }, + {INIT_CMD, 2, {0xC7, 0xF9} }, + {INIT_CMD, 2, {0xC8, 0xFC} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {INIT_CMD, 2, {0xB0, 0x09} }, + {INIT_CMD, 2, {0xB1, 0x04} }, + {INIT_CMD, 2, {0xB2, 0x05} }, + {INIT_CMD, 2, {0xB3, 0x17} }, + {INIT_CMD, 2, {0xB4, 0x2E} }, + {INIT_CMD, 2, {0xB5, 0x42} }, + {INIT_CMD, 2, {0xB6, 0x51} }, + {INIT_CMD, 2, {0xB7, 0x69} }, + {INIT_CMD, 2, {0xB8, 0x88} }, + {INIT_CMD, 2, {0xB9, 0xC9} }, + {INIT_CMD, 2, {0xBA, 0x0C} }, + {INIT_CMD, 2, {0xBB, 0x86} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x03} }, + {INIT_CMD, 2, {0xBD, 0x08} }, + {INIT_CMD, 2, {0xBE, 0x95} }, + {INIT_CMD, 2, {0xBF, 0x05} }, + {INIT_CMD, 2, {0xC0, 0x35} }, + {INIT_CMD, 2, {0xC1, 0x62} }, + {INIT_CMD, 2, {0xC2, 0x81} }, + {INIT_CMD, 2, {0xC3, 0x96} }, + {INIT_CMD, 2, {0xC4, 0x9E} }, + {INIT_CMD, 2, {0xC5, 0xA5} }, + {INIT_CMD, 2, {0xC6, 0xAD} }, + {INIT_CMD, 2, {0xC7, 0xB1} }, + {INIT_CMD, 2, {0xC8, 0xB4} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {INIT_CMD, 2, {0xB0, 0x0A} }, + {INIT_CMD, 2, {0xB1, 0x00} }, + {INIT_CMD, 2, {0xB2, 0x09} }, + {INIT_CMD, 2, {0xB3, 0x19} }, + {INIT_CMD, 2, {0xB4, 0x2F} }, + {INIT_CMD, 2, {0xB5, 0x44} }, + {INIT_CMD, 2, {0xB6, 0x52} }, + {INIT_CMD, 2, {0xB7, 0x6A} }, + {INIT_CMD, 2, {0xB8, 0x8A} }, + {INIT_CMD, 2, {0xB9, 0xCA} }, + {INIT_CMD, 2, {0xBA, 0x0C} }, + {INIT_CMD, 2, {0xBB, 0x87} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x06} }, + {INIT_CMD, 2, {0xBD, 0x0A} }, + {INIT_CMD, 2, {0xBE, 0x9B} }, + {INIT_CMD, 2, {0xBF, 0x0C} }, + {INIT_CMD, 2, {0xC0, 0x3D} }, + {INIT_CMD, 2, {0xC1, 0x71} }, + {INIT_CMD, 2, {0xC2, 0x90} }, + {INIT_CMD, 2, {0xC3, 0xA0} }, + {INIT_CMD, 2, {0xC4, 0xA8} }, + {INIT_CMD, 2, {0xC5, 0xB1} }, + {INIT_CMD, 2, {0xC6, 0xBB} }, + {INIT_CMD, 2, {0xC7, 0xC0} }, + {INIT_CMD, 2, {0xC8, 0xC4} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {INIT_CMD, 2, {0xB0, 0x0B} }, + {INIT_CMD, 2, {0xB1, 0x04} }, + {INIT_CMD, 2, {0xB2, 0x08} }, + {INIT_CMD, 2, {0xB3, 0x19} }, + {INIT_CMD, 2, {0xB4, 0x31} }, + {INIT_CMD, 2, {0xB5, 0x46} }, + {INIT_CMD, 2, {0xB6, 0x55} }, + {INIT_CMD, 2, {0xB7, 0x6E} }, + {INIT_CMD, 2, {0xB8, 0x92} }, + {INIT_CMD, 2, {0xB9, 0xD4} }, + {INIT_CMD, 2, {0xBA, 0x1B} }, + {INIT_CMD, 2, {0xBB, 0x9B} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x28} }, + {INIT_CMD, 2, {0xBD, 0x2D} }, + {INIT_CMD, 2, {0xBE, 0xC3} }, + {INIT_CMD, 2, {0xBF, 0x2F} }, + {INIT_CMD, 2, {0xC0, 0x62} }, + {INIT_CMD, 2, {0xC1, 0x99} }, + {INIT_CMD, 2, {0xC2, 0xAB} }, + {INIT_CMD, 2, {0xC3, 0xBF} }, + {INIT_CMD, 2, {0xC4, 0xCF} }, + {INIT_CMD, 2, {0xC5, 0xDF} }, + {INIT_CMD, 2, {0xC6, 0xF0} }, + {INIT_CMD, 2, {0xC7, 0xF9} }, + {INIT_CMD, 2, {0xC8, 0xFC} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {INIT_CMD, 2, {0xB0, 0x0C} }, + {INIT_CMD, 2, {0xB1, 0x04} }, + {INIT_CMD, 2, {0xB2, 0x05} }, + {INIT_CMD, 2, {0xB3, 0x17} }, + {INIT_CMD, 2, {0xB4, 0x2E} }, + {INIT_CMD, 2, {0xB5, 0x42} }, + {INIT_CMD, 2, {0xB6, 0x51} }, + {INIT_CMD, 2, {0xB7, 0x69} }, + {INIT_CMD, 2, {0xB8, 0x88} }, + {INIT_CMD, 2, {0xB9, 0xC9} }, + {INIT_CMD, 2, {0xBA, 0x0C} }, + {INIT_CMD, 2, {0xBB, 0x86} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x03} }, + {INIT_CMD, 2, {0xBD, 0x08} }, + {INIT_CMD, 2, {0xBE, 0x95} }, + {INIT_CMD, 2, {0xBF, 0x05} }, + {INIT_CMD, 2, {0xC0, 0x35} }, + {INIT_CMD, 2, {0xC1, 0x62} }, + {INIT_CMD, 2, {0xC2, 0x81} }, + {INIT_CMD, 2, {0xC3, 0x96} }, + {INIT_CMD, 2, {0xC4, 0x9E} }, + {INIT_CMD, 2, {0xC5, 0xA5} }, + {INIT_CMD, 2, {0xC6, 0xAD} }, + {INIT_CMD, 2, {0xC7, 0xB1} }, + {INIT_CMD, 2, {0xC8, 0xB4} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {DELAY_CMD, 0x64, {} }, + {INIT_CMD, 2, {0xB0, 0x00} }, + {INIT_CMD, 2, {0xB3, 0x08} }, + {INIT_CMD, 2, {0xB0, 0x04} }, + {INIT_CMD, 2, {0xB8, 0x68} }, + {DELAY_CMD, 0x0A, {} }, + {INIT_CMD, 1, {0x11} }, + {DELAY_CMD, 0x78, {} }, + {INIT_CMD, 1, {0x29} }, + {DELAY_CMD, 0x14, {} }, + +}; + +/* flapjack C19 BOE tv101wum panel : PANEL_FLAPJACK_BOE_TV101WUM_NG0 */ +static struct edid flapjack_boe_tv101wum_edid = { + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .name = "1200x1920@60Hz", + .pixel_clock = 159420, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1200, .hbl = 164, .hso = 80, .hspw = 24, .hborder = 0, + .va = 1920, .vbl = 28, .vso = 10, .vspw = 4, .vborder = 0, + .phsync = '-', .pvsync = '-', + .x_mm = 135, .y_mm = 216, + }, +}; + +static struct lcm_init_table boe_tv101wum_lcm_init_cmd[] = { + {INIT_CMD, 1, {0x10} }, + {DELAY_CMD, 0x22, {} }, + {INIT_CMD, 2, {0xB0, 0x05} }, + {INIT_CMD, 2, {0xB1, 0xE5} }, + {INIT_CMD, 2, {0xB3, 0x52} }, + {INIT_CMD, 2, {0xB0, 0x00} }, + {INIT_CMD, 2, {0xB3, 0x88} }, + {INIT_CMD, 2, {0xB0, 0x04} }, + {INIT_CMD, 2, {0xB8, 0x00} }, + {INIT_CMD, 2, {0xB0, 0x00} }, + {INIT_CMD, 2, {0xB2, 0x50} }, + {INIT_CMD, 2, {0xB6, 0x03} }, + {INIT_CMD, 2, {0xBA, 0x8B} }, + {INIT_CMD, 2, {0xBF, 0x15} }, + {INIT_CMD, 2, {0xC0, 0x0F} }, + {INIT_CMD, 2, {0xC2, 0x0C} }, + {INIT_CMD, 2, {0xC3, 0x02} }, + {INIT_CMD, 2, {0xC4, 0x0C} }, + {INIT_CMD, 2, {0xC5, 0x02} }, + {INIT_CMD, 2, {0xB0, 0x01} }, + {INIT_CMD, 2, {0xE0, 0x26} }, + {INIT_CMD, 2, {0xE1, 0x26} }, + {INIT_CMD, 2, {0xDC, 0x00} }, + {INIT_CMD, 2, {0xDD, 0x00} }, + {INIT_CMD, 2, {0xCC, 0x26} }, + {INIT_CMD, 2, {0xCD, 0x26} }, + {INIT_CMD, 2, {0xC8, 0x00} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xD2, 0x04} }, + {INIT_CMD, 2, {0xD3, 0x04} }, + {INIT_CMD, 2, {0xE6, 0x03} }, + {INIT_CMD, 2, {0xE7, 0x03} }, + {INIT_CMD, 2, {0xC4, 0x08} }, + {INIT_CMD, 2, {0xC5, 0x08} }, + {INIT_CMD, 2, {0xD8, 0x07} }, + {INIT_CMD, 2, {0xD9, 0x07} }, + {INIT_CMD, 2, {0xC2, 0x06} }, + {INIT_CMD, 2, {0xC3, 0x06} }, + {INIT_CMD, 2, {0xD6, 0x05} }, + {INIT_CMD, 2, {0xD7, 0x05} }, + {INIT_CMD, 2, {0xC0, 0x0C} }, + {INIT_CMD, 2, {0xC1, 0x0C} }, + {INIT_CMD, 2, {0xD4, 0x0B} }, + {INIT_CMD, 2, {0xD5, 0x0B} }, + {INIT_CMD, 2, {0xCA, 0x0A} }, + {INIT_CMD, 2, {0xCB, 0x0A} }, + {INIT_CMD, 2, {0xDE, 0x09} }, + {INIT_CMD, 2, {0xDF, 0x09} }, + {INIT_CMD, 2, {0xC6, 0x26} }, + {INIT_CMD, 2, {0xC7, 0x26} }, + {INIT_CMD, 2, {0xCE, 0x00} }, + {INIT_CMD, 2, {0xCF, 0x00} }, + {INIT_CMD, 2, {0xDA, 0x26} }, + {INIT_CMD, 2, {0xDB, 0x26} }, + {INIT_CMD, 2, {0xE2, 0x00} }, + {INIT_CMD, 2, {0xE3, 0x00} }, + {INIT_CMD, 2, {0xB0, 0x02} }, + {INIT_CMD, 2, {0xC0, 0x00} }, + {INIT_CMD, 2, {0xC1, 0x07} }, + {INIT_CMD, 2, {0xC2, 0x0D} }, + {INIT_CMD, 2, {0xC3, 0x18} }, + {INIT_CMD, 2, {0xC4, 0x27} }, + {INIT_CMD, 2, {0xC5, 0x28} }, + {INIT_CMD, 2, {0xC6, 0x30} }, + {INIT_CMD, 2, {0xC7, 0x2E} }, + {INIT_CMD, 2, {0xC8, 0x2F} }, + {INIT_CMD, 2, {0xC9, 0x1A} }, + {INIT_CMD, 2, {0xCA, 0x20} }, + {INIT_CMD, 2, {0xCB, 0x29} }, + {INIT_CMD, 2, {0xCC, 0x26} }, + {INIT_CMD, 2, {0xCD, 0x32} }, + {INIT_CMD, 2, {0xCE, 0x33} }, + {INIT_CMD, 2, {0xCF, 0x31} }, + {INIT_CMD, 2, {0xD0, 0x06} }, + {INIT_CMD, 2, {0xD2, 0x00} }, + {INIT_CMD, 2, {0xD3, 0x07} }, + {INIT_CMD, 2, {0xD4, 0x12} }, + {INIT_CMD, 2, {0xD5, 0x26} }, + {INIT_CMD, 2, {0xD6, 0x3D} }, + {INIT_CMD, 2, {0xD7, 0x3F} }, + {INIT_CMD, 2, {0xD8, 0x3F} }, + {INIT_CMD, 2, {0xD9, 0x3F} }, + {INIT_CMD, 2, {0xDA, 0x3F} }, + {INIT_CMD, 2, {0xDB, 0x3F} }, + {INIT_CMD, 2, {0xDC, 0x3F} }, + {INIT_CMD, 2, {0xDD, 0x3F} }, + {INIT_CMD, 2, {0xDE, 0x3F} }, + {INIT_CMD, 2, {0xDF, 0x3A} }, + {INIT_CMD, 2, {0xE0, 0x37} }, + {INIT_CMD, 2, {0xE1, 0x35} }, + {INIT_CMD, 2, {0xE2, 0x07} }, + {INIT_CMD, 2, {0xB0, 0x03} }, + {INIT_CMD, 2, {0xC8, 0x0B} }, + {INIT_CMD, 2, {0xC9, 0x07} }, + {INIT_CMD, 2, {0xC3, 0x00} }, + {INIT_CMD, 2, {0xE7, 0x00} }, + {INIT_CMD, 2, {0xC5, 0x2A} }, + {INIT_CMD, 2, {0xDE, 0x2A} }, + {INIT_CMD, 2, {0xCA, 0x43} }, + {INIT_CMD, 2, {0xC9, 0x07} }, + {INIT_CMD, 2, {0xE4, 0xC0} }, + {INIT_CMD, 2, {0xE5, 0x0D} }, + {INIT_CMD, 2, {0xCB, 0x00} }, + {INIT_CMD, 2, {0xB0, 0x06} }, + {INIT_CMD, 2, {0xB8, 0xA5} }, + {INIT_CMD, 2, {0xC0, 0xA5} }, + {INIT_CMD, 2, {0xC7, 0x0F} }, + {INIT_CMD, 2, {0xD5, 0x32} }, + {INIT_CMD, 2, {0xB8, 0x00} }, + {INIT_CMD, 2, {0xC0, 0x00} }, + {INIT_CMD, 2, {0xBC, 0x00} }, + {INIT_CMD, 2, {0xB0, 0x07} }, + {INIT_CMD, 2, {0xB1, 0x00} }, + {INIT_CMD, 2, {0xB2, 0x09} }, + {INIT_CMD, 2, {0xB3, 0x19} }, + {INIT_CMD, 2, {0xB4, 0x2F} }, + {INIT_CMD, 2, {0xB5, 0x44} }, + {INIT_CMD, 2, {0xB6, 0x52} }, + {INIT_CMD, 2, {0xB7, 0x6A} }, + {INIT_CMD, 2, {0xB8, 0x8A} }, + {INIT_CMD, 2, {0xB9, 0xCA} }, + {INIT_CMD, 2, {0xBA, 0x0C} }, + {INIT_CMD, 2, {0xBB, 0x87} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x06} }, + {INIT_CMD, 2, {0xBD, 0x0A} }, + {INIT_CMD, 2, {0xBE, 0x9B} }, + {INIT_CMD, 2, {0xBF, 0x0C} }, + {INIT_CMD, 2, {0xC0, 0x3D} }, + {INIT_CMD, 2, {0xC1, 0x71} }, + {INIT_CMD, 2, {0xC2, 0x90} }, + {INIT_CMD, 2, {0xC3, 0xA0} }, + {INIT_CMD, 2, {0xC4, 0xA8} }, + {INIT_CMD, 2, {0xC5, 0xB1} }, + {INIT_CMD, 2, {0xC6, 0xBB} }, + {INIT_CMD, 2, {0xC7, 0xC0} }, + {INIT_CMD, 2, {0xC8, 0xC4} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {INIT_CMD, 2, {0xB0, 0x08} }, + {INIT_CMD, 2, {0xB1, 0x04} }, + {INIT_CMD, 2, {0xB2, 0x08} }, + {INIT_CMD, 2, {0xB3, 0x19} }, + {INIT_CMD, 2, {0xB4, 0x31} }, + {INIT_CMD, 2, {0xB5, 0x46} }, + {INIT_CMD, 2, {0xB6, 0x55} }, + {INIT_CMD, 2, {0xB7, 0x6E} }, + {INIT_CMD, 2, {0xB8, 0x92} }, + {INIT_CMD, 2, {0xB9, 0xD4} }, + {INIT_CMD, 2, {0xBA, 0x1B} }, + {INIT_CMD, 2, {0xBB, 0x9B} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x28} }, + {INIT_CMD, 2, {0xBD, 0x2D} }, + {INIT_CMD, 2, {0xBE, 0xC3} }, + {INIT_CMD, 2, {0xBF, 0x2F} }, + {INIT_CMD, 2, {0xC0, 0x62} }, + {INIT_CMD, 2, {0xC1, 0x99} }, + {INIT_CMD, 2, {0xC2, 0xAB} }, + {INIT_CMD, 2, {0xC3, 0xBF} }, + {INIT_CMD, 2, {0xC4, 0xCF} }, + {INIT_CMD, 2, {0xC5, 0xDF} }, + {INIT_CMD, 2, {0xC6, 0xF0} }, + {INIT_CMD, 2, {0xC7, 0xF9} }, + {INIT_CMD, 2, {0xC8, 0xFC} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {INIT_CMD, 2, {0xB0, 0x09} }, + {INIT_CMD, 2, {0xB1, 0x04} }, + {INIT_CMD, 2, {0xB2, 0x05} }, + {INIT_CMD, 2, {0xB3, 0x17} }, + {INIT_CMD, 2, {0xB4, 0x2E} }, + {INIT_CMD, 2, {0xB5, 0x42} }, + {INIT_CMD, 2, {0xB6, 0x51} }, + {INIT_CMD, 2, {0xB7, 0x69} }, + {INIT_CMD, 2, {0xB8, 0x88} }, + {INIT_CMD, 2, {0xB9, 0xC9} }, + {INIT_CMD, 2, {0xBA, 0x0C} }, + {INIT_CMD, 2, {0xBB, 0x86} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x03} }, + {INIT_CMD, 2, {0xBD, 0x08} }, + {INIT_CMD, 2, {0xBE, 0x95} }, + {INIT_CMD, 2, {0xBF, 0x05} }, + {INIT_CMD, 2, {0xC0, 0x35} }, + {INIT_CMD, 2, {0xC1, 0x62} }, + {INIT_CMD, 2, {0xC2, 0x81} }, + {INIT_CMD, 2, {0xC3, 0x96} }, + {INIT_CMD, 2, {0xC4, 0x9E} }, + {INIT_CMD, 2, {0xC5, 0xA5} }, + {INIT_CMD, 2, {0xC6, 0xAD} }, + {INIT_CMD, 2, {0xC7, 0xB1} }, + {INIT_CMD, 2, {0xC8, 0xB4} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {INIT_CMD, 2, {0xB0, 0x0A} }, + {INIT_CMD, 2, {0xB1, 0x00} }, + {INIT_CMD, 2, {0xB2, 0x09} }, + {INIT_CMD, 2, {0xB3, 0x19} }, + {INIT_CMD, 2, {0xB4, 0x2F} }, + {INIT_CMD, 2, {0xB5, 0x44} }, + {INIT_CMD, 2, {0xB6, 0x52} }, + {INIT_CMD, 2, {0xB7, 0x6A} }, + {INIT_CMD, 2, {0xB8, 0x8A} }, + {INIT_CMD, 2, {0xB9, 0xCA} }, + {INIT_CMD, 2, {0xBA, 0x0C} }, + {INIT_CMD, 2, {0xBB, 0x87} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x06} }, + {INIT_CMD, 2, {0xBD, 0x0A} }, + {INIT_CMD, 2, {0xBE, 0x9B} }, + {INIT_CMD, 2, {0xBF, 0x0C} }, + {INIT_CMD, 2, {0xC0, 0x3D} }, + {INIT_CMD, 2, {0xC1, 0x71} }, + {INIT_CMD, 2, {0xC2, 0x90} }, + {INIT_CMD, 2, {0xC3, 0xA0} }, + {INIT_CMD, 2, {0xC4, 0xA8} }, + {INIT_CMD, 2, {0xC5, 0xB1} }, + {INIT_CMD, 2, {0xC6, 0xBB} }, + {INIT_CMD, 2, {0xC7, 0xC0} }, + {INIT_CMD, 2, {0xC8, 0xC4} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {INIT_CMD, 2, {0xB0, 0x0B} }, + {INIT_CMD, 2, {0xB1, 0x04} }, + {INIT_CMD, 2, {0xB2, 0x08} }, + {INIT_CMD, 2, {0xB3, 0x19} }, + {INIT_CMD, 2, {0xB4, 0x31} }, + {INIT_CMD, 2, {0xB5, 0x46} }, + {INIT_CMD, 2, {0xB6, 0x55} }, + {INIT_CMD, 2, {0xB7, 0x6E} }, + {INIT_CMD, 2, {0xB8, 0x92} }, + {INIT_CMD, 2, {0xB9, 0xD4} }, + {INIT_CMD, 2, {0xBA, 0x1B} }, + {INIT_CMD, 2, {0xBB, 0x9B} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x28} }, + {INIT_CMD, 2, {0xBD, 0x2D} }, + {INIT_CMD, 2, {0xBE, 0xC3} }, + {INIT_CMD, 2, {0xBF, 0x2F} }, + {INIT_CMD, 2, {0xC0, 0x62} }, + {INIT_CMD, 2, {0xC1, 0x99} }, + {INIT_CMD, 2, {0xC2, 0xAB} }, + {INIT_CMD, 2, {0xC3, 0xBF} }, + {INIT_CMD, 2, {0xC4, 0xCF} }, + {INIT_CMD, 2, {0xC5, 0xDF} }, + {INIT_CMD, 2, {0xC6, 0xF0} }, + {INIT_CMD, 2, {0xC7, 0xF9} }, + {INIT_CMD, 2, {0xC8, 0xFC} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {INIT_CMD, 2, {0xB0, 0x0C} }, + {INIT_CMD, 2, {0xB1, 0x04} }, + {INIT_CMD, 2, {0xB2, 0x05} }, + {INIT_CMD, 2, {0xB3, 0x17} }, + {INIT_CMD, 2, {0xB4, 0x2E} }, + {INIT_CMD, 2, {0xB5, 0x42} }, + {INIT_CMD, 2, {0xB6, 0x51} }, + {INIT_CMD, 2, {0xB7, 0x69} }, + {INIT_CMD, 2, {0xB8, 0x88} }, + {INIT_CMD, 2, {0xB9, 0xC9} }, + {INIT_CMD, 2, {0xBA, 0x0C} }, + {INIT_CMD, 2, {0xBB, 0x86} }, + {DELAY_CMD, 0x05, {} }, + {INIT_CMD, 2, {0xBC, 0x03} }, + {INIT_CMD, 2, {0xBD, 0x08} }, + {INIT_CMD, 2, {0xBE, 0x95} }, + {INIT_CMD, 2, {0xBF, 0x05} }, + {INIT_CMD, 2, {0xC0, 0x35} }, + {INIT_CMD, 2, {0xC1, 0x62} }, + {INIT_CMD, 2, {0xC2, 0x81} }, + {INIT_CMD, 2, {0xC3, 0x96} }, + {INIT_CMD, 2, {0xC4, 0x9E} }, + {INIT_CMD, 2, {0xC5, 0xA5} }, + {INIT_CMD, 2, {0xC6, 0xAD} }, + {INIT_CMD, 2, {0xC7, 0xB1} }, + {INIT_CMD, 2, {0xC8, 0xB4} }, + {INIT_CMD, 2, {0xC9, 0x00} }, + {INIT_CMD, 2, {0xCA, 0x00} }, + {INIT_CMD, 2, {0xCB, 0x16} }, + {INIT_CMD, 2, {0xCC, 0xAF} }, + {INIT_CMD, 2, {0xCD, 0xFF} }, + {INIT_CMD, 2, {0xCE, 0xFF} }, + {DELAY_CMD, 0x64, {} }, + {INIT_CMD, 2, {0xB0, 0x00} }, + {INIT_CMD, 2, {0xB3, 0x08} }, + {INIT_CMD, 2, {0xB0, 0x04} }, + {INIT_CMD, 2, {0xB8, 0x68} }, + {DELAY_CMD, 0x0A, {} }, + {INIT_CMD, 1, {0x11} }, + {DELAY_CMD, 0x78, {} }, + {INIT_CMD, 1, {0x29} }, + {DELAY_CMD, 0x14, {} }, +}; + +/* flapjack C18 AUO NT51021 panel : PANEL_AUO_NT51021D8P */ +static struct edid flapjack_auo_nt51021d8p_edid = { + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .name = "1200x1920@60Hz", + .pixel_clock = 159420, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1200, .hbl = 141, .hso = 80, .hspw = 1, .hborder = 0, + .va = 1920, .vbl = 61, .vso = 35, .vspw = 1, .vborder = 0, + .phsync = '-', .pvsync = '-', + .x_mm = 107, .y_mm = 132, + }, +}; + +static struct lcm_init_table auo_nt51021d8p_lcm_init_cmd[] = { + {INIT_CMD, 1, {0x11} }, + {DELAY_CMD, 0x78, {} }, + {INIT_CMD, 1, {0x29} }, + {DELAY_CMD, 0x14, {} }, +}; + +/* flapjack C19 INX OTA7290 panel : PANEL_INX_OTA7290D10P */ +static struct edid flapjack_inx_ota7290d10p_edid = { + .panel_bits_per_color = 8, + .panel_bits_per_pixel = 24, + .mode = { + .name = "1200x1920@60Hz", + .pixel_clock = 159420, + .lvds_dual_channel = 0, + .refresh = 60, + .ha = 1200, .hbl = 141, .hso = 80, .hspw = 1, .hborder = 0, + .va = 1920, .vbl = 61, .vso = 35, .vspw = 1, .vborder = 0, + .phsync = '-', .pvsync = '-', + .x_mm = 135, .y_mm = 216, + }, +}; + +static struct lcm_init_table inx_ota7290d10p_lcm_init_cmd[] = { + {INIT_CMD, 2, { 0xB0, 0x5A} }, + {INIT_CMD, 2, { 0xB1, 0x00} }, + {INIT_CMD, 2, { 0x89, 0x01} }, + {INIT_CMD, 2, { 0x91, 0x17} }, + {INIT_CMD, 2, { 0xB1, 0x03} }, + {INIT_CMD, 2, { 0x2C, 0x28} }, + {INIT_CMD, 2, { 0x00, 0xF1} }, + {INIT_CMD, 2, { 0x01, 0x78} }, + {INIT_CMD, 2, { 0x02, 0x3C} }, + {INIT_CMD, 2, { 0x03, 0x1E} }, + {INIT_CMD, 2, { 0x04, 0x8F} }, + {INIT_CMD, 2, { 0x05, 0x01} }, + {INIT_CMD, 2, { 0x06, 0x00} }, + {INIT_CMD, 2, { 0x07, 0x00} }, + {INIT_CMD, 2, { 0x08, 0x00} }, + {INIT_CMD, 2, { 0x09, 0x00} }, + {INIT_CMD, 2, { 0x0A, 0x01} }, + {INIT_CMD, 2, { 0x0B, 0x3C} }, + {INIT_CMD, 2, { 0x0C, 0x00} }, + {INIT_CMD, 2, { 0x0D, 0x00} }, + {INIT_CMD, 2, { 0x0E, 0x24} }, + {INIT_CMD, 2, { 0x0F, 0x1C} }, + {INIT_CMD, 2, { 0x10, 0xC8} }, + {INIT_CMD, 2, { 0x11, 0x60} }, + {INIT_CMD, 2, { 0x12, 0x70} }, + {INIT_CMD, 2, { 0x13, 0x01} }, + {INIT_CMD, 2, { 0x14, 0xE3} }, + {INIT_CMD, 2, { 0x15, 0xFF} }, + {INIT_CMD, 2, { 0x16, 0x3D} }, + {INIT_CMD, 2, { 0x17, 0x0E} }, + {INIT_CMD, 2, { 0x18, 0x01} }, + {INIT_CMD, 2, { 0x19, 0x00} }, + {INIT_CMD, 2, { 0x1A, 0x00} }, + {INIT_CMD, 2, { 0x1B, 0xFC} }, + {INIT_CMD, 2, { 0x1C, 0x0B} }, + {INIT_CMD, 2, { 0x1D, 0xA0} }, + {INIT_CMD, 2, { 0x1E, 0x03} }, + {INIT_CMD, 2, { 0x1F, 0x04} }, + {INIT_CMD, 2, { 0x20, 0x0C} }, + {INIT_CMD, 2, { 0x21, 0x00} }, + {INIT_CMD, 2, { 0x22, 0x04} }, + {INIT_CMD, 2, { 0x23, 0x81} }, + {INIT_CMD, 2, { 0x24, 0x1F} }, + {INIT_CMD, 2, { 0x25, 0x10} }, + {INIT_CMD, 2, { 0x26, 0x9B} }, + {INIT_CMD, 2, { 0x2D, 0x01} }, + {INIT_CMD, 2, { 0x2E, 0x84} }, + {INIT_CMD, 2, { 0x2F, 0x00} }, + {INIT_CMD, 2, { 0x30, 0x02} }, + {INIT_CMD, 2, { 0x31, 0x08} }, + {INIT_CMD, 2, { 0x32, 0x01} }, + {INIT_CMD, 2, { 0x33, 0x1C} }, + {INIT_CMD, 2, { 0x34, 0x70} }, + {INIT_CMD, 2, { 0x35, 0xFF} }, + {INIT_CMD, 2, { 0x36, 0xFF} }, + {INIT_CMD, 2, { 0x37, 0xFF} }, + {INIT_CMD, 2, { 0x38, 0xFF} }, + {INIT_CMD, 2, { 0x39, 0xFF} }, + {INIT_CMD, 2, { 0x3A, 0x05} }, + {INIT_CMD, 2, { 0x3B, 0x00} }, + {INIT_CMD, 2, { 0x3C, 0x00} }, + {INIT_CMD, 2, { 0x3D, 0x00} }, + {INIT_CMD, 2, { 0x3E, 0x0F} }, + {INIT_CMD, 2, { 0x3F, 0xA4} }, + {INIT_CMD, 2, { 0x40, 0x28} }, + {INIT_CMD, 2, { 0x41, 0xFC} }, + {INIT_CMD, 2, { 0x42, 0x01} }, + {INIT_CMD, 2, { 0x43, 0x08} }, + {INIT_CMD, 2, { 0x44, 0x05} }, + {INIT_CMD, 2, { 0x45, 0xF0} }, + {INIT_CMD, 2, { 0x46, 0x01} }, + {INIT_CMD, 2, { 0x47, 0x02} }, + {INIT_CMD, 2, { 0x48, 0x00} }, + {INIT_CMD, 2, { 0x49, 0x58} }, + {INIT_CMD, 2, { 0x4A, 0x00} }, + {INIT_CMD, 2, { 0x4B, 0x05} }, + {INIT_CMD, 2, { 0x4C, 0x03} }, + {INIT_CMD, 2, { 0x4D, 0xD0} }, + {INIT_CMD, 2, { 0x4E, 0x13} }, + {INIT_CMD, 2, { 0x4F, 0xFF} }, + {INIT_CMD, 2, { 0x50, 0x0A} }, + {INIT_CMD, 2, { 0x51, 0x53} }, + {INIT_CMD, 2, { 0x52, 0x26} }, + {INIT_CMD, 2, { 0x53, 0x22} }, + {INIT_CMD, 2, { 0x54, 0x09} }, + {INIT_CMD, 2, { 0x55, 0x22} }, + {INIT_CMD, 2, { 0x56, 0x00} }, + {INIT_CMD, 2, { 0x57, 0x1C} }, + {INIT_CMD, 2, { 0x58, 0x03} }, + {INIT_CMD, 2, { 0x59, 0x3F} }, + {INIT_CMD, 2, { 0x5A, 0x28} }, + {INIT_CMD, 2, { 0x5B, 0x01} }, + {INIT_CMD, 2, { 0x5C, 0xCC} }, + {INIT_CMD, 2, { 0x5D, 0x21} }, + {INIT_CMD, 2, { 0x5E, 0x04} }, + {INIT_CMD, 2, { 0x5F, 0x13} }, + {INIT_CMD, 2, { 0x60, 0x42} }, + {INIT_CMD, 2, { 0x61, 0x08} }, + {INIT_CMD, 2, { 0x62, 0x64} }, + {INIT_CMD, 2, { 0x63, 0xEB} }, + {INIT_CMD, 2, { 0x64, 0x10} }, + {INIT_CMD, 2, { 0x65, 0xA8} }, + {INIT_CMD, 2, { 0x66, 0x84} }, + {INIT_CMD, 2, { 0x67, 0x8E} }, + {INIT_CMD, 2, { 0x68, 0x29} }, + {INIT_CMD, 2, { 0x69, 0x11} }, + {INIT_CMD, 2, { 0x6A, 0x42} }, + {INIT_CMD, 2, { 0x6B, 0x38} }, + {INIT_CMD, 2, { 0x6C, 0x21} }, + {INIT_CMD, 2, { 0x6D, 0x84} }, + {INIT_CMD, 2, { 0x6E, 0x50} }, + {INIT_CMD, 2, { 0x6F, 0xB6} }, + {INIT_CMD, 2, { 0x70, 0x0E} }, + {INIT_CMD, 2, { 0x71, 0xA1} }, + {INIT_CMD, 2, { 0x72, 0xCE} }, + {INIT_CMD, 2, { 0x73, 0xF8} }, + {INIT_CMD, 2, { 0x74, 0xDA} }, + {INIT_CMD, 2, { 0x75, 0x1A} }, + {INIT_CMD, 2, { 0x76, 0x00} }, + {INIT_CMD, 2, { 0x77, 0x00} }, + {INIT_CMD, 2, { 0x78, 0x5F} }, + {INIT_CMD, 2, { 0x79, 0xE0} }, + {INIT_CMD, 2, { 0x7A, 0x01} }, + {INIT_CMD, 2, { 0x7B, 0xFF} }, + {INIT_CMD, 2, { 0x7C, 0xFF} }, + {INIT_CMD, 2, { 0x7D, 0xFF} }, + {INIT_CMD, 2, { 0x7E, 0xFF} }, + {INIT_CMD, 2, { 0x7F, 0xFE} }, + {INIT_CMD, 2, { 0xB1, 0x02} }, + {INIT_CMD, 2, { 0x00, 0xFF} }, + {INIT_CMD, 2, { 0x01, 0x01} }, + {INIT_CMD, 2, { 0x02, 0x00} }, + {INIT_CMD, 2, { 0x03, 0x00} }, + {INIT_CMD, 2, { 0x04, 0x00} }, + {INIT_CMD, 2, { 0x05, 0x00} }, + {INIT_CMD, 2, { 0x06, 0x00} }, + {INIT_CMD, 2, { 0x07, 0x00} }, + {INIT_CMD, 2, { 0x08, 0xC0} }, + {INIT_CMD, 2, { 0x09, 0x00} }, + {INIT_CMD, 2, { 0x0A, 0x00} }, + {INIT_CMD, 2, { 0x0B, 0x04} }, + {INIT_CMD, 2, { 0x0C, 0xE6} }, + {INIT_CMD, 2, { 0x0D, 0x0D} }, + {INIT_CMD, 2, { 0x0F, 0x08} }, + {INIT_CMD, 2, { 0x10, 0xE5} }, + {INIT_CMD, 2, { 0x11, 0xA8} }, + {INIT_CMD, 2, { 0x12, 0xEC} }, + {INIT_CMD, 2, { 0x13, 0x54} }, + {INIT_CMD, 2, { 0x14, 0x5A} }, + {INIT_CMD, 2, { 0x15, 0xD5} }, + {INIT_CMD, 2, { 0x16, 0x23} }, + {INIT_CMD, 2, { 0x17, 0x11} }, + {INIT_CMD, 2, { 0x18, 0x2F} }, + {INIT_CMD, 2, { 0x19, 0x93} }, + {INIT_CMD, 2, { 0x1A, 0xA6} }, + {INIT_CMD, 2, { 0x1B, 0x0F} }, + {INIT_CMD, 2, { 0x1C, 0xFF} }, + {INIT_CMD, 2, { 0x1D, 0xFF} }, + {INIT_CMD, 2, { 0x1E, 0xFF} }, + {INIT_CMD, 2, { 0x1F, 0xFF} }, + {INIT_CMD, 2, { 0x20, 0xFF} }, + {INIT_CMD, 2, { 0x21, 0xFF} }, + {INIT_CMD, 2, { 0x22, 0xFF} }, + {INIT_CMD, 2, { 0x23, 0xFF} }, + {INIT_CMD, 2, { 0x24, 0xFF} }, + {INIT_CMD, 2, { 0x25, 0xFF} }, + {INIT_CMD, 2, { 0x26, 0xFF} }, + {INIT_CMD, 2, { 0x27, 0x1F} }, + {INIT_CMD, 2, { 0x28, 0xC8} }, + {INIT_CMD, 2, { 0x29, 0xFF} }, + {INIT_CMD, 2, { 0x2A, 0xFF} }, + {INIT_CMD, 2, { 0x2B, 0xFF} }, + {INIT_CMD, 2, { 0x2C, 0x07} }, + {INIT_CMD, 2, { 0x2D, 0x03} }, + {INIT_CMD, 2, { 0x33, 0x09} }, + {INIT_CMD, 2, { 0x35, 0x7F} }, + {INIT_CMD, 2, { 0x36, 0x0C} }, + {INIT_CMD, 2, { 0x38, 0x7F} }, + {INIT_CMD, 2, { 0x3A, 0x80} }, + {INIT_CMD, 2, { 0x3B, 0x55} }, + {INIT_CMD, 2, { 0x3C, 0xE2} }, + {INIT_CMD, 2, { 0x3D, 0x32} }, + {INIT_CMD, 2, { 0x3E, 0x00} }, + {INIT_CMD, 2, { 0x3F, 0x58} }, + {INIT_CMD, 2, { 0x40, 0x06} }, + {INIT_CMD, 2, { 0x41, 0x80} }, + {INIT_CMD, 2, { 0x42, 0xCB} }, + {INIT_CMD, 2, { 0x43, 0x2C} }, + {INIT_CMD, 2, { 0x44, 0x61} }, + {INIT_CMD, 2, { 0x45, 0x39} }, + {INIT_CMD, 2, { 0x46, 0x00} }, + {INIT_CMD, 2, { 0x47, 0x00} }, + {INIT_CMD, 2, { 0x48, 0x8B} }, + {INIT_CMD, 2, { 0x49, 0xD2} }, + {INIT_CMD, 2, { 0x4A, 0x01} }, + {INIT_CMD, 2, { 0x4B, 0x00} }, + {INIT_CMD, 2, { 0x4C, 0x10} }, + {INIT_CMD, 2, { 0x4D, 0xC0} }, + {INIT_CMD, 2, { 0x4E, 0x0F} }, + {INIT_CMD, 2, { 0x4F, 0xF1} }, + {INIT_CMD, 2, { 0x50, 0x78} }, + {INIT_CMD, 2, { 0x51, 0x7A} }, + {INIT_CMD, 2, { 0x52, 0x34} }, + {INIT_CMD, 2, { 0x53, 0x99} }, + {INIT_CMD, 2, { 0x54, 0xA2} }, + {INIT_CMD, 2, { 0x55, 0x03} }, + {INIT_CMD, 2, { 0x56, 0x6C} }, + {INIT_CMD, 2, { 0x57, 0x1A} }, + {INIT_CMD, 2, { 0x58, 0x05} }, + {INIT_CMD, 2, { 0x59, 0x30} }, + {INIT_CMD, 2, { 0x5A, 0x1E} }, + {INIT_CMD, 2, { 0x5B, 0x8F} }, + {INIT_CMD, 2, { 0x5C, 0xC7} }, + {INIT_CMD, 2, { 0x5D, 0xE3} }, + {INIT_CMD, 2, { 0x5E, 0xF1} }, + {INIT_CMD, 2, { 0x5F, 0x78} }, + {INIT_CMD, 2, { 0x60, 0x3C} }, + {INIT_CMD, 2, { 0x61, 0x36} }, + {INIT_CMD, 2, { 0x62, 0x1E} }, + {INIT_CMD, 2, { 0x63, 0x1B} }, + {INIT_CMD, 2, { 0x64, 0x8F} }, + {INIT_CMD, 2, { 0x65, 0xC7} }, + {INIT_CMD, 2, { 0x66, 0xE3} }, + {INIT_CMD, 2, { 0x67, 0x31} }, + {INIT_CMD, 2, { 0x68, 0x14} }, + {INIT_CMD, 2, { 0x69, 0x89} }, + {INIT_CMD, 2, { 0x6A, 0x70} }, + {INIT_CMD, 2, { 0x6B, 0x8C} }, + {INIT_CMD, 2, { 0x6C, 0x8D} }, + {INIT_CMD, 2, { 0x6D, 0x8D} }, + {INIT_CMD, 2, { 0x6E, 0x8D} }, + {INIT_CMD, 2, { 0x6F, 0x8D} }, + {INIT_CMD, 2, { 0x70, 0xC7} }, + {INIT_CMD, 2, { 0x71, 0xE3} }, + {INIT_CMD, 2, { 0x72, 0xF1} }, + {INIT_CMD, 2, { 0x73, 0xD8} }, + {INIT_CMD, 2, { 0x74, 0xD8} }, + {INIT_CMD, 2, { 0x75, 0xD8} }, + {INIT_CMD, 2, { 0x76, 0x18} }, + {INIT_CMD, 2, { 0x77, 0x00} }, + {INIT_CMD, 2, { 0x78, 0x00} }, + {INIT_CMD, 2, { 0x79, 0x00} }, + {INIT_CMD, 2, { 0x7A, 0xC6} }, + {INIT_CMD, 2, { 0x7B, 0xC6} }, + {INIT_CMD, 2, { 0x7C, 0xC6} }, + {INIT_CMD, 2, { 0x7D, 0xC6} }, + {INIT_CMD, 2, { 0x7E, 0xC6} }, + {INIT_CMD, 2, { 0x7F, 0xE3} }, + {INIT_CMD, 2, { 0x0B, 0x04} }, + {INIT_CMD, 2, { 0xB1, 0x03} }, + {INIT_CMD, 2, { 0x2C, 0x2C} }, + {INIT_CMD, 2, { 0xB1, 0x00} }, + {INIT_CMD, 2, { 0x89, 0x03} }, + {INIT_CMD, 1, {0x11} }, + {DELAY_CMD, 0x78, {} }, + {INIT_CMD, 1, {0x29} }, + {DELAY_CMD, 0x14, {} }, +}; + +struct panel_info flapjack_panel_info[] = { + PANEL(PANEL_FLAPJACK_BOE_TV101WUM_NG0, + 74000, + flapjack_boe_tv101wum_edid, + boe_tv101wum_lcm_init_cmd), + PANEL(PANEL_FLAPJACK_BOE_TV080WUM_NG0, + 212000, + flapjack_boe_tv080wum_edid, + boe_tv080wum_lcm_init_cmd), + PANEL(PANEL_FLAPJACK_INX_OTA7290D10P, + 1191000, + flapjack_inx_ota7290d10p_edid, + inx_ota7290d10p_lcm_init_cmd), + PANEL(PANEL_FLAPJACK_AUO_NT51021D8P, + 1027000, + flapjack_auo_nt51021d8p_edid, + auo_nt51021d8p_lcm_init_cmd), + {{PANEL_FLAPJACK_UNKNOWN}, "PANEL_FLAPJACK_UNKNOWN", + 0, NULL, NULL, 0}, +}; + +static union panel_id get_panel_id_from_adc(int channel, + struct board_display_intf *intf) +{ + uint32_t ver = board_id(); + + if (ver == BOARD_ID_UNKNOWN || ver < 3) { + int id; + int value = auxadc_get_voltage(channel); + + for (id = 0; id < intf->all_panel_info_size; id++) { + if (ABS(value - intf->all_panel_info[id].voltage) < tolerance) + return intf->all_panel_info[id].disp_id; + } + + return (union panel_id)PANEL_FLAPJACK_UNKNOWN; + } else + return (union panel_id)((sku_id() >> FLAPJACK_PANEL_ID_BIT_POSITION) & 0xf); +} + + +static union panel_id flapjack_get_panel_id(struct board_display_intf *intf) +{ + union panel_id id; + + id = get_panel_id_from_adc(FLAPJACK_PANEL_ADC_ID, + intf); + return id; +}; + +static bool flapjack_is_panel_id_valid(union panel_id id) +{ + if (id.value < PANEL_FLAPJACK_UNKNOWN) + return true; + return false; +}; + +static int flapjack_backlight(struct board_display_intf *intf) +{ + configure_backlight(); + return 0; +}; + +static int flapjack_power(struct board_display_intf *intf) +{ + int result = 0; + switch (intf->cur_panel_info->disp_id.value) { + case PANEL_FLAPJACK_BOE_HIMAX8279D10P: + case PANEL_FLAPJACK_BOE_HIMAX8279D8P: + case PANEL_FLAPJACK_INX_OTA7290D10P: + case PANEL_FLAPJACK_AUO_NT51021D8P: + gpio_output(PP3300_LCM_EN, 1); + gpio_output(PP1800_LCM_EN, 1); + + gpio_output(GPIO(LCM_RST), 0); + mdelay(20); + gpio_output(GPIO(LCM_RST), 1); + mdelay(10); + break; + case PANEL_FLAPJACK_UNKNOWN: + default: + result = ERR; + break; + } + return result; +}; + +struct board_display_intf flapjack_display_intf = { + .board = "flapjack", + .all_panel_info = flapjack_panel_info, + .all_panel_info_size = ARRAY_SIZE(flapjack_panel_info), + .cur_panel_info = NULL, + .get_panel_id = &flapjack_get_panel_id, + .is_panel_id_valid = &flapjack_is_panel_id_valid, + .backlight = &flapjack_backlight, + .power = &flapjack_power, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/32840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e50df59de3db9ed6efcccbd01b553c21f793a3f Gerrit-Change-Number: 32840 Gerrit-PatchSet: 1 Gerrit-Owner: Jerry Han <hanxu5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

6 6

Change in ...coreboot[master]: soc/intel/braswell: select SOUTHBRIDGE_INTEL_COMMON
by Arthur Heymans (Code Review) 07 Aug '23

07 Aug '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33204 Change subject: soc/intel/braswell: select SOUTHBRIDGE_INTEL_COMMON ...................................................................... soc/intel/braswell: select SOUTHBRIDGE_INTEL_COMMON Use the sb/intel/common/reset.c implementation. Change-Id: I9342f16c947d5e5eb768e426c5ab95c372f95c76 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/braswell/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/33204/1 diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index ed5c972..b2702f0 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -33,7 +33,6 @@ select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_HDA - select SOC_INTEL_COMMON_RESET select SMM_TSEG select SMP select SPI_FLASH @@ -50,6 +49,7 @@ select INTEL_GMA_ACPI select INTEL_GMA_SWSMISCI select CPU_INTEL_COMMON + select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS config VBOOT -- To view, visit https://review.coreboot.org/c/coreboot/+/33204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9342f16c947d5e5eb768e426c5ab95c372f95c76 Gerrit-Change-Number: 33204 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: soc/intel/cannonlake: Disable PCH thermal sensor check during S0ix
by Sumeet R Pawnikar (Code Review) 07 Aug '23

07 Aug '23

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33292 Change subject: soc/intel/cannonlake: Disable PCH thermal sensor check during S0ix ...................................................................... soc/intel/cannonlake: Disable PCH thermal sensor check during S0ix This disables PCH thermal sensor check during system entry in S0ix state. BUG=133345634 BRANCH=None TEST=Verified S0ix entry with Thermal sensor disabled. Change-Id: I298079e91bfea87ba02a8a32a622f2b0bbfc31a6 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/include/soc/pmc.h 2 files changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/33292/1 diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 4dfd15b..b2f3d48 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -81,7 +81,7 @@ /* Disable XTAL shutdown qualification for low power idle. */ if (config->s0ix_enable) { reg32 = read32(pmcbase + CPPMVRIC); - reg32 |= XTALSDQDIS; + reg32 |= (XTALSDQDIS | TSDQDIS); write32(pmcbase + CPPMVRIC, reg32); } diff --git a/src/soc/intel/cannonlake/include/soc/pmc.h b/src/soc/intel/cannonlake/include/soc/pmc.h index 67854d4..b4110cf 100644 --- a/src/soc/intel/cannonlake/include/soc/pmc.h +++ b/src/soc/intel/cannonlake/include/soc/pmc.h @@ -150,6 +150,7 @@ #define CPPMVRIC 0x1B1C #define XTALSDQDIS (1 << 22) +#define TSDQDIS (1 << 26) #define IRQ_REG ACTL #define SCI_IRQ_ADJUST 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/33292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I298079e91bfea87ba02a8a32a622f2b0bbfc31a6 Gerrit-Change-Number: 33292 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

3 4

Change in ...coreboot[master]: commonlib: reliicense to for > GPL-2
by Aaron Durbin (Code Review) 07 Aug '23

07 Aug '23

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33367 Change subject: commonlib: reliicense to for > GPL-2 ...................................................................... commonlib: reliicense to for > GPL-2 Allow compatibility with > GPL-2 code bases such that the current implementations of: - iobuf - mem_pol - region can be utilitized in other projects. Change-Id: If4d947d87bf04313a956e2bece9399c3dc770f19 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/commonlib/include/commonlib/iobuf.h M src/commonlib/include/commonlib/mem_pool.h M src/commonlib/include/commonlib/region.h M src/commonlib/iobuf.c M src/commonlib/mem_pool.c M src/commonlib/region.c 6 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/33367/1 diff --git a/src/commonlib/include/commonlib/iobuf.h b/src/commonlib/include/commonlib/iobuf.h index c5a0f4c..fee789e 100644 --- a/src/commonlib/include/commonlib/iobuf.h +++ b/src/commonlib/include/commonlib/iobuf.h @@ -5,7 +5,7 @@ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * the Free Software Foundation; version 2 or later of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of diff --git a/src/commonlib/include/commonlib/mem_pool.h b/src/commonlib/include/commonlib/mem_pool.h index c21fa0e..0b6f08c 100644 --- a/src/commonlib/include/commonlib/mem_pool.h +++ b/src/commonlib/include/commonlib/mem_pool.h @@ -5,7 +5,7 @@ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * the Free Software Foundation; version 2 or later of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h index 45484dd..efb7931 100644 --- a/src/commonlib/include/commonlib/region.h +++ b/src/commonlib/include/commonlib/region.h @@ -5,7 +5,7 @@ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * the Free Software Foundation; version 2 or later of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of diff --git a/src/commonlib/iobuf.c b/src/commonlib/iobuf.c index b73ee19..219d692 100644 --- a/src/commonlib/iobuf.c +++ b/src/commonlib/iobuf.c @@ -5,7 +5,7 @@ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * the Free Software Foundation; version 2 or later of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of diff --git a/src/commonlib/mem_pool.c b/src/commonlib/mem_pool.c index cb3e726..69b1160 100644 --- a/src/commonlib/mem_pool.c +++ b/src/commonlib/mem_pool.c @@ -5,7 +5,7 @@ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * the Free Software Foundation; version 2 or later of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of diff --git a/src/commonlib/region.c b/src/commonlib/region.c index 541a125..8840ecd 100644 --- a/src/commonlib/region.c +++ b/src/commonlib/region.c @@ -5,7 +5,7 @@ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. + * the Free Software Foundation; version 2 or later of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of -- To view, visit https://review.coreboot.org/c/coreboot/+/33367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If4d947d87bf04313a956e2bece9399c3dc770f19 Gerrit-Change-Number: 33367 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

5 7

Change in ...coreboot[master]: Documentation: Convert cbfs.txt to markdown
by Patrick Rudolph (Code Review) 07 Aug '23

07 Aug '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33663 Change subject: Documentation: Convert cbfs.txt to markdown ...................................................................... Documentation: Convert cbfs.txt to markdown Convert the document to markdown. Needs to be fixed in a separate commit as it doesn't reflect coreboot v4. Change-Id: I0fb2713a9cda08e528902ec641dd4a4e0dc148fe Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- A Documentation/lib/cbfs.md M Documentation/lib/index.md 2 files changed, 372 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/33663/1 diff --git a/Documentation/lib/cbfs.md b/Documentation/lib/cbfs.md new file mode 100644 index 0000000..83d8b44 --- /dev/null +++ b/Documentation/lib/cbfs.md @@ -0,0 +1,371 @@ +# coreboot CBFS Specification +by Jordan Crouse <jordan(a)cosmicpenguin.net> + +**WARNING: This documentation is written against coreboot v1.** + +**TODO: Update this document ASAP** + +## Introduction + +This document describes the coreboot CBFS specification (from here +referred to as CBFS). CBFS is a scheme for managing independent chunks +of data in a system ROM. Though not a true filesystem, the style and +concepts are similar. + + +## Architecture + +The CBFS architecture looks like the following: + +``` +/---------------\ <-- Start of ROM +| /-----------\ | --| +| | Header | | | +| |-----------| | | +| | Name | | |-- Component +| |-----------| | | +| |Data | | | +| |.. | | | +| \-----------/ | --| +| | +| /-----------\ | +| | Header | | +| |-----------| | +| | Name | | +| |-----------| | +| |Data | | +| |.. | | +| \-----------/ | +| | +| ... | +| /-----------\ | +| | | | +| | Bootblock | | +| | --------- | | +| | Reset | | <- 0xFFFFFFF0 +| \-----------/ | +\---------------/ +``` + +The CBFS architecture consists of a binary associated with a physical +ROM disk referred hereafter as the ROM. A number of independent of +components, each with a header prepended on to data are located within +the ROM. The components are nominally arranged sequentially, though they +are aligned along a pre-defined boundary. + +The bootblock occupies the last 20k of the ROM. Within +the bootblock is a master header containing information about the ROM +including the size, alignment of the components, and the offset of the +start of the first CBFS component within the ROM. + +## Master Header + +The master header contains essential information about the ROM that is +used by both the CBFS implementation within coreboot at runtime as well +as host based utilities to create and manage the ROM. The master header +will be located somewhere within the bootblock (last 20k of the ROM). A +pointer to the location of the header will be located at offset +-4 from the end of the ROM. This translates to address 0xFFFFFFFC on a +normal x86 system. The pointer will be to physical memory somewhere +between - 0xFFFFB000 and 0xFFFFFFF0. This makes it easier for coreboot +to locate the header at run time. Build time utilities will +need to read the pointer and do the appropriate math to locate the header. + +The following is the structure of the master header: + +```c +struct cbfs_header { + u32 magic; + u32 version; + u32 romsize; + u32 bootblocksize; + u32 align; + u32 offset; + u32 architecture; + u32 pad[1]; +} __packed; +``` + +The meaning of each member is as follows: + +`magic` is a 32 bit number that identifies the ROM as a CBFS type. The +magic +number is 0x4F524243, which is 'ORBC' in ASCII. + +`version` is a version number for CBFS header. cbfs_header structure may be +different if version is not matched. + +`romsize` is the size of the ROM in bytes. coreboot will subtract 'size' from +0xFFFFFFFF to locate the beginning of the ROM in memory. + +`bootblocksize` is the size of bootblock reserved in firmware image. + +`align` is the number of bytes that each component is aligned to within the +ROM. This is used to make sure that each component is aligned correctly +with +regards to the erase block sizes on the ROM - allowing one to replace a +component at runtime without disturbing the others. + +`offset` is the offset of the first CBFS component (from the start of +the ROM). This is to allow for arbitrary space to be left at the beginning +of the ROM for things like embedded controller firmware. + +`architecture` describes which architecture (x86, arm, ...) this CBFS is created +for. + +## Bootblock +The bootblock is a mandatory component in the ROM. It is located in the +last 20k of the ROM space, and contains, among other things, the location of the +master header and the entry point for the loader firmware. The bootblock +does not have a component header attached to it. + +## Components + +CBFS components are placed in the ROM starting at 'offset' specified in +the master header and ending at the bootblock. Thus the total size +available for components in the ROM is (ROM size - 20k - 'offset'). +Each CBFS component is to be aligned according to the 'align' value in the +header. +Thus, if a component of size 1052 is located at offset 0 with an 'align' +value of 1024, the next component will be located at offset 2048. + +Each CBFS component will be indexed with a unique ASCII string name of +unlimited size. + +Each CBFS component starts with a header: + +```c +struct cbfs_file { + char magic[8]; + unsigned int len; + unsigned int type; + unsigned int checksum; + unsigned int offset; +}; +``` + +`magic` is a magic value used to identify the header. During runtime, +coreboot will scan the ROM looking for this value. The default magic is +the string 'LARCHIVE'. + +`len` is the length of the data, not including the size of the header and +the size of the name. + +`type` is a 32 bit number indicating the type of data that is attached. +The data type is used in a number of ways, as detailed in the section +below. + +`checksum` is a 32bit checksum of the entire component, including the +header and name. + +`offset` is the start of the component data, based off the start of the +header. +The difference between the size of the header and offset is the size of the +component name. + +Immediately following the header will be the name of the component, +which will null terminated and 16 byte aligned. The following picture shows the +structure of the header: + +``` +/--------\ <- start +| Header | +|--------| <- sizeof(struct cbfs_file) +| Name | +|--------| <- 'offset' +| Data | +| ... | +\--------/ <- start + 'offset' + 'len' +``` + +### Searching Algorithm + +To locate a specific component in the ROM, one starts at the 'offset' +specified in the CBFS master header. For this example, the offset will +be 0. + +From that offset, the code should search for the magic string on the +component, jumping 'align' bytes each time. So, assuming that 'align' is +16, the code will search for the string 'LARCHIVE' at offset 0, 16, 32, etc. +If the offset ever exceeds the allowable range for CBFS components, then no +component was found. + +Upon recognizing a component, the software then has to search for the +specific name of the component. This is accomplished by comparing the +desired name with the string on the component located at +`offset + sizeof(struct cbfs_file)`. If the string matches, then the +component has been located, otherwise the software should add +`'offset' + 'len'` to the offset and resume the search for the magic value. + +### Data Types + +The 'type' member of struct cbfs_file is used to identify the content +of the component data, and is used by coreboot and other +run-time entities to make decisions about how to handle the data. + +There are three component types that are essential to coreboot, and so +are defined here. + +#### Stages + +Stages are code loaded by coreboot during the boot process. They are +essential to a successful boot. Stages are comprised of a single blob +of binary data that is to be loaded into a particular location in memory +and executed. The uncompressed header contains information about how +large the data is, and where it should be placed, and what additional memory +needs to be cleared. + +Stages are assigned a component value of 0x10. When coreboot sees this +component type, it knows that it should pass the data to a sub-function +that will process the stage. + +The following is the format of a stage component: + +``` +/--------\ +| Header | +|--------| +| Binary | +| .. | +\--------/ +``` + +The header is defined as: + +```c +struct cbfs_stage { + unsigned int compression; + unsigned long long entry; + unsigned long long load; + unsigned int len; + unsigned int memlen; +}; +``` + +`compression` is an integer defining how the data is compressed. There +are three compression types defined by this version of the standard: +none (0x0), lzma (0x1), and nrv2b (0x02, deprecated), though additional +types may be added assuming that coreboot understands how to handle the scheme. + +`entry` is a 64 bit value indicating the location where the program +counter should jump following the loading of the stage. This should be +an absolute physical memory address. + +`load` is a 64 bit value indicating where the subsequent data should be +loaded. This should be an absolute physical memory address. + +`len` is the length of the compressed data in the component. + +`memlen` is the amount of memory that will be used by the component when +it is loaded. + +The component data will start immediately following the header. + +When coreboot loads a stage, it will first zero the memory from 'load' to +'memlen'. It will then decompress the component data according to the +specified scheme and place it in memory starting at 'load'. Following that, +it will jump execution to the address specified by 'entry'. +Some components are designed to execute directly from the ROM - coreboot +knows which components must do that and will act accordingly. + +#### Payloads + +Payloads are loaded by coreboot following the boot process. + +Stages are assigned a component value of 0x20. When coreboot sees this +component type, it knows that it should pass the data to a sub-function +that will process the payload. Furthermore, other run time applications such +as 'bayou' may easily index all available payloads +on the system by searching for the payload type. + + +The following is the format of a stage component: + +``` +/-----------\ +| Header | +| Segment 1 | +| Segment 2 | +| ... | +|-----------| +| Binary | +| .. | +\-----------/ +``` + +The header is as follows: + +```c +struct cbfs_payload { + struct cbfs_payload_segment segments; +} +``` + +The header contains a number of segments corresponding to the segments +that need to be loaded for the payload. + +The following is the structure of each segment header: + +```c +struct cbfs_payload_segment { + unsigned int type; + unsigned int compression; + unsigned int offset; + unsigned long long load_addr; + unsigned int len; + unsigned int mem_len; +}; +``` + +`type` is the type of segment, one of the following: + +```eval_rst ++----------------------+-------------+---------------------------------------+ +|PAYLOAD_SEGMENT_CODE | 0x45444F43 | The segment contains executable code | ++----------------------+-------------+---------------------------------------+ +|PAYLOAD_SEGMENT_DATA | 0x41544144 | The segment contains data | ++----------------------+-------------+---------------------------------------+ +|PAYLOAD_SEGMENT_BSS | 0x20535342 | The memory specified by the segment | +| | | should be zeroed | ++----------------------+-------------+---------------------------------------+ +|PAYLOAD_SEGMENT_PARAMS| 0x41524150 | The segment contains information for | +| | | the payload | ++----------------------+-------------+---------------------------------------+ +|PAYLOAD_SEGMENT_ENTRY | 0x52544E45 | The segment contains the entry point | +| | | for the payload | ++----------------------+-------------+---------------------------------------+ +``` + +`compression` is the compression scheme for the segment. Each segment can +be independently compressed. There are three compression types defined by +this version of the standard: none (0x0), lzma (0x1), and nrv2b +(0x02, deprecated), though additional types may be added assuming that +coreboot understands how to handle the scheme. + +`offset` is the address of the data within the component, starting from +the component header. + +`load_addr` is a 64 bit value indicating where the segment should be placed +in memory. + +`len` is a 32 bit value indicating the size of the segment within the +component. + +`mem_len` is the size of the data when it is placed into memory. + +The data will located immediately following the last segment. + +#### Option ROMS + +The third specified component type will be Option ROMs. Option ROMS will +have component type '0x30'. They will have no additional header, the +uncompressed binary data will be located in the data portion of the +component. + +#### NULL + +There is a 4th component type ,defined as NULL (0xFFFFFFFF). This is +the "don't care" component type. This can be used when the component +type is not necessary (such as when the name of the component is unique. +i.e. option_table). It is recommended that all components be assigned a +unique type, but NULL can be used when the type does not matter. diff --git a/Documentation/lib/index.md b/Documentation/lib/index.md index 99b8061..808bac8 100644 --- a/Documentation/lib/index.md +++ b/Documentation/lib/index.md @@ -6,4 +6,5 @@ ## Structure and layout - [Flashmap and Flashmap Descriptor](flashmap.md) - [ABI data consumption](abi-data-consumption.md) +- [CBFS](cbfs.md) - [Timestamps](timestamp.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/33663 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fb2713a9cda08e528902ec641dd4a4e0dc148fe Gerrit-Change-Number: 33663 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 4

Change in coreboot[master]: new file: toshiba/Kconfig new file: toshiba/Kconfig.name new f...
by franlego98 franlego98 (Code Review) 07 Aug '23

07 Aug '23

franlego98 franlego98 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34138 ) Change subject: new file: toshiba/Kconfig new file: toshiba/Kconfig.name new file: toshiba/satellite_u940/Kconfig new file: toshiba/satellite_u940/Kconfig.name new file: toshiba/satellite_u940/Makefile.inc new file: toshiba/satellite_u940/acpi/ec.asl new file: toshiba/satellite_u940/acpi/platform.asl new file: toshiba/satellite_u940/acpi/superio.asl new file: toshiba/satellite_u940/acpi_tables.c new file: toshiba/satellite_u940/board_info.txt new file: toshiba/satellite_u940/devicetree.cb new file: toshiba/satellite_u940/dsdt.asl new file: toshiba/satellite_u940/gma-mainboard.ads new file: toshiba/satellite_u940/gpio.c new file: toshiba/satellite_u940/hda_verb.c new file: toshiba/satellite_u940/mainboard.c new file: toshiba/satellite_u940/romstage.c ...................................................................... new file: toshiba/Kconfig new file: toshiba/Kconfig.name new file: toshiba/satellite_u940/Kconfig new file: toshiba/satellite_u940/Kconfig.name new file: toshiba/satellite_u940/Makefile.inc new file: toshiba/satellite_u940/acpi/ec.asl new file: toshiba/satellite_u940/acpi/platform.asl new file: toshiba/satellite_u940/acpi/superio.asl new file: toshiba/satellite_u940/acpi_tables.c new file: toshiba/satellite_u940/board_info.txt new file: toshiba/satellite_u940/devicetree.cb new file: toshiba/satellite_u940/dsdt.asl new file: toshiba/satellite_u940/gma-mainboard.ads new file: toshiba/satellite_u940/gpio.c new file: toshiba/satellite_u940/hda_verb.c new file: toshiba/satellite_u940/mainboard.c new file: toshiba/satellite_u940/romstage.c Change-Id: If87c327cd15fe44479d6738c45acbd510873d994 --- A src/mainboard/toshiba/Kconfig A src/mainboard/toshiba/Kconfig.name A src/mainboard/toshiba/satellite_u940/Kconfig A src/mainboard/toshiba/satellite_u940/Kconfig.name A src/mainboard/toshiba/satellite_u940/Makefile.inc A src/mainboard/toshiba/satellite_u940/acpi/ec.asl A src/mainboard/toshiba/satellite_u940/acpi/platform.asl A src/mainboard/toshiba/satellite_u940/acpi/superio.asl A src/mainboard/toshiba/satellite_u940/acpi_tables.c A src/mainboard/toshiba/satellite_u940/board_info.txt A src/mainboard/toshiba/satellite_u940/devicetree.cb A src/mainboard/toshiba/satellite_u940/dsdt.asl A src/mainboard/toshiba/satellite_u940/gma-mainboard.ads A src/mainboard/toshiba/satellite_u940/gpio.c A src/mainboard/toshiba/satellite_u940/hda_verb.c A src/mainboard/toshiba/satellite_u940/mainboard.c A src/mainboard/toshiba/satellite_u940/romstage.c 17 files changed, 836 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/34138/1 diff --git a/src/mainboard/toshiba/Kconfig b/src/mainboard/toshiba/Kconfig new file mode 100644 index 0000000..1466d64 --- /dev/null +++ b/src/mainboard/toshiba/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_TOSHIBA + +choice + prompt "Mainboard model" + +source "src/mainboard/toshiba/*/Kconfig.name" + +endchoice + +source "src/mainboard/toshiba/*/Kconfig" + +config MAINBOARD_TOSHIBA + string + default "TOSHIBA" + +endif # VENDOR_TOSHIBA diff --git a/src/mainboard/toshiba/Kconfig.name b/src/mainboard/toshiba/Kconfig.name new file mode 100644 index 0000000..47dbb59 --- /dev/null +++ b/src/mainboard/toshiba/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_TOSHIBA + bool "TOSHIBA" diff --git a/src/mainboard/toshiba/satellite_u940/Kconfig b/src/mainboard/toshiba/satellite_u940/Kconfig new file mode 100644 index 0000000..9a13486 --- /dev/null +++ b/src/mainboard/toshiba/satellite_u940/Kconfig @@ -0,0 +1,48 @@ +if BOARD_TOSHIBA_SATELLITE_U940 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_2048 # FIXME: correct this + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + +config MAINBOARD_DIR + string + default toshiba/satellite_u940 + +config MAINBOARD_PART_NUMBER + string + default "SATELLITE U940" + +config MAINBOARD_VENDOR + string + default "TOSHIBA" + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +config VGA_BIOS_ID + string + default "8086,0166" + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/toshiba/satellite_u940/Kconfig.name b/src/mainboard/toshiba/satellite_u940/Kconfig.name new file mode 100644 index 0000000..d347bc8 --- /dev/null +++ b/src/mainboard/toshiba/satellite_u940/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_TOSHIBA_SATELLITE_U940 + bool "SATELLITE U940" diff --git a/src/mainboard/toshiba/satellite_u940/Makefile.inc b/src/mainboard/toshiba/satellite_u940/Makefile.inc new file mode 100644 index 0000000..ebe01ae --- /dev/null +++ b/src/mainboard/toshiba/satellite_u940/Makefile.inc @@ -0,0 +1,2 @@ +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/toshiba/satellite_u940/acpi/ec.asl b/src/mainboard/toshiba/satellite_u940/acpi/ec.asl new file mode 100644 index 0000000..8da2182 --- /dev/null +++ b/src/mainboard/toshiba/satellite_u940/acpi/ec.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device(EC) +{ + Name (_HID, EISAID("PNP0C09")) + Name (_UID, 0) + Name (_GPE, 23) +/* FIXME: EC support */ +} diff --git a/src/mainboard/toshiba/satellite_u940/acpi/platform.asl b/src/mainboard/toshiba/satellite_u940/acpi/platform.asl new file mode 100644 index 0000000..c34ed7d --- /dev/null +++ b/src/mainboard/toshiba/satellite_u940/acpi/platform.asl @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + /* FIXME: EC support */ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + /* FIXME: EC support */ +} diff --git a/src/mainboard/toshiba/satellite_u940/acpi/superio.asl b/src/mainboard/toshiba/satellite_u940/acpi/superio.asl new file mode 100644 index 0000000..4ede634 --- /dev/null +++ b/src/mainboard/toshiba/satellite_u940/acpi/superio.asl @@ -0,0 +1,18 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/toshiba/satellite_u940/acpi_tables.c b/src/mainboard/toshiba/satellite_u940/acpi_tables.c new file mode 100644 index 0000000..6b731cc --- /dev/null +++ b/src/mainboard/toshiba/satellite_u940/acpi_tables.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/toshiba/satellite_u940/board_info.txt b/src/mainboard/toshiba/satellite_u940/board_info.txt new file mode 100644 index 0000000..db677c6 --- /dev/null +++ b/src/mainboard/toshiba/satellite_u940/board_info.txt @@ -0,0 +1,2 @@ +Category: laptop +FIXME: put ROM package, ROM socketed, ROM protocol, Flashrom support, Release year diff --git a/src/mainboard/toshiba/satellite_u940/devicetree.cb b/src/mainboard/toshiba/satellite_u940/devicetree.cb new file mode 100644 index 0000000..d1b5780 --- /dev/null +++ b/src/mainboard/toshiba/satellite_u940/devicetree.cb @@ -0,0 +1,116 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "0" + register "gpu_cpu_backlight" = "0x00000000" + register "gpu_dp_b_hotplug" = "0" + register "gpu_dp_c_hotplug" = "0" + register "gpu_dp_d_hotplug" = "0" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_panel_power_backlight_on_delay" = "0" + register "gpu_panel_power_cycle_delay" = "0" + register "gpu_panel_power_down_delay" = "0" + register "gpu_panel_power_up_delay" = "0" + register "gpu_pch_backlight" = "0x00000000" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "1" + register "gen1_dec" = "0x00040069" + register "gen2_dec" = "0x0004fd61" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x00000000" + register "gpi7_routing" = "2" + register "p_cnt_throttling_supported" = "0" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3" + register "spi_lvscc" = "0x0" + register "spi_uvscc" = "0x0" + register "superspeed_capable_ports" = "0x0000000f" + register "xhci_overcurrent_mapping" = "0x08040201" + register "xhci_switchable_ports" = "0x0000000f" + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x1179 0xfb30 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1179 0xfb30 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1179 0xfb30 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x1179 0xfb30 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x1179 0xfb30 + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x1179 0xfb30 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1179 0xfb30 + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x1179 0xfb30 + end + device pci 1f.2 on # SATA Controller 1 Unsupported PCI device 8086:282a + subsystemid 0x1179 0xfb30 + end + device pci 1f.3 on # SMBus + subsystemid 0x1179 0xfb30 + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x1179 0xfb10 + end + device pci 01.0 off # PCIe Bridge for discrete graphics + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x1179 0xfb10 + end + end +end diff --git a/src/mainboard/toshiba/satellite_u940/dsdt.asl b/src/mainboard/toshiba/satellite_u940/dsdt.asl new file mode 100644 index 0000000..cdaf16d --- /dev/null +++ b/src/mainboard/toshiba/satellite_u940/dsdt.asl @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/toshiba/satellite_u940/gma-mainboard.ads b/src/mainboard/toshiba/satellite_u940/gma-mainboard.ads new file mode 100644 index 0000000..ce27742 --- /dev/null +++ b/src/mainboard/toshiba/satellite_u940/gma-mainboard.ads @@ -0,0 +1,35 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/toshiba/satellite_u940/gpio.c b/src/mainboard/toshiba/satellite_u940/gpio.c new file mode 100644 index 0000000..44c67ed --- /dev/null +++ b/src/mainboard/toshiba/satellite_u940/gpio.c @@ -0,0 +1,238 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_NATIVE, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_OUTPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio4 = GPIO_LEVEL_LOW, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio20 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio27 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio8 = GPIO_INVERT, + .gpio10 = GPIO_INVERT, + .gpio14 = GPIO_INVERT, + .gpio15 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_NATIVE, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_GPIO, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio34 = GPIO_DIR_OUTPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_OUTPUT, + .gpio43 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio34 = GPIO_LEVEL_LOW, + .gpio37 = GPIO_LEVEL_LOW, + .gpio42 = GPIO_LEVEL_LOW, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_LOW, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_GPIO, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_OUTPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio66 = GPIO_LEVEL_LOW, + .gpio68 = GPIO_LEVEL_LOW, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_LOW, + .gpio74 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/toshiba/satellite_u940/hda_verb.c b/src/mainboard/toshiba/satellite_u940/hda_verb.c new file mode 100644 index 0000000..d1a1cec --- /dev/null +++ b/src/mainboard/toshiba/satellite_u940/hda_verb.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ + 0x1179fb14, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x1179fb14), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x90a60940), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x0421101f), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x0, 0x17, 0x411111f0), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x0, 0x18, 0x04a11830), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x4005822d), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x1179fb30, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x1179fb30), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x58560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x58560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/toshiba/satellite_u940/mainboard.c b/src/mainboard/toshiba/satellite_u940/mainboard.c new file mode 100644 index 0000000..017a577 --- /dev/null +++ b/src/mainboard/toshiba/satellite_u940/mainboard.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/acpi/ec.h> +#include <console/console.h> +#include <pc80/keyboard.h> + +static void mainboard_init(struct device *dev) +{ + /* FIXME: trim this down or remove if necessary */ + { + int i; + const u8 dmp[256] = { + /* 00 */ 0x1b, 0x00, 0x00, 0x00, 0x10, 0x19, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 10 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 20 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 30 */ 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x04, 0x0a, 0x14, 0x00, 0x00, + /* 40 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 50 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 60 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 70 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 80 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 90 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* a0 */ 0x00, 0x00, 0x00, 0x84, 0x81, 0x00, 0x00, 0x61, 0x64, 0x00, 0x00, 0x08, 0x64, 0x19, 0x00, 0x98, + /* b0 */ 0x00, 0x00, 0x00, 0x3a, 0xff, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x1f, 0x00, 0x0b, 0x00, 0x00, + /* c0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* d0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* e0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* f0 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + }; + + printk(BIOS_DEBUG, "Replaying EC dump ..."); + for (i = 0; i < 256; i++) + ec_write (i, dmp[i]); + printk(BIOS_DEBUG, "done\n"); + } + pc_keyboard_init(NO_AUX_DEVICE); +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/toshiba/satellite_u940/romstage.c b/src/mainboard/toshiba/satellite_u940/romstage.c new file mode 100644 index 0000000..b90e7bd --- /dev/null +++ b/src/mainboard/toshiba/satellite_u940/romstage.c @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* FIXME: Check if all includes are needed. */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3c00); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00040069); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x0004fd61); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00000000); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +/* FIXME: Put proper SPD map here. */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/34138 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If87c327cd15fe44479d6738c45acbd510873d994 Gerrit-Change-Number: 34138 Gerrit-PatchSet: 1 Gerrit-Owner: franlego98 franlego98 <new.francisco.1998(a)tuta.io> Gerrit-MessageType: newchange

6 19

← Newer
1
2
3
4
5
6
7
8
...
155
Older →

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2019