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Change in ...coreboot[master]: [UNTESTED]drivers/lenovo/wacom: Move ssdt generator to nsc/pc87382
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33789 Change subject: [UNTESTED]drivers/lenovo/wacom: Move ssdt generator to nsc/pc87382 ...................................................................... [UNTESTED]drivers/lenovo/wacom: Move ssdt generator to nsc/pc87382 This adds a hook to the pc87382 code to specify the ACPI _HID in the case that a wacom device is hooked up to it. TODO: - the wacom code needs to know quite a lot about the SIO and has weird Kconfig hooks to force stuff that is bound to no work. - Add a function to detect the sio and disable it, if not found. Change-Id: Ic1bfebcdaf19798e5ca2fe6c96ac1f9f4cf73e9b Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/lenovo/wacom.c M src/mainboard/lenovo/x200/mainboard.c M src/mainboard/lenovo/x201/mainboard.c M src/mainboard/lenovo/x60/mainboard.c M src/superio/nsc/pc87382/pc87382.h M src/superio/nsc/pc87382/superio.c 6 files changed, 66 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/33789/1 diff --git a/src/drivers/lenovo/wacom.c b/src/drivers/lenovo/wacom.c index dfbd840..45395d3 100644 --- a/src/drivers/lenovo/wacom.c +++ b/src/drivers/lenovo/wacom.c @@ -21,6 +21,7 @@ #include <device/device.h> #include <device/pnp.h> #include <string.h> +#include <superio/nsc/pc87382/pc87382.h> #include "lenovo.h" #include "drivers/i2c/at24rf08c/lenovo.h" @@ -84,28 +85,10 @@ return (result = 0); } -void drivers_lenovo_serial_ports_ssdt_generate(const char *scope) +const char *nsc_pc87382_sp1_acpi_hid(void) { - acpigen_write_scope(scope); - - if (drivers_lenovo_is_wacom_present()) { - acpigen_write_device("DTR"); - - acpigen_write_name("_HID"); - acpigen_emit_eisaid("WACF004"); - - acpigen_write_name("_CRS"); - - acpigen_write_resourcetemplate_header(); - acpigen_write_io16(0x200, 0x200, 1, 8, 1); - acpigen_write_irq((1 << 5)); - - acpigen_write_resourcetemplate_footer(); - - acpigen_write_STA(0xf); - - acpigen_pop_len(); - } - - acpigen_pop_len(); + if (drivers_lenovo_is_wacom_present()) + return "WACF004"; + else + return "PNP0501"; } diff --git a/src/mainboard/lenovo/x200/mainboard.c b/src/mainboard/lenovo/x200/mainboard.c index bcb94b1..2e65e56 100644 --- a/src/mainboard/lenovo/x200/mainboard.c +++ b/src/mainboard/lenovo/x200/mainboard.c @@ -17,18 +17,11 @@ #include <drivers/intel/gma/int15.h> #include <drivers/lenovo/lenovo.h> -static void fill_ssdt(struct device *device) -{ - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB"); -} - static void mainboard_enable(struct device *dev) { install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 2); - - dev->ops->acpi_fill_ssdt_generator = fill_ssdt; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 8cd87aa..87a2f0e 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -56,17 +56,11 @@ printk(BIOS_SPEW, "SPI configured\n"); } -static void fill_ssdt(struct device *device) -{ - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB"); -} - static void mainboard_enable(struct device *dev) { u16 pmbase; dev->ops->init = mainboard_init; - dev->ops->acpi_fill_ssdt_generator = fill_ssdt; pmbase = pci_read_config32(pcidev_on_root(0x1f, 0), PMBASE) & 0xff80; diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 9febea5..acf63cb 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -113,15 +113,9 @@ } } -static void fill_ssdt(struct device *device) -{ - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB"); -} - static void mainboard_enable(struct device *dev) { dev->ops->init = mainboard_init; - dev->ops->acpi_fill_ssdt_generator = fill_ssdt; } struct chip_operations mainboard_ops = { diff --git a/src/superio/nsc/pc87382/pc87382.h b/src/superio/nsc/pc87382/pc87382.h index 6826f45..480a646 100644 --- a/src/superio/nsc/pc87382/pc87382.h +++ b/src/superio/nsc/pc87382/pc87382.h @@ -21,4 +21,6 @@ #define PC87382_SP1 0x03 #define PC87382_GPIO 0x07 #define PC87382_DOCK 0x19 + +const char *nsc_pc87382_sp1_acpi_hid(void); #endif diff --git a/src/superio/nsc/pc87382/superio.c b/src/superio/nsc/pc87382/superio.c index 7c04023..4d270c0 100644 --- a/src/superio/nsc/pc87382/superio.c +++ b/src/superio/nsc/pc87382/superio.c @@ -14,6 +14,8 @@ * GNU General Public License for more details. */ +#include <arch/acpigen.h> +#include <console/console.h> #include <device/device.h> #include <device/pnp.h> #include <stdlib.h> @@ -33,12 +35,68 @@ } } +__weak const char *nsc_pc87382_sp1_acpi_hid(void) +{ + return "PNP0501"; +} + +#if CONFIG(HAVE_ACPI_TABLES) +static void pc87382_ssdt(struct device *dev) +{ + struct resource *io_res; + struct resource *irq_res; + + const char *scope = acpi_device_path(dev); + if (!scope) { + printk(BIOS_ERR, "%s: Missing ACPI scope\n", dev_path(dev)); + return; + } + + acpigen_write_scope(scope); + + switch (dev->path.pnp.device) { + case PC87382_SP1: + io_res = find_resource(dev, PNP_IDX_IO0); + if (!io_res || !io_res->base) { + printk(BIOS_ERR, "PC87382: LDN%u IOBASE not set.\n", + PC87382_SP1); + break; + } + irq_res = find_resource(dev, PNP_IDX_IRQ0); + if (!irq_res || !irq_res->base) { + printk(BIOS_ERR, "PC87382: LDN%u IRQ not set.\n", + PC87382_SP1); + break; + } + + acpigen_write_device("DIR"); + + acpigen_write_name("_HID"); + acpigen_emit_eisaid(nsc_pc87382_sp1_acpi_hid()); + acpigen_write_name("_CRS"); + + acpigen_write_resourcetemplate_header( ); + acpigen_write_io16(io_res->base, io_res->base, io_res->align, + io_res->size, 1); + acpigen_write_irq(irq_res->base); + acpigen_write_resourcetemplate_footer(); + acpigen_write_STA(0xf); + + break; + } + acpigen_pop_len(); +} +#endif + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_enable, .init = init, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt_generator = pc87382_ssdt, +#endif }; static struct pnp_info pnp_dev_info[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/33789 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1bfebcdaf19798e5ca2fe6c96ac1f9f4cf73e9b Gerrit-Change-Number: 33789 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 7

Change in ...coreboot[master]: src/drivers/aspeed/common/ast_tables.h: Fix checkpatch Errors
by Abdullah Zafar (Code Review) 10 Jun '23

10 Jun '23

Abdullah Zafar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31975 Change subject: src/drivers/aspeed/common/ast_tables.h: Fix checkpatch Errors ...................................................................... src/drivers/aspeed/common/ast_tables.h: Fix checkpatch Errors Fix trailing whitespace and space required after that ','. Signed-off-by: Abdullah Zafar <azafar.bee16seecs(a)seecs.edu.pk> Change-Id: I28bf4280bf49be1c0f582a73387e845173582f53 --- M src/drivers/aspeed/common/ast_tables.h 1 file changed, 53 insertions(+), 53 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/31975/1 diff --git a/src/drivers/aspeed/common/ast_tables.h b/src/drivers/aspeed/common/ast_tables.h index 6c20f36..f59e5a7 100644 --- a/src/drivers/aspeed/common/ast_tables.h +++ b/src/drivers/aspeed/common/ast_tables.h @@ -112,71 +112,71 @@ /* MD_2_3_400 */ { 0x67, - {0x00,0x03,0x00,0x02}, - {0x5f,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f, - 0x00,0x4f,0x0d,0x0e,0x00,0x00,0x00,0x00, - 0x9c,0x8e,0x8f,0x28,0x1f,0x96,0xb9,0xa3, + {0x00, 0x03, 0x00, 0x02}, + {0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, + 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, + 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07, - 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f, - 0x0c,0x00,0x0f,0x08}, - {0x00,0x00,0x00,0x00,0x00,0x10,0x0e,0x00, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, + 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, + 0x0c, 0x00, 0x0f, 0x08}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00, 0xff} }, /* Mode12/ExtEGATable */ { 0xe3, - {0x01,0x0f,0x00,0x06}, - {0x5f,0x4f,0x50,0x82,0x55,0x81,0x0b,0x3e, - 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, - 0xe9,0x8b,0xdf,0x28,0x00,0xe7,0x04,0xe3, + {0x01, 0x0f, 0x00, 0x06}, + {0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0x0b, 0x3e, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xe9, 0x8b, 0xdf, 0x28, 0x00, 0xe7, 0x04, 0xe3, 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07, - 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f, - 0x01,0x00,0x0f,0x00}, - {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07, + 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f, + 0x01, 0x00, 0x0f, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff} }, /* ExtVGATable */ { 0x2f, - {0x01,0x0f,0x00,0x0e}, - {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, - 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, - 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, + {0x01, 0x0f, 0x00, 0x0e}, + {0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xea, 0x8c, 0xdf, 0x28, 0x40, 0xe7, 0x04, 0xa3, 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, - 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, - 0x01,0x00,0x00,0x00}, - {0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0f, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x01, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0f, 0xff} }, /* ExtHiCTable */ { 0x2f, - {0x01,0x0f,0x00,0x0e}, - {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, - 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, - 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, + {0x01, 0x0f, 0x00, 0x0e}, + {0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xea, 0x8c, 0xdf, 0x28, 0x40, 0xe7, 0x04, 0xa3, 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, - 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, - 0x01,0x00,0x00,0x00}, - {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x01, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff} }, /* ExtTrueCTable */ { 0x2f, - {0x01,0x0f,0x00,0x0e}, - {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e, - 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00, - 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3, + {0x01, 0x0f, 0x00, 0x0e}, + {0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e, + 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xea, 0x8c, 0xdf, 0x28, 0x40, 0xe7, 0x04, 0xa3, 0xff}, - {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07, - 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f, - 0x01,0x00,0x00,0x00}, - {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f, + {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, + 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, + 0x01, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f, 0xff} }, }; @@ -187,11 +187,11 @@ { 832, 640, 16, 40, 520, 480, 1, 3, VCLK31_5, /* 72Hz */ (SyncNN | HBorder | VBorder | Charx8Dot), 72, 2, 0x2E }, { 840, 640, 16, 64, 500, 480, 1, 3, VCLK31_5, /* 75Hz */ - (SyncNN | Charx8Dot) , 75, 3, 0x2E }, + (SyncNN | Charx8Dot), 75, 3, 0x2E }, { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36, /* 85Hz */ - (SyncNN | Charx8Dot) , 85, 4, 0x2E }, + (SyncNN | Charx8Dot), 85, 4, 0x2E }, { 832, 640, 56, 56, 509, 480, 1, 3, VCLK36, /* end */ - (SyncNN | Charx8Dot) , 0xFF, 4, 0x2E }, + (SyncNN | Charx8Dot), 0xFF, 4, 0x2E }, }; static struct ast_vbios_enhtable res_800x600[] = { @@ -243,18 +243,18 @@ /* 16:9 */ static struct ast_vbios_enhtable res_1360x768[] = { - {1792, 1360, 64,112, 795, 768, 3, 6, VCLK85_5, /* 60Hz */ + {1792, 1360, 64, 112, 795, 768, 3, 6, VCLK85_5, /* 60Hz */ (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x39 }, - {1792, 1360, 64,112, 795, 768, 3, 6, VCLK85_5, /* end */ + {1792, 1360, 64, 112, 795, 768, 3, 6, VCLK85_5, /* end */ (SyncPP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 1, 0x39 }, }; static struct ast_vbios_enhtable res_1600x900[] = { {1760, 1600, 48, 32, 926, 900, 3, 5, VCLK97_75, /* 60Hz CVT RB */ (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x3A }, - {2112, 1600, 88,168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ + {2112, 1600, 88, 168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x3A }, - {2112, 1600, 88,168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ + {2112, 1600, 88, 168, 934, 900, 3, 5, VCLK118_25, /* 60Hz CVT */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x3A }, }; @@ -270,9 +270,9 @@ static struct ast_vbios_enhtable res_1280x800[] = { {1440, 1280, 48, 32, 823, 800, 3, 6, VCLK71, /* 60Hz RB */ (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x35 }, - {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ + {1680, 1280, 72, 128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x35 }, - {1680, 1280, 72,128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ + {1680, 1280, 72, 128, 831, 800, 3, 6, VCLK83_5, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x35 }, }; @@ -280,18 +280,18 @@ static struct ast_vbios_enhtable res_1440x900[] = { {1600, 1440, 48, 32, 926, 900, 3, 6, VCLK88_75, /* 60Hz RB */ (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x36 }, - {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ + {1904, 1440, 80, 152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x36 }, - {1904, 1440, 80,152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ + {1904, 1440, 80, 152, 934, 900, 3, 6, VCLK106_5, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x36 }, }; static struct ast_vbios_enhtable res_1680x1050[] = { {1840, 1680, 48, 32, 1080, 1050, 3, 6, VCLK119, /* 60Hz RB */ (SyncNP | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 1, 0x37 }, - {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ + {2240, 1680, 104, 176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 60, 2, 0x37 }, - {2240, 1680,104,176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ + {2240, 1680, 104, 176, 1089, 1050, 3, 6, VCLK146_25, /* 60Hz */ (SyncPN | Charx8Dot | LineCompareOff | WideScreenMode | NewModeInfo), 0xFF, 2, 0x37 }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/31975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28bf4280bf49be1c0f582a73387e845173582f53 Gerrit-Change-Number: 31975 Gerrit-PatchSet: 1 Gerrit-Owner: Abdullah Zafar <abdullahzafar4876(a)yahoo.com> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: [UNTESTED]drivers/lenovo/wacom.c: Move DOCK SIO config to SIO code
by Arthur Heymans (Code Review) 10 Jun '23

10 Jun '23

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33788 Change subject: [UNTESTED]drivers/lenovo/wacom.c: Move DOCK SIO config to SIO code ...................................................................... [UNTESTED]drivers/lenovo/wacom.c: Move DOCK SIO config to SIO code This is not wacom specific code. Change-Id: I2fbcb25e78f490a65ecf4e0c8e6c84cd759a6f55 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/lenovo/lenovo.h M src/drivers/lenovo/wacom.c M src/mainboard/lenovo/x200/mainboard.c M src/mainboard/lenovo/x201/mainboard.c M src/mainboard/lenovo/x60/mainboard.c M src/superio/nsc/pc87392/superio.c 6 files changed, 66 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/33788/1 diff --git a/src/drivers/lenovo/lenovo.h b/src/drivers/lenovo/lenovo.h index 4c44119..c7e1b8f 100644 --- a/src/drivers/lenovo/lenovo.h +++ b/src/drivers/lenovo/lenovo.h @@ -1,3 +1,2 @@ int drivers_lenovo_is_wacom_present(void); -void drivers_lenovo_serial_ports_ssdt_generate(const char *scope, - int have_dock_serial); +void drivers_lenovo_serial_ports_ssdt_generate(const char *scope); diff --git a/src/drivers/lenovo/wacom.c b/src/drivers/lenovo/wacom.c index 9dcbf15..dfbd840 100644 --- a/src/drivers/lenovo/wacom.c +++ b/src/drivers/lenovo/wacom.c @@ -37,8 +37,7 @@ "2263", "2266", }; -int -drivers_lenovo_is_wacom_present(void) +int drivers_lenovo_is_wacom_present(void) { const char *pn; int i; @@ -85,9 +84,7 @@ return (result = 0); } -void -drivers_lenovo_serial_ports_ssdt_generate(const char *scope, - int have_dock_serial) +void drivers_lenovo_serial_ports_ssdt_generate(const char *scope) { acpigen_write_scope(scope); @@ -110,27 +107,5 @@ acpigen_pop_len(); } - if (have_dock_serial) { - acpigen_write_device("COMA"); - - acpigen_write_name("_HID"); - acpigen_emit_eisaid("PNP0501"); - acpigen_write_name("_UID"); - /* Byte */ - acpigen_write_byte(0x2); - - acpigen_write_name("_CRS"); - - acpigen_write_resourcetemplate_header(); - acpigen_write_io16(0x3f8, 0x3f8, 1, 8, 1); - acpigen_write_irq(1 << 4); - - acpigen_write_resourcetemplate_footer(); - - acpigen_write_STA(0xf); - - acpigen_pop_len(); - } - acpigen_pop_len(); } diff --git a/src/mainboard/lenovo/x200/mainboard.c b/src/mainboard/lenovo/x200/mainboard.c index 1510ab7..bcb94b1 100644 --- a/src/mainboard/lenovo/x200/mainboard.c +++ b/src/mainboard/lenovo/x200/mainboard.c @@ -19,7 +19,7 @@ static void fill_ssdt(struct device *device) { - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); + drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB"); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 70b393cc..8cd87aa 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -58,7 +58,7 @@ static void fill_ssdt(struct device *device) { - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 0); + drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB"); } static void mainboard_enable(struct device *dev) diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 964e9c0..9febea5 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -115,7 +115,7 @@ static void fill_ssdt(struct device *device) { - drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB", 1); + drivers_lenovo_serial_ports_ssdt_generate("\\_SB.PCI0.LPCB"); } static void mainboard_enable(struct device *dev) diff --git a/src/superio/nsc/pc87392/superio.c b/src/superio/nsc/pc87392/superio.c index a15d0a2..bf4ee54 100644 --- a/src/superio/nsc/pc87392/superio.c +++ b/src/superio/nsc/pc87392/superio.c @@ -14,6 +14,8 @@ * GNU General Public License for more details. */ +#include <arch/acpigen.h> +#include <console/console.h> #include <device/device.h> #include <device/pnp.h> #include <stdlib.h> @@ -25,12 +27,70 @@ return; } +#if CONFIG(HAVE_ACPI_TABLES) +static void pc87392_ssdt(struct device *dev) +{ + struct resource *io_res; + struct resource *irq_res; + + const char *scope = acpi_device_path(dev); + if (!scope) { + printk(BIOS_ERR, "%s: Missing ACPI scope\n", dev_path(dev)); + return; + } + + switch (dev->path.pnp.device) { + case PC87392_SP2: + case PC87392_SP1: + io_res = find_resource(dev, PNP_IDX_IO0); + if (!io_res || !io_res->base) { + printk(BIOS_ERR, "PC87392: LDN%u IOBASE not set.\n", + dev->path.pnp.device); + break; + } + irq_res = find_resource(dev, PNP_IDX_IRQ0); + if (!irq_res || !irq_res->base) { + printk(BIOS_ERR, "PC87392: LDN%u IRQ not set.\n", + dev->path.pnp.device); + break; + } + acpigen_write_scope(scope); + const char *dev_name = dev->path.pnp.device == PC87392_SP1 + ? "COMA" : "COMB"; + acpigen_write_device(dev_name); + + acpigen_write_name("_HID"); + acpigen_emit_eisaid("PNP0501"); + acpigen_write_name("_UID"); + /* Byte */ + acpigen_write_byte(0x2); + + acpigen_write_name("_CRS"); + + acpigen_write_resourcetemplate_header(); + acpigen_write_io16(io_res->base, io_res->base, io_res->align, + io_res->size, 1); + acpigen_write_irq(irq_res->base); + acpigen_write_resourcetemplate_footer(); + + /* TODO, This likely depends on dock status */ + acpigen_write_STA(0xf); + + acpigen_pop_len(); /* pop scope */ + } +} +#endif + + static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_enable, .init = init, +#if CONFIG(HAVE_ACPI_TABLES) + .acpi_fill_ssdt_generator = pc87392_ssdt, +#endif }; static struct pnp_info pnp_dev_info[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/33788 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2fbcb25e78f490a65ecf4e0c8e6c84cd759a6f55 Gerrit-Change-Number: 33788 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: mb/google/hatch: Disable the eMMC controller for hatch
by V Sowmya (Code Review) 10 Jun '23

10 Jun '23

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30615 Change subject: mb/google/hatch: Disable the eMMC controller for hatch ...................................................................... mb/google/hatch: Disable the eMMC controller for hatch eMMC controller is not used in hatch hence this patch adds the Kconfig option to disable the eMMC controller ACPI entries. BUG=b:120914069 BRANCH=none TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot. Change-Id: Ie52c4fa581ad2c9b14e57919a63b3128bd928596 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/google/hatch/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/30615/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 711d2e9..15fe354 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -15,6 +15,7 @@ select SOC_INTEL_CANNONLAKE_MEMCFG_INIT select SOC_INTEL_COFFEELAKE select SYSTEM_TYPE_LAPTOP + select EXCLUDE_EMMC_INTERFACE if BOARD_GOOGLE_BASEBOARD_HATCH -- To view, visit https://review.coreboot.org/c/coreboot/+/30615 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie52c4fa581ad2c9b14e57919a63b3128bd928596 Gerrit-Change-Number: 30615 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

4 3

Change in ...coreboot[master]: mb/google/hatch: [TEST- ONLY] Enable RMT log capture in FSP
by Aamir Bohra (Code Review) 10 Jun '23

10 Jun '23

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30664 Change subject: mb/google/hatch: [TEST- ONLY] Enable RMT log capture in FSP ...................................................................... mb/google/hatch: [TEST- ONLY] Enable RMT log capture in FSP **** DO NOT MERGE **** Change-Id: I0a0865b2baa6d3606a38b9f07b1d32f13e4e7178 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/google/hatch/romstage.c 1 file changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/30664/1 diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c index 401f41f..4a47d12 100644 --- a/src/mainboard/google/hatch/romstage.c +++ b/src/mainboard/google/hatch/romstage.c @@ -19,11 +19,14 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { + FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; + mem_cfg->RMT = 1; + memupd->FspmTestConfig.BdatEnable = 1; + mem_cfg->MrcFastBoot = 0; + const struct spd_info spd = { .spd_by_index = true, .spd_spec.spd_index = variant_memory_sku(), }; - - cannonlake_memcfg_init(&memupd->FspmConfig, - variant_memory_params(), &spd); + cannonlake_memcfg_init(mem_cfg, variant_memory_params(), &spd); } -- To view, visit https://review.coreboot.org/c/coreboot/+/30664 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a0865b2baa6d3606a38b9f07b1d32f13e4e7178 Gerrit-Change-Number: 30664 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: Documentation: Update soc/intel/apollolake
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33740 Change subject: Documentation: Update soc/intel/apollolake ...................................................................... Documentation: Update soc/intel/apollolake Explaing LBPs and how to disable dual partition mode. Change-Id: I0b609f802d96aa90d0c1479ffeccf3aaaa70a85d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/soc/intel/apollolake/flash_layout.dia M Documentation/soc/intel/apollolake/flash_layout.svg A Documentation/soc/intel/apollolake/flash_layout2.dia A Documentation/soc/intel/apollolake/flash_layout2.svg M Documentation/soc/intel/apollolake/index.md 5 files changed, 272 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/33740/1 diff --git a/Documentation/soc/intel/apollolake/flash_layout.dia b/Documentation/soc/intel/apollolake/flash_layout.dia index 4ea5440..a329620 100644 --- a/Documentation/soc/intel/apollolake/flash_layout.dia +++ b/Documentation/soc/intel/apollolake/flash_layout.dia Binary files differ diff --git a/Documentation/soc/intel/apollolake/flash_layout.svg b/Documentation/soc/intel/apollolake/flash_layout.svg index 9322875..07b3a58 100644 --- a/Documentation/soc/intel/apollolake/flash_layout.svg +++ b/Documentation/soc/intel/apollolake/flash_layout.svg @@ -1,6 +1,6 @@ <?xml version="1.0" encoding="UTF-8" standalone="no"?> <!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.0//EN" "http://www.w3.org/TR/2001/PR-SVG-20010719/DTD/svg10.dtd"> -<svg width="38cm" height="18cm" viewBox="118 98 744 344" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"> +<svg width="38cm" height="19cm" viewBox="118 61 744 380" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"> <g> <rect style="fill: #ffffff" x="620" y="100" width="180" height="60"/> <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="620" y="100" width="180" height="60"/> @@ -16,18 +16,18 @@ <tspan x="460" y="134.425">BIOS</tspan> </text> <g> - <rect style="fill: #ffffff" x="240" y="100" width="60" height="60"/> - <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="240" y="100" width="60" height="60"/> + <rect style="fill: #ffffff" x="227.633" y="99.4585" width="60" height="60"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="227.633" y="99.4585" width="60" height="60"/> </g> - <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="270" y="134.425"> - <tspan x="270" y="134.425">IFD</tspan> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="257.633" y="133.884"> + <tspan x="257.633" y="133.884">IFD</tspan> </text> <g> <rect style="fill: #ffffff" x="200" y="240" width="80" height="60"/> <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="200" y="240" width="80" height="60"/> </g> - <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="240" y="274.425"> - <tspan x="240" y="274.425">IFWI</tspan> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="240" y="274.238"> + <tspan x="240" y="274.238">IFWI</tspan> </text> <g> <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 200 240 C 200,160 460,220 460,169.736"/> @@ -35,7 +35,7 @@ <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="460,162.236 465,172.236 460,169.736 455,172.236 "/> </g> <g> - <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 700 240 C 700,160 460,220 460,169.736"/> + <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 700.289 239.999 C 700.289,159.999 460,220 460,169.736"/> <polygon style="fill: #000000" points="460,162.236 465,172.236 460,169.736 455,172.236 "/> <polygon style="fill: none; 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fill-opacity:0; stroke-width: 3; stroke: #000000" x="280" y="240" width="420" height="60"/> + <rect style="fill: #ffffff" x="280" y="240" width="420.151" height="60"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="280" y="240" width="420.151" height="60"/> </g> - <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="490" y="274.425"> - <tspan x="490" y="274.425">OBB</tspan> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="490.076" y="274.425"> + <tspan x="490.076" y="274.425">OBB</tspan> </text> <g> - <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 320 380 C 320,300 490,360 490,311"/> - <polygon style="fill: #000000" points="495,311 490,301 485,311 "/> - <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="495,311 490,301 485,311 "/> + <path style="fill: none; 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fill-opacity:0; stroke-width: 3; stroke: #000000" x="668.7" y="241.9" width="28.5491" height="54.6579"/> + </g> +</svg> diff --git a/Documentation/soc/intel/apollolake/index.md b/Documentation/soc/intel/apollolake/index.md index d4a5ee5..3ff0027 100644 --- a/Documentation/soc/intel/apollolake/index.md +++ b/Documentation/soc/intel/apollolake/index.md @@ -1,9 +1,7 @@ # Apollolake -## SPI flash layout -![][apl_flash_layout] - -With Apollolake Intel invented another flash layout for x86 firmware called IFWI (Intel FirmWare Image). +With Apollolake Intel invented another flash layout for x86 firmware called +IFWI (Intel FirmWare Image). Usually on x86 platforms the bootblock is stored at the end of the bios region and the Intel ME / TXE has its own IFD region. On Apollolake both have been @@ -12,6 +10,47 @@ The IFWI region can be manipulated by `ifwitool`. -[apl_flash_layout]: flash_layout.svg +## SPI flash layout +IFD regions: +* The "ME" region isn't used on production boards +* The "BIOS" region contains one or two logical boot partitions (LBP) + * The IFD controls if one or two LBP are active + * Each LBP has it's own IFWI and OBB + * The last 256 KiB of the "BIOS" region are BIOS_UNUSABLE +* The "device extension" region is used by TXE as secure filesystem + +### SPI layout with single LBP + +When configured for single LBP mode, the LBP uses the whole "BIOS" region's +flash size. + +![][apl_flash_layout] + +### SPI layout with dual LBP + +When configured for dual LBP mode, each LBP uses exactly half of the "BIOS" +region's flash size. + +![][apl_flash_layout2] + +### IFWI + +The IFWI contains the bootblock, while the OBB contains the CBFS and other +regions as specified in the FMAP. +The OBB spans the whole size from IFWI till the end of the LBP. + +**Note:** ifwitool doesn't care about LBP2! + +### Logical boot partitions + +Each LBP has their own IFWI and OBB. It allows failsafe firmware updates. + +**Note:** If configured in dual partition mode, the TXE will enter recovery +mode if LBP2 is missing. + +To disable dual partitioning mode, set bit3 in IFD at offset `0x1ff` to 1. + +[apl_flash_layout]: flash_layout.svg +[apl_flash_layout2]: flash_layout2.svg -- To view, visit https://review.coreboot.org/c/coreboot/+/33740 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0b609f802d96aa90d0c1479ffeccf3aaaa70a85d Gerrit-Change-Number: 33740 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

8 36

Change in ...coreboot[master]: util/smctool: A tool for reading Apple SMC keys
by Evgeny Zinoviev (Code Review) 10 Jun '23

10 Jun '23

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33052 Change subject: util/smctool: A tool for reading Apple SMC keys ...................................................................... util/smctool: A tool for reading Apple SMC keys SMC is an embedded controller on Apple computers. With this tool you can read SMC keys. It supports various data types and can output result in various formats. Example how to get battery capacity level: smctool -k B0FC -t ui16 # returns Full Capacity of Battery 0 smctool -k B0RM -t ui16 # returns Remaining Capacity of Batery 0 So B0RM / B0FC * 100 = battery capacity in percents. Another example, reading current fan speed, which is returned as unsigned fixed point number: sudo ./smctool -k F0Ac -t fpe2 Change-Id: I6161203e52b7f7eaa1205de06e8241d7d40a7481 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- A util/smctool/Makefile A util/smctool/description.md A util/smctool/smc.c A util/smctool/smc.h A util/smctool/smctool.c 5 files changed, 538 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/33052/1 diff --git a/util/smctool/Makefile b/util/smctool/Makefile new file mode 100644 index 0000000..ce7cca2 --- /dev/null +++ b/util/smctool/Makefile @@ -0,0 +1,38 @@ +## +## Makefile for smctool +## +## Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +CC = gcc +CFLAGS = -O2 -Wall -W +PROGRAM = smctool +INSTALL = /usr/bin/env install +PREFIX = /usr/local + +all: $(PROGRAM) + +$(PROGRAM): smc.o smctool.o + $(CC) $(CFLAGS) -o $@ $^ $(LDFLAGS) + +install: $(PROGRAM) + $(INSTALL) $(PROGRAM) $(PREFIX)/sbin + +clean: + rm -f *.o $(PROGRAM) + +distclean: clean + +%.o: %.c + $(CC) $(CFLAGS) -c $^ -I. -o $@ + +.PHONY: all install clean distclean diff --git a/util/smctool/description.md b/util/smctool/description.md new file mode 100644 index 0000000..37a2d2a --- /dev/null +++ b/util/smctool/description.md @@ -0,0 +1 @@ +Reads keys from Apple SMC. Supports various data types. `C` diff --git a/util/smctool/smc.c b/util/smctool/smc.c new file mode 100644 index 0000000..a875b2c --- /dev/null +++ b/util/smctool/smc.c @@ -0,0 +1,156 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * SMC interacting code is based on applesmc linux driver by: + * Copyright (C) 2007 Nicolas Boichat <nicolas(a)boichat.ch> + * Copyright (C) 2010 Henrik Rydberg <rydberg(a)euromail.se> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdlib.h> +#include <sys/io.h> +#include <errno.h> +#include <stdio.h> +#include "smc.h" + +/* + * wait_read - Wait for a byte to appear on SMC port. Callers must + * hold applesmc_lock. + */ +int wait_read(void) +{ + uint8_t status; + int us; + for (us = APPLESMC_MIN_WAIT; us < APPLESMC_MAX_WAIT; us <<= 1) { + usleep(us); + status = inb(APPLESMC_CMD_PORT); + + /* read: wait for smc to settle */ + if (status & 0x01) + return 0; + } + + fprintf(stderr, "%s() fail: 0x%02x\n", __func__, status); + return -EIO; +} + +/* + * send_byte - Write to SMC port, retrying when necessary. Callers + * must hold applesmc_lock. + */ +int send_byte(uint8_t cmd, uint16_t port) +{ + uint8_t status; + int us; + + outb(cmd, port); + for (us = APPLESMC_MIN_WAIT; us < APPLESMC_MAX_WAIT; us <<= 1) { + usleep(us); + status = inb(APPLESMC_CMD_PORT); + /* write: wait for smc to settle */ + if (status & 0x02) + continue; + /* ready: cmd accepted, return */ + if (status & 0x04) + return 0; + /* timeout: give up */ + if (us << 1 == APPLESMC_MAX_WAIT) + break; + /* busy: long wait and resend */ + usleep(APPLESMC_RETRY_WAIT); + outb(cmd, port); + } + + fprintf(stderr, "%s(0x%02x, 0x%04x) fail: 0x%02x\n", + __func__, cmd, port, status); + return -EIO; +} + +int send_command(uint8_t cmd) +{ + return send_byte(cmd, APPLESMC_CMD_PORT); +} + +int send_argument(const char *key) +{ + int i; + + for (i = 0; i < 4; i++) + if (send_byte(key[i], APPLESMC_DATA_PORT)) + return -EIO; + return 0; +} + +int read_smc(uint8_t cmd, const char *key, uint8_t *buffer, uint8_t len) +{ + uint8_t status, data = 0; + int i; + + if (send_command(cmd) || send_argument(key)) { + fprintf(stderr, "%.4s: read arg fail\n", key); + return -EIO; + } + + /* This has no effect on newer (2012) SMCs */ + if (send_byte(len, APPLESMC_DATA_PORT)) { + fprintf(stderr, "%.4s: read len fail\n", key); + return -EIO; + } + + for (i = 0; i < len; i++) { + if (wait_read()) { + fprintf(stderr, "%.4s: read data[%d] fail\n", key, i); + return -EIO; + } + buffer[i] = inb(APPLESMC_DATA_PORT); + } + + /* Read the data port until bit0 is cleared */ + for (i = 0; i < 16; i++) { + usleep(APPLESMC_MIN_WAIT); + status = inb(APPLESMC_CMD_PORT); + if (!(status & 0x01)) + break; + data = inb(APPLESMC_DATA_PORT); + } + + if (i) + fprintf(stderr, "flushed %d bytes, last value is: %d\n", + i, data); + + return 0; +} + +int write_smc(uint8_t cmd, const char *key, const uint8_t *buffer, uint8_t len) +{ + int i; + + if (send_command(cmd) || send_argument(key)) { + fprintf(stderr, "%s: write arg fail\n", key); + return -EIO; + } + + if (send_byte(len, APPLESMC_DATA_PORT)) { + fprintf(stderr, "%.4s: write len fail\n", key); + return -EIO; + } + + for (i = 0; i < len; i++) { + if (send_byte(buffer[i], APPLESMC_DATA_PORT)) { + fprintf(stderr, "%s: write data fail\n", key); + return -EIO; + } + } + + return 0; +} diff --git a/util/smctool/smc.h b/util/smctool/smc.h new file mode 100644 index 0000000..dffd8db --- /dev/null +++ b/util/smctool/smc.h @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SMC_H +#define SMC_H + +#include <stdbool.h> +#include <unistd.h> +#include <stdint.h> + +/* data port used by Apple SMC */ +#define APPLESMC_DATA_PORT 0x300 +/* command/status port used by Apple SMC */ +#define APPLESMC_CMD_PORT 0x304 + +#define APPLESMC_MAX_DATA_LENGTH 32 + +/* wait up to 128 ms for a status change. */ +#define APPLESMC_MIN_WAIT 0x0010 +#define APPLESMC_RETRY_WAIT 0x0100 +#define APPLESMC_MAX_WAIT 0x20000 + +#define APPLESMC_READ_CMD 0x10 +#define APPLESMC_WRITE_CMD 0x11 + +int wait_read(void); +int send_byte(uint8_t cmd, uint16_t port); +int send_command(uint8_t cmd); +int send_argument(const char *key); +int read_smc(uint8_t cmd, const char *key, uint8_t *buffer, uint8_t len); +int write_smc(uint8_t cmd, const char *key, const uint8_t *buffer, uint8_t len); + +#endif /* SMC_H */ diff --git a/util/smctool/smctool.c b/util/smctool/smctool.c new file mode 100644 index 0000000..fda7904 --- /dev/null +++ b/util/smctool/smctool.c @@ -0,0 +1,298 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <getopt.h> +#include <string.h> +#include <stdlib.h> +#include <assert.h> +#include <endian.h> +#include <sys/io.h> +#include <stdio.h> +#include <errno.h> +#include "smc.h" +#include "smctool.h" + +static bool fp_bits(char c, uint8_t *dest) +{ + if ((c >= '0' && c <= '9') || (c >= 'a' && c <= 'f')) { + *dest = strtol(&c, NULL, 16); + return true; + } + return false; +} + +static void print_bits(uint8_t len, uint8_t *ptr) +{ + for (int i = len - 1; i >= 0; i--) { + for (int j = 7; j >= 0; j--) + printf("%u", (ptr[i] >> j) & 1); + + if (i > 0) + printf(" "); + } +} + +static void print_usage(const char *name) +{ + printf("usage: %s <options>\n", name); + printf("\n" + "Options:\n" + " -h, --help: print this help\n" + " -k, --key <name>: key name\n" + " -t, --type <type>: data type, see below\n" + " --output-hex\n" + " --output-bin\n" + "\n" + "Supported data types:\n" + " ui8, ui16, ui32, si8, si16, flag, fpXY, spXY\n" + "\n" + " fp and sp are unsigned and signed fixed point\n" + " data types respectively.\n" + "\n" + " The X in fp and sp data types is integer bits count\n" + " and Y is fraction bits count.\n" + "\n" + " For example,\n" + " fpe2 means 14 integer bits, 2 fraction bits,\n" + " sp78 means 7 integer bits, 8 fraction bits\n" + " (and one sign bit).\n" + "\n"); +} + + +enum output_format {dec, hex, bin}; + +enum smctype {none, ui8, ui16, ui32, si8, si16, flag, fp, sp}; +struct { + enum smctype type; + uint8_t len; + char *str; + char *decfmt; + char *hexfmt; +} types[] = { + {ui8, 1, "ui8", "%u", "0x%02x"}, + {ui16, 2, "ui16", "%u", "0x%04x"}, + {ui32, 4, "ui32", "%u", "0x%08x"}, + {si8, 1, "si8", "%d", "0x%02x"}, + {si16, 2, "si16", "%d", "0x%04x"}, + {flag, 1, "flag", "%u", "0x%01x"}, +}; + +int main(int argc, char *argv[]) +{ + bool show_help = false; + int opt, option_index = 0; + char name[KEYBUFSIZE+1] = {0}; + char typebuf[KEYBUFSIZE+1] = {0}; + uint8_t fp_int_bits = 0, fp_fraction_bits = 0; + + enum output_format of = dec; + char *ofmt = NULL; + char fmtbuf[32]; + + enum smctype type = none; + uint8_t len; + + struct option long_options[] = { + {"help", 0, 0, 'h'}, + {"key", 1, 0, 'k'}, + {"type", 1, 0, 't'}, + {"output-hex", 0, 0, 1000}, + {"output-bin", 0, 0, 1001}, + {0, 0, 0, 0} + }; + + if (argv[1] == NULL) { + print_usage(argv[0]); + exit(0); + } + + while ((opt = getopt_long(argc, argv, "hk:t:", + long_options, &option_index)) != EOF) { + switch (opt) { + case 'h': + show_help = true; + break; + + case 'k': + snprintf(name, KEYBUFSIZE, "%s", optarg); + break; + + case 't': + snprintf(typebuf, KEYBUFSIZE, "%s", optarg); + break; + + case 1000: // output-hex + of = hex; + break; + + case 1001: // output-bin + of = bin; + break; + } + } + + if (optind < argc) { + fprintf(stderr, "Error: Extra parameter found.\n"); + print_usage(argv[0]); + exit(1); + } + + if (show_help) { + print_usage(argv[0]); + exit(0); + } + + /* Validate key name */ + if (strlen(name) != 4) { + fprintf(stderr, "Key name must be 4 characters long.\n"); + exit(1); + } + + /* Validate key type */ + if ((typebuf[0] == 'f' || typebuf[0] == 's') && typebuf[1] == 'p') { + if (!fp_bits(typebuf[2], &fp_int_bits) + || !fp_bits(typebuf[3], &fp_fraction_bits)) { + fprintf(stderr, "Invalid fixed point data type.\n"); + exit(1); + } + if (typebuf[0] == 'f' && fp_int_bits + fp_fraction_bits != 16) { + fprintf(stderr, + "Invalid unsigned fixed point data type.\n"); + exit(1); + } + if (typebuf[0] == 's' && fp_int_bits + fp_fraction_bits != 15) { + fprintf(stderr, + "Invalid signed fixed point data type.\n"); + exit(1); + } + type = typebuf[0] == 'f' ? fp : sp; + len = 2; + ofmt = "%d.%u"; + } + + if (type == none) { + for (unsigned int i = 0; i < ARRAY_SIZE(types); i++) { + if (strcmp(typebuf, types[i].str)) + continue; + + type = types[i].type; + len = types[i].len; + if (of == dec) + ofmt = types[i].decfmt; + else if (of == hex) + ofmt = types[i].hexfmt; + break; + } + } + + if (type == none) { + fprintf(stderr, "Key type \"%s\" is not known.\n", typebuf); + exit(1); + } + + /* Check permissions */ + if (geteuid() != 0) { + fprintf(stderr, "You must be root.\n"); + exit(1); + } + + /* Open SMC port */ + if (ioperm(APPLESMC_DATA_PORT, 0x10, 1)) { + fprintf(stderr, "ioperm: %s\n", strerror(errno)); + exit(1); + } + + /* Read key from SMC */ + int retval; + uint32_t buf = 0; + + retval = read_smc(APPLESMC_READ_CMD, name, (uint8_t *)&buf, len); + assert(retval == 0); + + /* Handle returned value according to the requested type */ + buf = be32toh(buf); + + int32_t fp_int = 0; + uint16_t fp_fraction = 0; + bool fp_sign = false; + + switch (type) { + case flag: + buf = (buf >> 24) & 1; + break; + + case ui8: + buf = (buf >> 24) & 0xff; + break; + + case si8: + buf = (buf >> 24) & 0xff; + if (of == dec) + buf = (int8_t)buf; + break; + + case ui16: + buf = (buf >> 16) & 0xffff; + break; + + case si16: + buf = (buf >> 16) & 0xffff; + if (of == dec) + buf = (int16_t)buf; + break; + + case fp: + buf = (buf >> 16) & 0xffff; + fp_int = buf >> fp_fraction_bits; + fp_fraction = buf & (0xffff >> fp_int_bits); + break; + + case sp: + buf = (buf >> 16) & 0xffff; + fp_sign = ((buf >> 15) & 1) == 1; + + buf &= ~(1 << 15); + + fp_int = buf >> fp_fraction_bits; + fp_fraction = buf & (0xffff >> fp_int_bits); + + if (fp_sign) + fp_int *= -1; + break; + + case ui32: + case none: // to avoid gcc warning + break; + } + + /* Output the result */ + if (of != bin) { + strcpy(fmtbuf, "%s = "); + strcat(fmtbuf, ofmt); + strcat(fmtbuf, "\n"); + + if (type == fp || type == sp) + printf(fmtbuf, name, fp_int, fp_fraction); + else + printf(fmtbuf, name, buf); + } else { + printf("%s = ", name); + print_bits(len, (uint8_t *)&buf); + printf("\n"); + } + + return 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6161203e52b7f7eaa1205de06e8241d7d40a7481 Gerrit-Change-Number: 33052 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: newchange

5 7

Change in ...coreboot[master]: drivers/spi: Instrument erase operation
by Paul Menzel (Code Review) 10 Jun '23

10 Jun '23

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31793 Change subject: drivers/spi: Instrument erase operation ...................................................................... drivers/spi: Instrument erase operation Verify console output contains the new string. BS: BS_DEV_INIT times (us): entry 0 run 72771 exit 0 Finalize devices... Devices finalized APIC 00: ** Enter AmdInitLate [00020004] SB800: sb_Late_Post AmdInitLate() returned AGESA_SUCCESS APIC 00: Heap in SystemMem (4) at 0x10000014 APIC 00: ** Exit AmdInitLate [00020004] APIC 00: ** Enter AmdS3Save [0002000b] Manufacturer: ef SF: Detected W25Q32_V with sector size 0x1000, total 0x400000 SF: Successfully erased 4096 bytes @ 0xffff1000 in 97754 usecs Manufacturer: ef SF: Detected W25Q32_V with sector size 0x1000, total 0x400000 SF: Successfully erased 4096 bytes @ 0xffff0000 in 121777 usecs AmdS3Save() returned AGESA_SUCCESS APIC 00: Heap in SystemMem (4) at 0x10000014 APIC 00: ** Exit AmdS3Save [0002000b] BS: BS_POST_DEVICE times (us): entry 0 run 3 exit 228371 Change-Id: I4eb8a850d7263bc3c800d97655f0b37623b78562 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M src/drivers/spi/spi_flash.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/31793/1 diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index d1f5227..7f64968 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -198,6 +198,9 @@ u32 start, end, erase_size; int ret = -1; u8 cmd[4]; + struct stopwatch sw; + + stopwatch_init(&sw); erase_size = flash->sector_size; if (offset % erase_size || len % erase_size) { @@ -234,7 +237,8 @@ goto out; } - printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x\n", len, start); + printk(BIOS_DEBUG, "SF: Successfully erased %zu bytes @ %#x in %ld usecs\n", + len, start, stopwatch_duration_usecs(&sw)); out: return ret; -- To view, visit https://review.coreboot.org/c/coreboot/+/31793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4eb8a850d7263bc3c800d97655f0b37623b78562 Gerrit-Change-Number: 31793 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

4 4

Change in ...coreboot[master]: sb/intel/ibexpeak: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB
by Patrick Rudolph (Code Review) 10 Jun '23

10 Jun '23

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32316 Change subject: sb/intel/ibexpeak: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB ...................................................................... sb/intel/ibexpeak: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB Use common code to detect ACPI S3. Untested. Change-Id: I766a3f4206e6605e6b7bb9a1ff0b2deb6721eb77 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/lenovo/x201/romstage.c M src/mainboard/packardbell/ms2290/romstage.c M src/southbridge/intel/ibexpeak/Kconfig 3 files changed, 13 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/32316/1 diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 7e895b4..e65622c 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -34,6 +34,7 @@ #include "dock.h" #include <southbridge/intel/ibexpeak/pch.h> #include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/nehalem/nehalem.h> #include <northbridge/intel/nehalem/raminit.h> @@ -206,24 +207,14 @@ /* Halt if there was a built in self test failure */ report_bist_failure(bist); - /* Read PM1_CNT */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); - if (((reg32 >> 10) & 7) == 5) { - u8 reg8; - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + /* Check for S3 resume. */ + s3resume = southbridge_detect_s3_resume(); + if (s3resume) { + u8 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); printk(BIOS_DEBUG, "a2: %02x\n", reg8); if (!(reg8 & 0x20)) { - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); printk(BIOS_DEBUG, "Bad resume from S3 detected.\n"); - } else { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - s3resume = 1; - } else { - printk(BIOS_DEBUG, - "Resume from S3 detected, but disabled.\n"); - } + s3resume = 0; } } @@ -263,13 +254,5 @@ intel_early_me_status(); - if (s3resume) { - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - } - romstage_handoff_init(s3resume); } diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 8442dfa..854c835 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -34,6 +34,7 @@ #include "arch/early_variables.h" #include <southbridge/intel/ibexpeak/pch.h> #include <northbridge/intel/nehalem/nehalem.h> +#include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/nehalem/raminit.h> #include <southbridge/intel/ibexpeak/me.h> @@ -206,24 +207,14 @@ /* Halt if there was a built in self test failure */ report_bist_failure(bist); - /* Read PM1_CNT */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); - if (((reg32 >> 10) & 7) == 5) { - u8 reg8; - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + /* Check for S3 resume. */ + s3resume = southbridge_detect_s3_resume(); + if (s3resume) { + u8 reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); printk(BIOS_DEBUG, "a2: %02x\n", reg8); if (!(reg8 & 0x20)) { - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); printk(BIOS_DEBUG, "Bad resume from S3 detected.\n"); - } else { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - s3resume = 1; - } else { - printk(BIOS_DEBUG, - "Resume from S3 detected, but disabled.\n"); - } + s3resume = 0; } } @@ -255,13 +246,5 @@ intel_early_me_status(); - if (s3resume) { - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - } - romstage_handoff_init(s3resume); } diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index bb6e22c..59b012e 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -32,6 +32,7 @@ select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI + select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select HAVE_USBDEBUG_OPTIONS select COMMON_FADT select ACPI_SATA_GENERATOR -- To view, visit https://review.coreboot.org/c/coreboot/+/32316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I766a3f4206e6605e6b7bb9a1ff0b2deb6721eb77 Gerrit-Change-Number: 32316 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 4

Change in ...coreboot[master]: mb/lenovo: Add Lenovo Thinkpad Helix
by Christoph Pomaska (Code Review) 10 Jun '23

10 Jun '23

Christoph Pomaska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33867 Change subject: mb/lenovo: Add Lenovo Thinkpad Helix ...................................................................... mb/lenovo: Add Lenovo Thinkpad Helix This port was originally generated by autoport, but has been modified. This device is technically a tablet PC, but the linter rejects 'tablet' in board_info.txt at the moment (TODO). THIS PORT IS UNTESTED YET Change-Id: I7dbf10bc85edb161fce077568d4ef3db91e10db7 Signed-off-by: Christoph Pomaska <github(a)aufmachen.jetzt> --- A src/mainboard/lenovo/helix/Kconfig A src/mainboard/lenovo/helix/Kconfig.name A src/mainboard/lenovo/helix/Makefile.inc A src/mainboard/lenovo/helix/acpi/ec.asl A src/mainboard/lenovo/helix/acpi/platform.asl A src/mainboard/lenovo/helix/acpi/superio.asl A src/mainboard/lenovo/helix/acpi_tables.c A src/mainboard/lenovo/helix/board_info.txt A src/mainboard/lenovo/helix/devicetree.cb A src/mainboard/lenovo/helix/dock.c A src/mainboard/lenovo/helix/dsdt.asl A src/mainboard/lenovo/helix/gma-mainboard.ads A src/mainboard/lenovo/helix/gpio.c A src/mainboard/lenovo/helix/hda_verb.c A src/mainboard/lenovo/helix/mainboard.c A src/mainboard/lenovo/helix/romstage.c A src/mainboard/lenovo/helix/smihandler.c 17 files changed, 921 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/33867/1 diff --git a/src/mainboard/lenovo/helix/Kconfig b/src/mainboard/lenovo/helix/Kconfig new file mode 100644 index 0000000..5f97a0e --- /dev/null +++ b/src/mainboard/lenovo/helix/Kconfig @@ -0,0 +1,46 @@ +if BOARD_LENOVO_THINKPAD_HELIX + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_12288 + select EC_LENOVO_H8 + select EC_LENOVO_PMH7 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select MAINBOARD_HAS_LIBGFXINIT # FIXME: check this + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_C216 + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + select GFX_GMA_INTERNAL_IS_EDP + +config MAINBOARD_DIR + string + default lenovo/helix + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad Helix" + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +config VGA_BIOS_ID + string + default "8086,0166" + +config DRAM_RESET_GATE_GPIO # FIXME: check this + int + default 10 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 +endif diff --git a/src/mainboard/lenovo/helix/Kconfig.name b/src/mainboard/lenovo/helix/Kconfig.name new file mode 100644 index 0000000..d36682b --- /dev/null +++ b/src/mainboard/lenovo/helix/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_LENOVO_THINKPAD_HELIX + bool "ThinkPad Helix" diff --git a/src/mainboard/lenovo/helix/Makefile.inc b/src/mainboard/lenovo/helix/Makefile.inc new file mode 100644 index 0000000..333f63a --- /dev/null +++ b/src/mainboard/lenovo/helix/Makefile.inc @@ -0,0 +1,4 @@ +romstage-y += gpio.c +ramstage-y += dock.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads +smm-y += smihandler.c diff --git a/src/mainboard/lenovo/helix/acpi/ec.asl b/src/mainboard/lenovo/helix/acpi/ec.asl new file mode 100644 index 0000000..c3569e8 --- /dev/null +++ b/src/mainboard/lenovo/helix/acpi/ec.asl @@ -0,0 +1 @@ +#include <ec/lenovo/h8/acpi/ec.asl> diff --git a/src/mainboard/lenovo/helix/acpi/platform.asl b/src/mainboard/lenovo/helix/acpi/platform.asl new file mode 100644 index 0000000..1340cd7 --- /dev/null +++ b/src/mainboard/lenovo/helix/acpi/platform.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Christoph Pomaska <github(a)aufmachen.jetzt> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +Method(_WAK,1) +{ + /* ME may not be up yet. */ + Store (0, \_TZ.MEB1) + Store (0, \_TZ.MEB2) + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC.RADI(0) +} diff --git a/src/mainboard/lenovo/helix/acpi/superio.asl b/src/mainboard/lenovo/helix/acpi/superio.asl new file mode 100644 index 0000000..f2b35ba --- /dev/null +++ b/src/mainboard/lenovo/helix/acpi/superio.asl @@ -0,0 +1 @@ +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/lenovo/helix/acpi_tables.c b/src/mainboard/lenovo/helix/acpi_tables.c new file mode 100644 index 0000000..6b731cc --- /dev/null +++ b/src/mainboard/lenovo/helix/acpi_tables.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/lenovo/helix/board_info.txt b/src/mainboard/lenovo/helix/board_info.txt new file mode 100644 index 0000000..a7c651b --- /dev/null +++ b/src/mainboard/lenovo/helix/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM protocol: SPI +Flashrom support: ? +ROM package: SOIC8 +ROM socketed: n +Release year: 2013 diff --git a/src/mainboard/lenovo/helix/devicetree.cb b/src/mainboard/lenovo/helix/devicetree.cb new file mode 100644 index 0000000..d5a6dd9 --- /dev/null +++ b/src/mainboard/lenovo/helix/devicetree.cb @@ -0,0 +1,166 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0x00001156" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "1" + register "gpu_panel_power_backlight_off_delay" = "1" + register "gpu_panel_power_backlight_on_delay" = "1" + register "gpu_panel_power_cycle_delay" = "6" + register "gpu_panel_power_down_delay" = "500" + register "gpu_panel_power_up_delay" = "2000" + register "gpu_pch_backlight" = "0x11561156" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax # FIXME: check all registers + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "1" + register "gen1_dec" = "0x007c1601" + register "gen2_dec" = "0x000c15e1" + register "gen3_dec" = "0x00000000" + register "gen4_dec" = "0x000c06a1" + register "gpi13_routing" = "2" + register "gpi1_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 1, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x1" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "superspeed_capable_ports" = "0x0000000b" + register "xhci_overcurrent_mapping" = "0x04000201" + register "xhci_switchable_ports" = "0x0000000b" + device pci 14.0 on # USB 3.0 Controller + subsystemid 0x17aa 0x2207 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x17aa 0x2207 + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 off # Intel Gigabit Ethernet + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x17aa 0x2207 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x17aa 0x2207 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x17aa 0x2207 + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x17aa 0x2207 + end + device pci 1c.2 off # PCIe Port #3 + end + device pci 1c.3 off # PCIe Port #4 + end + device pci 1c.4 off # PCIe Port #5 + end + device pci 1c.5 off # PCIe Port #6 + end + device pci 1c.6 off # PCIe Port #7 + end + device pci 1c.7 off # PCIe Port #8 + end + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x17aa 0x2207 + end + device pci 1e.0 off # PCI bridge + end + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x17aa 0x2207 + chip ec/lenovo/pmh7 + register "backlight_enable" = "0x01" + register "dock_event_enable" = "0x01" + device pnp ff.1 on # dummy + end + end + chip ec/lenovo/h8 # FIXME: has_keyboard_backlight, has_power_management_beeps, has_uwb + register "beepmask0" = "0x00" + register "beepmask1" = "0x86" + register "config0" = "0xa6" + register "config1" = "0x29" + register "config2" = "0xa1" + register "config3" = "0xc0" + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xf0" + register "event5_enable" = "0x3c" + register "event7_enable" = "0x01" + register "event8_enable" = "0x7b" + register "event9_enable" = "0xff" + register "eventb_enable" = "0x80" + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + register "evente_enable" = "0x1d" + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end + end + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x17aa 0x2207 + end + device pci 1f.3 on # SMBus + subsystemid 0x17aa 0x2207 + chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip + device i2c 54 on + end + device i2c 55 on + end + device i2c 56 on + end + device i2c 57 on + end + device i2c 5c on + end + device i2c 5d on + end + device i2c 5e on + end + device i2c 5f on + end + end + end + device pci 1f.5 off # SATA Controller 2 + end + device pci 1f.6 off # Thermal + end + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x17aa 0x2207 + end + device pci 01.0 off # PCIe Bridge for discrete graphics + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x17aa 0x2207 + end + end +end diff --git a/src/mainboard/lenovo/helix/dock.c b/src/mainboard/lenovo/helix/dock.c new file mode 100644 index 0000000..df84d02 --- /dev/null +++ b/src/mainboard/lenovo/helix/dock.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Christoph Pomaska <github(a)aufmachen.jetzt> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <ec/lenovo/h8/h8.h> + +void h8_mainboard_init_dock(void) +{ +/* FIXME: fill this if needed. */ +} diff --git a/src/mainboard/lenovo/helix/dsdt.asl b/src/mainboard/lenovo/helix/dsdt.asl new file mode 100644 index 0000000..4a55d4f --- /dev/null +++ b/src/mainboard/lenovo/helix/dsdt.asl @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Christoph Pomaska <github(a)aufmachen.jetzt> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +#define EC_LENOVO_H8_ME_WORKAROUND 1 +#define THINKPAD_EC_GPE 17 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/lenovo/helix/gma-mainboard.ads b/src/mainboard/lenovo/helix/gma-mainboard.ads new file mode 100644 index 0000000..ce27742 --- /dev/null +++ b/src/mainboard/lenovo/helix/gma-mainboard.ads @@ -0,0 +1,35 @@ +-- +-- This file is part of the coreboot project. +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/helix/gpio.c b/src/mainboard/lenovo/helix/gpio.c new file mode 100644 index 0000000..b1dcb0a --- /dev/null +++ b/src/mainboard/lenovo/helix/gpio.c @@ -0,0 +1,239 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_GPIO, + .gpio26 = GPIO_MODE_GPIO, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_LOW, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio3 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio6 = GPIO_INVERT, + .gpio11 = GPIO_INVERT, + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_GPIO, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_OUTPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio68 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/lenovo/helix/hda_verb.c b/src/mainboard/lenovo/helix/hda_verb.c new file mode 100644 index 0000000..32f1126 --- /dev/null +++ b/src/mainboard/lenovo/helix/hda_verb.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0269, /* Codec Vendor / Device ID: Realtek */ + 0x17aa2207, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x17aa2207), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x90a60130), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x0, 0x14, 0x90170110), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x03214020), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x0, 0x17, 0x40008008), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x0, 0x18, 0x03a19040), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x411111f0), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x411111f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x40f6862d), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x411111f0), + 0x80862806, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560020), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x58560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/helix/mainboard.c b/src/mainboard/lenovo/helix/mainboard.c new file mode 100644 index 0000000..040941d --- /dev/null +++ b/src/mainboard/lenovo/helix/mainboard.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Christoph Pomaska <github(a)aufmachen.jetzt> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_enable(struct device *dev) +{ + /* FIXME: fix those values*/ + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/helix/romstage.c b/src/mainboard/lenovo/helix/romstage.c new file mode 100644 index 0000000..ff8bd1d --- /dev/null +++ b/src/mainboard/lenovo/helix/romstage.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* FIXME: Check if all includes are needed. */ + +#include <stdint.h> +#include <string.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/gpio.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, 0 }, + { 1, 2, 1 }, + { 1, 1, 3 }, + { 1, 0, -1 }, + { 1, 1, 2 }, + { 1, 1, -1 }, + { 0, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 1, 5 }, + { 0, 0, -1 }, + { 1, 1, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +/* FIXME: Put proper SPD map here. */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x52, id_only); + read_spd(&spd[2], 0x51, id_only); + read_spd(&spd[3], 0x53, id_only); +} diff --git a/src/mainboard/lenovo/helix/smihandler.c b/src/mainboard/lenovo/helix/smihandler.c new file mode 100644 index 0000000..a235c3e --- /dev/null +++ b/src/mainboard/lenovo/helix/smihandler.c @@ -0,0 +1,104 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/acpi/ec.h> +#include <ec/lenovo/h8/h8.h> +#include <delay.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/pmutil.h> + +#define GPE_EC_SCI 1 +/* FIXME: check this */ +#define GPE_EC_WAKE 13 + +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); + /* Enable 0x1600/0x1600 register pair */ + ec_set_bit(0x00, 0x05); +} + +int mainboard_io_trap_handler(int smif) +{ + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + + return 0; +} + +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = inb(EC_SC); + u8 event; + + if (!(status & EC_SCI_EVT)) + return; + + event = ec_query(); + printk(BIOS_DEBUG, "EC event %02x\n", event); +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << GPE_EC_SCI)) + mainboard_smi_handle_ec_sci(); +} + +int mainboard_smi_apmc(u8 data) +{ + switch (data) { + case APM_CNT_ACPI_ENABLE: + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route EC_SCI to SCI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SCI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_ACPI_DISABLE: + /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't + provide a EC query function */ + ec_set_ports(0x66, 0x62); + /* route EC_SCI to SMI */ + gpi_route_interrupt(GPE_EC_SCI, GPI_IS_SMI); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + default: + break; + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == 3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ + if (ec_wake & 0x14) { + /* Redirect EC WAKE GPE to SCI. */ + gpi_route_interrupt(GPE_EC_WAKE, GPI_IS_SCI); + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33867 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7dbf10bc85edb161fce077568d4ef3db91e10db7 Gerrit-Change-Number: 33867 Gerrit-PatchSet: 1 Gerrit-Owner: Christoph Pomaska <github(a)aufmachen.jetzt> Gerrit-MessageType: newchange

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coreboot-gerrit July 2019