V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30615
Change subject: mb/google/hatch: Disable the eMMC controller for hatch
......................................................................
mb/google/hatch: Disable the eMMC controller for hatch
eMMC controller is not used in hatch hence this patch adds the
Kconfig option to disable the eMMC controller ACPI entries.
BUG=b:120914069
BRANCH=none
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot.
Change-Id: Ie52c4fa581ad2c9b14e57919a63b3128bd928596
Signed-off-by: V Sowmya <v.sowmya(a)intel.com>
---
M src/mainboard/google/hatch/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/30615/1
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index 711d2e9..15fe354 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -15,6 +15,7 @@
select SOC_INTEL_CANNONLAKE_MEMCFG_INIT
select SOC_INTEL_COFFEELAKE
select SYSTEM_TYPE_LAPTOP
+ select EXCLUDE_EMMC_INTERFACE
if BOARD_GOOGLE_BASEBOARD_HATCH
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie52c4fa581ad2c9b14e57919a63b3128bd928596
Gerrit-Change-Number: 30615
Gerrit-PatchSet: 1
Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com>
Gerrit-MessageType: newchange
Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30747
Change subject: cpu/amd/microcode: Search all containers
......................................................................
cpu/amd/microcode: Search all containers
Currently, it’s aborted if the first file is not found.
The commit was only tested with all microcode containers present in
CBFS.
If only one microcode update container is present, which is not the
first, it is skipped.
Change the return to continue to traverse all elements.
Fixes: 83e4c5613 (cpu/amd/microcode: Update parser to use stock microcode blobs)
Change-Id: I5195ff0334cf49cadc25de31822a9f2f2cd90490
Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de>
---
M src/cpu/amd/microcode/microcode.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/30747/1
diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c
index e8ab175..622c6db 100644
--- a/src/cpu/amd/microcode/microcode.c
+++ b/src/cpu/amd/microcode/microcode.c
@@ -214,7 +214,7 @@
spin_unlock(romstage_microcode_cbfs_lock());
#endif
#endif
- return;
+ continue;
}
amd_update_microcode(ucode, ucode_len, equivalent_processor_rev_id);
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I5195ff0334cf49cadc25de31822a9f2f2cd90490
Gerrit-Change-Number: 30747
Gerrit-PatchSet: 1
Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-MessageType: newchange
Hello Marco Chen,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/33661
to review the following change.
Change subject: vendorcode/google: load sar config from CBFS first then VPD
......................................................................
vendorcode/google: load sar config from CBFS first then VPD
SAR config provisioned in RO VPD can be done in the factory only. Once
it is wrong, we can override the SAR config by updating FW RW which can
carry new SAR config in CBFS. As a result, we should check CBFS first
then VPD.
Change-Id: I5aa6235fb7a6d0b2ed52893a42f7bd57806af6c1
Signed-off-by: Marco Chen <marcochen(a)chromium.org>
---
M src/vendorcode/google/chromeos/sar.c
1 file changed, 23 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/33661/1
diff --git a/src/vendorcode/google/chromeos/sar.c b/src/vendorcode/google/chromeos/sar.c
index bbcb211..a5a2c3b 100644
--- a/src/vendorcode/google/chromeos/sar.c
+++ b/src/vendorcode/google/chromeos/sar.c
@@ -82,36 +82,37 @@
sizeof(struct wifi_sar_delta_table);
}
- /* Try to read the SAR limit entry from VPD */
- if (!vpd_gets(wifi_sar_limit_key, wifi_sar_limit_str,
- buffer_size, VPD_ANY)) {
- printk(BIOS_ERR, "Error: Could not locate '%s' in VPD.\n",
- wifi_sar_limit_key);
-
- if (!CONFIG(WIFI_SAR_CBFS))
- return -1;
-
+ if (CONFIG(WIFI_SAR_CBFS)) {
printk(BIOS_DEBUG, "Checking CBFS for default SAR values\n");
sar_cbfs_len = load_sar_file_from_cbfs(
(void *) wifi_sar_limit_str,
sar_expected_len);
- if (sar_cbfs_len != sar_expected_len) {
- printk(BIOS_ERR, "%s has bad len in CBFS\n",
- WIFI_SAR_CBFS_FILENAME);
- return -1;
- }
- } else {
- /* VPD key "wifi_sar" found. strlen is checked with addition of
- * 1 as we have created buffer size 1 char larger for the reason
- * mentioned at start of this function itself */
- if (strlen(wifi_sar_limit_str) + 1 != sar_expected_len) {
- printk(BIOS_ERR, "WIFI SAR key has bad len in VPD\n");
- return -1;
- }
+ if (sar_cbfs_len == sar_expected_len)
+ goto done;
+
+ printk(BIOS_ERR, "%s has bad len in CBFS\n",
+ WIFI_SAR_CBFS_FILENAME);
}
+ /* Try to read the SAR limit entry from VPD */
+ if (!vpd_gets(wifi_sar_limit_key, wifi_sar_limit_str,
+ buffer_size, VPD_ANY)) {
+ printk(BIOS_ERR, "Error: Could not locate '%s' in VPD.\n",
+ wifi_sar_limit_key);
+ return -1;
+ }
+
+ /* VPD key "wifi_sar" found. strlen is checked with addition of
+ * 1 as we have created buffer size 1 char larger for the reason
+ * mentioned at start of this function itself */
+ if (strlen(wifi_sar_limit_str) + 1 != sar_expected_len) {
+ printk(BIOS_ERR, "WIFI SAR key has bad len in VPD\n");
+ return -1;
+ }
+
+done:
/* Decode the heximal encoded string to binary values */
if (hexstrtobin(wifi_sar_limit_str, bin_buffer, bin_buff_adjusted_size)
< bin_buff_adjusted_size) {
--
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I5aa6235fb7a6d0b2ed52893a42f7bd57806af6c1
Gerrit-Change-Number: 33661
Gerrit-PatchSet: 1
Gerrit-Owner: Marco Chen <marcochen(a)google.com>
Gerrit-Reviewer: Marco Chen <marcochen(a)chromium.org>
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