coreboot-gerrit July 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: configs: add ASUS AM1I-A sample configuration
by Mike Banon (Code Review) 01 Jun '22

01 Jun '22

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33800 Change subject: configs: add ASUS AM1I-A sample configuration ...................................................................... configs: add ASUS AM1I-A sample configuration You can use this .config as the base configuration for your AM1I-A by saving it to ./coreboot/.config - however, you may want to change some of its' configs! If you are using a SSD - you may want to change the "CONFIG_HUDSON_SATA_MODE" from "0: NATIVE" to "2: AHCI". In addition, I have disabled Intel WiFi adapter at my .config to save some space ( CONFIG_DRIVERS_INTEL_WIFI is not set ). If you have any questions/suggestions regarding this .config, please contact me. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ide7529762813944b4f91b2ee8b3ef327b5daffc4 --- A configs/config.asus_am1i-a 1 file changed, 789 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/33800/1 diff --git a/configs/config.asus_am1i-a b/configs/config.asus_am1i-a new file mode 100644 index 0000000..0660c44 --- /dev/null +++ b/configs/config.asus_am1i-a @@ -0,0 +1,789 @@ +######### +### +### ./coreboot/.config for ASUS AM1I-A - 26 Jun 2019 +### +######### +# +# Automatically generated file; DO NOT EDIT. +# coreboot configuration +# + +# +# General setup +# +CONFIG_COREBOOT_BUILD=y +CONFIG_LOCALVERSION="" +CONFIG_CBFS_PREFIX="fallback" +CONFIG_COMPILER_GCC=y +# CONFIG_COMPILER_LLVM_CLANG is not set +# CONFIG_ANY_TOOLCHAIN is not set +# CONFIG_CCACHE is not set +# CONFIG_FMD_GENPARSER is not set +# CONFIG_UTIL_GENPARSER is not set +CONFIG_USE_OPTION_TABLE=y +# CONFIG_STATIC_OPTION_TABLE is not set +CONFIG_COMPRESS_RAMSTAGE=y +CONFIG_INCLUDE_CONFIG_FILE=y +CONFIG_COLLECT_TIMESTAMPS=y +# CONFIG_TIMESTAMPS_ON_CONSOLE is not set +# CONFIG_USE_BLOBS is not set +# CONFIG_COVERAGE is not set +# CONFIG_UBSAN is not set +# CONFIG_NO_RELOCATABLE_RAMSTAGE is not set +CONFIG_RELOCATABLE_RAMSTAGE=y +# CONFIG_UPDATE_IMAGE is not set +# CONFIG_BOOTSPLASH_IMAGE is not set + +# +# Mainboard +# + +# +# Important: Run 'make distclean' before switching boards +# +# CONFIG_VENDOR_ADI is not set +# CONFIG_VENDOR_ADLINK is not set +# CONFIG_VENDOR_ADVANSUS is not set +# CONFIG_VENDOR_AMD is not set +# CONFIG_VENDOR_AOPEN is not set +# CONFIG_VENDOR_APPLE is not set +# CONFIG_VENDOR_ASROCK is not set +CONFIG_VENDOR_ASUS=y +# CONFIG_VENDOR_AVALUE is not set +# CONFIG_VENDOR_BAP is not set +# CONFIG_VENDOR_BIOSTAR is not set +# CONFIG_VENDOR_CAVIUM is not set +# CONFIG_VENDOR_COMPULAB is not set +# CONFIG_VENDOR_CUBIETECH is not set +# CONFIG_VENDOR_ELMEX is not set +# CONFIG_VENDOR_EMULATION is not set +# CONFIG_VENDOR_ESD is not set +# CONFIG_VENDOR_FACEBOOK is not set +# CONFIG_VENDOR_FOXCONN is not set +# CONFIG_VENDOR_GETAC is not set +# CONFIG_VENDOR_GIGABYTE is not set +# CONFIG_VENDOR_GIZMOSPHERE is not set +# CONFIG_VENDOR_GOOGLE is not set +# CONFIG_VENDOR_HP is not set +# CONFIG_VENDOR_IBASE is not set +# CONFIG_VENDOR_IEI is not set +# CONFIG_VENDOR_INTEL is not set +# CONFIG_VENDOR_JETWAY is not set +# CONFIG_VENDOR_KONTRON is not set +# CONFIG_VENDOR_LENOVO is not set +# CONFIG_VENDOR_LIPPERT is not set +# CONFIG_VENDOR_MSI is not set +# CONFIG_VENDOR_OCP is not set +# CONFIG_VENDOR_OPENCELLULAR is not set +# CONFIG_VENDOR_PACKARDBELL is not set +# CONFIG_VENDOR_PCENGINES is not set +# CONFIG_VENDOR_PURISM is not set +# CONFIG_VENDOR_RODA is not set +# CONFIG_VENDOR_SAMSUNG is not set +# CONFIG_VENDOR_SAPPHIRE is not set +# CONFIG_VENDOR_SCALEWAY is not set +# CONFIG_VENDOR_SIEMENS is not set +# CONFIG_VENDOR_SIFIVE is not set +# CONFIG_VENDOR_SUPERMICRO is not set +# CONFIG_VENDOR_TI is not set +# CONFIG_VENDOR_TYAN is not set +# CONFIG_VENDOR_UP is not set +# CONFIG_VENDOR_VIA is not set +CONFIG_BOARD_SPECIFIC_OPTIONS=y +CONFIG_MAINBOARD_DIR="asus/am1i-a" +CONFIG_MAINBOARD_PART_NUMBER="AM1I-A" +CONFIG_MAX_CPUS=4 +CONFIG_CBFS_SIZE=0x800000 +CONFIG_UART_FOR_CONSOLE=0 +CONFIG_PAYLOAD_CONFIGFILE="$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios" +CONFIG_MAINBOARD_VENDOR="ASUS" +CONFIG_HW_MEM_HOLE_SIZEK=0x200000 +CONFIG_IRQ_SLOT_COUNT=9 +CONFIG_VGA_BIOS_ID="1002,9830" +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +# CONFIG_HUDSON_LEGACY_FREE is not set +CONFIG_DIMM_SPD_SIZE=256 +CONFIG_VGA_BIOS=y +CONFIG_MAINBOARD_SERIAL_NUMBER="123456789" +CONFIG_AZ_PIN=0xaa +CONFIG_VGA_BIOS_FILE="pci1002,9830.rom" +CONFIG_C_ENV_BOOTBLOCK_SIZE=0x10000 +CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="ASUS" +CONFIG_DEVICETREE="devicetree.cb" +CONFIG_BOARD_ASUS_AM1I_A=y +# CONFIG_BOARD_ASUS_F2A85_M is not set +# CONFIG_BOARD_ASUS_F2A85_M_PRO is not set +# CONFIG_BOARD_ASUS_F2A85_M_LE is not set +# CONFIG_BOARD_ASUS_H61M_CS is not set +# CONFIG_BOARD_ASUS_KCMA_D8 is not set +# CONFIG_BOARD_ASUS_KFSN4_DRE is not set +# CONFIG_BOARD_ASUS_KGPE_D16 is not set +# CONFIG_BOARD_ASUS_M4A78_EM is not set +# CONFIG_BOARD_ASUS_M4A785M is not set +# CONFIG_BOARD_ASUS_M4A785TM is not set +# CONFIG_BOARD_ASUS_M5A88_V is not set +# CONFIG_BOARD_ASUS_MAXIMUS_IV_GENE_Z is not set +# CONFIG_BOARD_ASUS_P2B_D is not set +# CONFIG_BOARD_ASUS_P2B_DS is not set +# CONFIG_BOARD_ASUS_P2B_F is not set +# CONFIG_BOARD_ASUS_P2B_LS is not set +# CONFIG_BOARD_ASUS_P2B is not set +# CONFIG_BOARD_ASUS_P3B_F is not set +# CONFIG_BOARD_ASUS_P5GC_MX is not set +# CONFIG_BOARD_ASUS_P5QC is not set +# CONFIG_BOARD_ASUS_P5Q_PRO is not set +# CONFIG_BOARD_ASUS_P5QL_PRO is not set +# CONFIG_BOARD_ASUS_P5QPL_AM is not set +# CONFIG_BOARD_ASUS_P5G41T_M_LX is not set +# CONFIG_BOARD_ASUS_P8H61_M_LX is not set +# CONFIG_BOARD_ASUS_P8H61_M_PRO is not set +# CONFIG_HUDSON_IMC_FWM is not set +# CONFIG_HUDSON_XHCI_FWM is not set +CONFIG_DCACHE_RAM_BASE=0x30000 +CONFIG_DCACHE_RAM_SIZE=0x10000 +CONFIG_MAX_REBOOT_CNT=3 +CONFIG_OVERRIDE_DEVICETREE="" +CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0 +CONFIG_FMDFILE="" +CONFIG_MMCONF_BASE_ADDRESS=0xF8000000 +CONFIG_DRIVERS_UART_8250IO=y +# CONFIG_VBOOT is not set +CONFIG_DIMM_MAX=4 +CONFIG_TPM_PIRQ=0x0 +CONFIG_TTYS0_LCS=3 +CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="AM1I-A" +CONFIG_CPU_ADDR_BITS=40 +# CONFIG_USBDEBUG is not set +CONFIG_MAINBOARD_VERSION="1.0" +# CONFIG_DRIVERS_PS2_KEYBOARD is not set +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_SMBIOS_ENCLOSURE_TYPE=0x03 +CONFIG_HEAP_SIZE=0xc0000 +CONFIG_BOARD_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set +CONFIG_COREBOOT_ROMSIZE_KB_8192=y +# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set +# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set +CONFIG_COREBOOT_ROMSIZE_KB=8192 +CONFIG_ROM_SIZE=0x800000 +# CONFIG_SYSTEM_TYPE_LAPTOP is not set +# CONFIG_SYSTEM_TYPE_TABLET is not set +# CONFIG_SYSTEM_TYPE_DETACHABLE is not set +# CONFIG_SYSTEM_TYPE_CONVERTIBLE is not set +# CONFIG_CBFS_AUTOGEN_ATTRIBUTES is not set + +# +# Chipset +# + +# +# SoC +# +CONFIG_UDELAY_LAPIC_FIXED_FSB=200 +CONFIG_MMCONF_BUS_NUMBER=64 +CONFIG_S3_VGA_ROM_RUN=y +CONFIG_EHCI_BAR=0xfef00000 +CONFIG_ACPI_CPU_STRING="\\_PR.CP%02d" +# CONFIG_SOC_CAVIUM_CN81XX is not set +CONFIG_ARCH_ARMV8_EXTENSION=0 +CONFIG_STACK_SIZE=0x1000 +# CONFIG_SOC_CAVIUM_COMMON is not set +# CONFIG_SOC_INTEL_GLK is not set +CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y +CONFIG_ROMSTAGE_ADDR=0x2000000 +CONFIG_VERSTAGE_ADDR=0x2000000 +CONFIG_PCIEXP_ASPM=y +CONFIG_PCIEXP_COMMON_CLOCK=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_TTYS0_BASE=0x3f8 +# CONFIG_SOC_INTEL_CANNONLAKE_ALTERNATE_HEADERS is not set +# CONFIG_SOC_INTEL_COFFEELAKE is not set +# CONFIG_SOC_INTEL_WHISKEYLAKE is not set +# CONFIG_SOC_INTEL_COMETLAKE is not set +# CONFIG_SOC_INTEL_CANNONLAKE_PCH_H is not set +CONFIG_UART_PCI_ADDR=0x0 +# CONFIG_SOC_MEDIATEK_MT8173 is not set +# CONFIG_SOC_MEDIATEK_MT8183 is not set +# CONFIG_SOC_NVIDIA_TEGRA124 is not set +# CONFIG_SOC_NVIDIA_TEGRA210 is not set +# CONFIG_SOC_QUALCOMM_COMMON is not set +# CONFIG_SOC_QC_IPQ40XX is not set +# CONFIG_SOC_QC_IPQ806X is not set +# CONFIG_SOC_QUALCOMM_QCS405 is not set +# CONFIG_SOC_QUALCOMM_SDM845 is not set +# CONFIG_SOC_ROCKCHIP_RK3288 is not set +# CONFIG_SOC_ROCKCHIP_RK3399 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5250 is not set +# CONFIG_CPU_SAMSUNG_EXYNOS5420 is not set +# CONFIG_SOC_UCB_RISCV is not set + +# +# CPU +# +# CONFIG_CPU_ALLWINNER_A10 is not set +CONFIG_XIP_ROM_SIZE=0x100000 +CONFIG_NUM_IPI_STARTS=2 +CONFIG_CPU_AMD_AGESA=y +# CONFIG_ENABLE_MRC_CACHE is not set +CONFIG_S3_DATA_POS=0xFFFF0000 +CONFIG_S3_DATA_SIZE=32768 +CONFIG_CPU_AMD_AGESA_FAMILY16_KB=y +CONFIG_FORCE_AM1_SOCKET_SUPPORT=y +# CONFIG_CPU_AMD_PI is not set +# CONFIG_CPU_ARMLTD_CORTEX_A9 is not set +# CONFIG_SSE2 is not set +# CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE is not set +# CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED is not set +# CONFIG_CPU_TI_AM335X is not set +# CONFIG_PARALLEL_CPU_INIT is not set +# CONFIG_PARALLEL_MP is not set +# CONFIG_UDELAY_IO is not set +CONFIG_UDELAY_LAPIC=y +CONFIG_LAPIC_MONOTONIC_TIMER=y +# CONFIG_UDELAY_TSC is not set +# CONFIG_UDELAY_TIMER2 is not set +CONFIG_TSC_SYNC_LFENCE=y +# CONFIG_TSC_SYNC_MFENCE is not set +# CONFIG_NO_FIXED_XIP_ROM_SIZE is not set +CONFIG_LOGICAL_CPUS=y +# CONFIG_SMM_TSEG is not set +# CONFIG_SMM_LAPIC_REMAP_MITIGATION is not set +# CONFIG_SERIALIZED_SMM_INITIALIZATION is not set +CONFIG_X86_AMD_FIXED_MTRRS=y +# CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING is not set +# CONFIG_SOC_SETS_MSRS is not set +CONFIG_CACHE_AS_RAM=y +CONFIG_NO_CAR_GLOBAL_MIGRATION=y +CONFIG_SMP=y +# CONFIG_SUPPORT_CPU_UCODE_IN_CBFS is not set +# CONFIG_USES_MICROCODE_HEADER_FILES is not set + +# +# Northbridge +# +CONFIG_NORTHBRIDGE_AMD_AGESA=y +# CONFIG_CONSOLE_VGA_MULTI is not set +CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB=y +# CONFIG_NORTHBRIDGE_AMD_PI is not set +CONFIG_MAX_PIRQ_LINKS=4 + +# +# Southbridge +# +CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE=y +CONFIG_SOUTHBRIDGE_SPECIFIC_OPTIONS=y +CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/amd/agesa/hudson/bootblock.c" +# CONFIG_HUDSON_XHCI_ENABLE is not set +# CONFIG_HUDSON_IMC_ENABLE is not set +# CONFIG_HUDSON_GEC_FWM is not set +CONFIG_HUDSON_SATA_MODE=0 + +# +# NATIVE +# +CONFIG_ACPI_ENABLE_THERMAL_ZONE=y +# CONFIG_AMD_SB_CIMX is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set +# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ is not set +# CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN is not set +# CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM is not set +# CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE is not set + +# +# Super I/O +# +# CONFIG_SUPERIO_ASPEED_AST2400 is not set +# CONFIG_SUPERIO_ASPEED_COMMON_PRE_RAM is not set +CONFIG_SUPERIO_ITE_COMMON_PRE_RAM=y +CONFIG_SUPERIO_ITE_ENV_CTRL=y +CONFIG_SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG=y +CONFIG_SUPERIO_ITE_ENV_CTRL_8BIT_PWM=y +CONFIG_SUPERIO_ITE_ENV_CTRL_PWM_FREQ2=y +CONFIG_SUPERIO_ITE_IT8623E=y + +# +# Embedded Controllers +# +# CONFIG_EC_GOOGLE_WILCO is not set +CONFIG_EC_BASE_ACPI_DATA=0x930 +CONFIG_EC_BASE_ACPI_COMMAND=0x934 +CONFIG_EC_BASE_HOST_DATA=0x940 +CONFIG_EC_BASE_HOST_COMMAND=0x944 +CONFIG_EC_BASE_PACKET=0x950 +CONFIG_SEABIOS_PS2_TIMEOUT=0 + +# +# AMD Platform Initialization +# +# CONFIG_CPU_AMD_AGESA_BINARY_PI is not set +CONFIG_CPU_AMD_AGESA_OPENSOURCE=y +CONFIG_AGESA_EXTRA_TIMESTAMPS=y +# CONFIG_CAVIUM_BDK is not set +# CONFIG_MAINBOARD_HAS_CHROMEOS is not set +# CONFIG_GOOGLE_SMBIOS_MAINBOARD_VERSION is not set +# CONFIG_UEFI_2_4_BINDING is not set +# CONFIG_UDK_2015_BINDING is not set +# CONFIG_UDK_2017_BINDING is not set +CONFIG_UDK_2013_VERSION=2013 +CONFIG_UDK_2015_VERSION=2015 +CONFIG_UDK_2017_VERSION=2017 +CONFIG_UDK_VERSION=2013 +# CONFIG_USE_SIEMENS_HWILIB is not set +# CONFIG_ARCH_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARM is not set +# CONFIG_ARCH_VERSTAGE_ARM is not set +# CONFIG_ARCH_ROMSTAGE_ARM is not set +# CONFIG_ARCH_RAMSTAGE_ARM is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV4 is not set +# CONFIG_ARCH_VERSTAGE_ARMV4 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV4 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV4 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7 is not set +# CONFIG_ARCH_VERSTAGE_ARMV7 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_M is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_M is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV7_R is not set +# CONFIG_ARCH_VERSTAGE_ARMV7_R is not set +# CONFIG_ARCH_ROMSTAGE_ARMV7_R is not set +# CONFIG_ARCH_RAMSTAGE_ARMV7_R is not set +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARM64 is not set +# CONFIG_ARCH_VERSTAGE_ARM64 is not set +# CONFIG_ARCH_ROMSTAGE_ARM64 is not set +# CONFIG_ARCH_RAMSTAGE_ARM64 is not set +# CONFIG_ARCH_BOOTBLOCK_ARMV8_64 is not set +# CONFIG_ARCH_VERSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_ROMSTAGE_ARMV8_64 is not set +# CONFIG_ARCH_RAMSTAGE_ARMV8_64 is not set +# CONFIG_ARM64_USE_ARCH_TIMER is not set +# CONFIG_ARM64_A53_ERRATUM_843419 is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_BOOTBLOCK_MIPS is not set +# CONFIG_ARCH_VERSTAGE_MIPS is not set +# CONFIG_ARCH_ROMSTAGE_MIPS is not set +# CONFIG_ARCH_RAMSTAGE_MIPS is not set +# CONFIG_ARCH_PPC64 is not set +# CONFIG_ARCH_BOOTBLOCK_PPC64 is not set +# CONFIG_ARCH_VERSTAGE_PPC64 is not set +# CONFIG_ARCH_ROMSTAGE_PPC64 is not set +# CONFIG_ARCH_RAMSTAGE_PPC64 is not set +# CONFIG_ARCH_RISCV is not set +# CONFIG_ARCH_RISCV_M is not set +# CONFIG_ARCH_RISCV_S is not set +# CONFIG_ARCH_RISCV_U is not set +# CONFIG_ARCH_RISCV_RV64 is not set +# CONFIG_ARCH_RISCV_RV32 is not set +# CONFIG_ARCH_RISCV_PMP is not set +# CONFIG_ARCH_BOOTBLOCK_RISCV is not set +# CONFIG_ARCH_VERSTAGE_RISCV is not set +# CONFIG_ARCH_ROMSTAGE_RISCV is not set +# CONFIG_ARCH_RAMSTAGE_RISCV is not set +# CONFIG_RISCV_USE_ARCH_TIMER is not set +CONFIG_ARCH_X86=y +CONFIG_ARCH_BOOTBLOCK_X86_32=y +CONFIG_ARCH_VERSTAGE_X86_32=y +CONFIG_ARCH_ROMSTAGE_X86_32=y +CONFIG_ARCH_POSTCAR_X86_32=y +CONFIG_ARCH_RAMSTAGE_X86_32=y +# CONFIG_ARCH_BOOTBLOCK_X86_64 is not set +# CONFIG_ARCH_VERSTAGE_X86_64 is not set +# CONFIG_ARCH_ROMSTAGE_X86_64 is not set +# CONFIG_ARCH_POSTCAR_X86_64 is not set +# CONFIG_ARCH_RAMSTAGE_X86_64 is not set +# CONFIG_USE_MARCH_586 is not set +# CONFIG_AP_IN_SIPI_WAIT is not set +# CONFIG_SIPI_VECTOR_IN_ROM is not set +CONFIG_RAMBASE=0xe00000 +CONFIG_RAMTOP=0x1000000 +CONFIG_CBMEM_TOP_BACKUP=y +# CONFIG_EARLY_EBDA_INIT is not set +CONFIG_PC80_SYSTEM=y +# CONFIG_BOOTBLOCK_DEBUG_SPINLOOP is not set +# CONFIG_BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP is not set +CONFIG_HAVE_CMOS_DEFAULT=y +CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default" +CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y +# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set +# CONFIG_HPET_ADDRESS_OVERRIDE is not set +CONFIG_HPET_ADDRESS=0xfed00000 +CONFIG_ID_SECTION_OFFSET=0x80 +CONFIG_POSTCAR_STAGE=y +# CONFIG_VERSTAGE_DEBUG_SPINLOOP is not set +# CONFIG_ROMSTAGE_DEBUG_SPINLOOP is not set +CONFIG_BOOTBLOCK_SIMPLE=y +# CONFIG_BOOTBLOCK_NORMAL is not set +CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c" +CONFIG_ACPI_HAVE_PCAT_8259=y +# CONFIG_COLLECT_TIMESTAMPS_NO_TSC is not set +CONFIG_COLLECT_TIMESTAMPS_TSC=y +# CONFIG_PAGING_IN_CACHE_AS_RAM is not set +# CONFIG_IDT_IN_EVERY_STAGE is not set +CONFIG_HAVE_CF9_RESET=y +CONFIG_HAVE_CF9_RESET_PREPARE=y + +# +# Devices +# +CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y +CONFIG_HAVE_VBE_LINEAR_FRAMEBUFFER=y +# CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT is not set +# CONFIG_MAINBOARD_HAS_LIBGFXINIT is not set +CONFIG_VGA_ROM_RUN=y +# CONFIG_NO_GFX_INIT is not set +# CONFIG_ALWAYS_LOAD_OPROM is not set +CONFIG_ON_DEVICE_ROM_LOAD=y +# CONFIG_PCI_OPTION_ROM_RUN_REALMODE is not set +CONFIG_PCI_OPTION_ROM_RUN_YABEL=y +CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES=y +# CONFIG_YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG is not set +CONFIG_YABEL_VIRTMEM_LOCATION=0x1000000 +CONFIG_YABEL_DIRECTHW=y + +# +# Display +# +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +# CONFIG_FRAMEBUFFER_VESA_MODE_100 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_101 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_102 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_103 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_104 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_105 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_106 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_107 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_108 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_109 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10A is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10B is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10C is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10D is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10E is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_10F is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_110 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_111 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_112 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_113 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_114 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_115 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_116 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_117 is not set +CONFIG_FRAMEBUFFER_VESA_MODE_118=y +# CONFIG_FRAMEBUFFER_VESA_MODE_119 is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_11A is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_11B is not set +# CONFIG_FRAMEBUFFER_VESA_MODE_USER is not set +CONFIG_FRAMEBUFFER_VESA_MODE=0x118 +CONFIG_BOOTSPLASH=y +# CONFIG_VGA_TEXT_FRAMEBUFFER is not set +CONFIG_VBE_LINEAR_FRAMEBUFFER=y +CONFIG_LINEAR_FRAMEBUFFER=y +# CONFIG_SMBUS_HAS_AUX_CHANNELS is not set +CONFIG_PCI=y +# CONFIG_NO_MMCONF_SUPPORT is not set +CONFIG_MMCONF_SUPPORT=y +# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set +CONFIG_PCIX_PLUGIN_SUPPORT=y +CONFIG_CARDBUS_PLUGIN_SUPPORT=y +# CONFIG_AZALIA_PLUGIN_SUPPORT is not set +CONFIG_PCIEXP_PLUGIN_SUPPORT=y +# CONFIG_EARLY_PCI_BRIDGE is not set +CONFIG_SUBSYSTEM_VENDOR_ID=0x0000 +CONFIG_SUBSYSTEM_DEVICE_ID=0x0000 +# CONFIG_VGA_BIOS_DGPU is not set +# CONFIG_SOFTWARE_I2C is not set + +# +# Generic Drivers +# +# CONFIG_DRIVERS_AS3722_RTC is not set +# CONFIG_GIC is not set +# CONFIG_IPMI_KCS is not set +# CONFIG_DRIVERS_LENOVO_WACOM is not set +# CONFIG_RT8168_GET_MAC_FROM_VPD is not set +# CONFIG_RT8168_SET_LED_MODE is not set +# CONFIG_SMMSTORE_IN_CBFS is not set +CONFIG_SPI_FLASH=y +CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y +# CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY is not set +# CONFIG_SPI_FLASH_NO_FAST_READ is not set +CONFIG_SPI_FLASH_ADESTO=y +CONFIG_SPI_FLASH_AMIC=y +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y +# CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B is not set +# CONFIG_SPI_FLASH_HAS_VOLATILE_GROUP is not set +# CONFIG_HAVE_SPI_CONSOLE_SUPPORT is not set +CONFIG_DRIVERS_UART=y +# CONFIG_DRIVERS_UART_8250IO_SKIP_INIT is not set +# CONFIG_NO_UART_ON_SUPERIO is not set +# CONFIG_UART_OVERRIDE_INPUT_CLOCK_DIVIDER is not set +# CONFIG_UART_OVERRIDE_REFCLK is not set +# CONFIG_DRIVERS_UART_8250MEM is not set +# CONFIG_DRIVERS_UART_8250MEM_32 is not set +# CONFIG_HAVE_UART_SPECIAL is not set +# CONFIG_DRIVERS_UART_OXPCIE is not set +# CONFIG_DRIVERS_UART_PL011 is not set +# CONFIG_UART_USE_REFCLK_AS_INPUT_CLOCK is not set +CONFIG_HAVE_USBDEBUG=y +CONFIG_HAVE_USBDEBUG_OPTIONS=y +# CONFIG_VPD is not set +CONFIG_DRIVERS_AMD_PI=y +# CONFIG_SMBIOS_PROVIDED_BY_MOBO is not set +# CONFIG_DRIVERS_I2C_MAX98373 is not set +# CONFIG_DRIVERS_I2C_MAX98927 is not set +# CONFIG_DRIVERS_I2C_PCA9538 is not set +# CONFIG_DRIVERS_I2C_PCF8523 is not set +# CONFIG_DRIVERS_I2C_RT5663 is not set +# CONFIG_DRIVERS_I2C_RTD2132 is not set +# CONFIG_DRIVERS_I2C_RX6110SA is not set +# CONFIG_DRIVERS_I2C_SX9310 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_ATMEL is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_CR50 is not set +# CONFIG_MAINBOARD_HAS_I2C_TPM_GENERIC is not set +# CONFIG_PLATFORM_USES_FSP1_0 is not set +# CONFIG_PLATFORM_USES_FSP2_0 is not set +# CONFIG_PLATFORM_USES_FSP2_1 is not set +# CONFIG_INTEL_DDI is not set +# CONFIG_INTEL_EDID is not set +# CONFIG_INTEL_INT15 is not set +# CONFIG_INTEL_GMA_ACPI is not set +# CONFIG_INTEL_GMA_SSC_ALTERNATE_REF is not set +# CONFIG_INTEL_GMA_SWSMISCI is not set +# CONFIG_DRIVER_INTEL_I210 is not set +# CONFIG_DRIVERS_INTEL_MIPI_CAMERA is not set +# CONFIG_DRIVERS_INTEL_WIFI is not set +# CONFIG_USE_SAR is not set +# CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS is not set +# CONFIG_DRIVER_MAXIM_MAX77686 is not set +# CONFIG_DRIVER_PARADE_PS8625 is not set +# CONFIG_DRIVER_PARADE_PS8640 is not set +CONFIG_DRIVERS_MC146818=y +CONFIG_LPC_TPM=y +CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000 +CONFIG_MAINBOARD_HAS_LPC_TPM=y +# CONFIG_DRIVERS_RICOH_RCE822 is not set +# CONFIG_DRIVER_SIEMENS_NC_FPGA is not set +# CONFIG_NC_FPGA_NOTIFY_CB_READY is not set +# CONFIG_DRIVERS_SIL_3114 is not set +# CONFIG_MAINBOARD_HAS_SPI_TPM_CR50 is not set +# CONFIG_DRIVER_TI_TPS65090 is not set +# CONFIG_DRIVERS_TI_TPS65913 is not set +# CONFIG_DRIVERS_TI_TPS65913_RTC is not set +# CONFIG_DRIVERS_USB_ACPI is not set +# CONFIG_DRIVER_XPOWERS_AXP209 is not set +# CONFIG_COMMONLIB_STORAGE is not set + +# +# Security +# + +# +# Verified Boot (vboot) +# + +# +# Trusted Platform Module +# +CONFIG_USER_NO_TPM=y +# CONFIG_USER_TPM1 is not set +# CONFIG_USER_TPM2 is not set +# CONFIG_TPM_RDRESP_NEED_DELAY is not set +# CONFIG_ACPI_SATA_GENERATOR is not set +# CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES is not set +# CONFIG_ACPI_AMD_HARDWARE_SLEEP_VALUES is not set +# CONFIG_BOOT_DEVICE_NOT_SPI_FLASH is not set +CONFIG_BOOT_DEVICE_SPI_FLASH=y +CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y +# CONFIG_BOOT_DEVICE_SUPPORTS_WRITES is not set +# CONFIG_RTC is not set + +# +# Console +# +# CONFIG_POSTCAR_CONSOLE is not set +CONFIG_SQUELCH_EARLY_SMP=y +CONFIG_CONSOLE_SERIAL=y +CONFIG_CONSOLE_CBMEM=y +CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00 +CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 + +# +# I/O mapped, 8250-compatible +# + +# +# Serial port base address = 0x3f8 +# +# CONFIG_CONSOLE_SERIAL_921600 is not set +# CONFIG_CONSOLE_SERIAL_460800 is not set +# CONFIG_CONSOLE_SERIAL_230400 is not set +CONFIG_CONSOLE_SERIAL_115200=y +# CONFIG_CONSOLE_SERIAL_57600 is not set +# CONFIG_CONSOLE_SERIAL_38400 is not set +# CONFIG_CONSOLE_SERIAL_19200 is not set +# CONFIG_CONSOLE_SERIAL_9600 is not set +CONFIG_TTYS0_BAUD=115200 +# CONFIG_SPKMODEM is not set +# CONFIG_CONSOLE_NE2K is not set +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +# CONFIG_CONSOLE_SPI_FLASH is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set +# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set +# CONFIG_NO_POST is not set +# CONFIG_CMOS_POST is not set +# CONFIG_CONSOLE_POST is not set +CONFIG_POST_DEVICE=y +CONFIG_POST_DEVICE_NONE=y +# CONFIG_POST_DEVICE_LPC is not set +# CONFIG_POST_DEVICE_PCI_PCIE is not set +CONFIG_POST_IO=y +CONFIG_POST_IO_PORT=0x80 +# CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES is not set +CONFIG_HWBASE_DEBUG_CB=y +CONFIG_HAVE_ACPI_RESUME=y +# CONFIG_ACPI_HUGE_LOWMEM_BACKUP is not set +CONFIG_RESUME_PATH_SAME_AS_BOOT=y +# CONFIG_HAVE_ROMSTAGE_CONSOLE_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK is not set +# CONFIG_HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK is not set +CONFIG_HAVE_MONOTONIC_TIMER=y +# CONFIG_GENERIC_UDELAY is not set +# CONFIG_TIMER_QUEUE is not set +CONFIG_HAVE_OPTION_TABLE=y +# CONFIG_PIRQ_ROUTE is not set +# CONFIG_HAVE_SMI_HANDLER is not set +# CONFIG_PCI_IO_CFG_EXT is not set +CONFIG_IOAPIC=y +# CONFIG_USE_WATCHDOG_ON_BOOT is not set +CONFIG_GFXUMA=y +CONFIG_HAVE_ACPI_TABLES=y +CONFIG_HAVE_MP_TABLE=y +CONFIG_HAVE_PIRQ_TABLE=y +# CONFIG_COMMON_FADT is not set +# CONFIG_ACPI_NHLT is not set + +# +# System tables +# +CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_PIRQ_TABLE=y +CONFIG_GENERATE_SMBIOS_TABLES=y + +# +# Payload +# +# CONFIG_PAYLOAD_NONE is not set +# CONFIG_PAYLOAD_ELF is not set +# CONFIG_PAYLOAD_BAYOU is not set +# CONFIG_PAYLOAD_FILO is not set +# CONFIG_PAYLOAD_GRUB2 is not set +# CONFIG_PAYLOAD_LINUXBOOT is not set +CONFIG_PAYLOAD_SEABIOS=y +# CONFIG_PAYLOAD_UBOOT is not set +# CONFIG_PAYLOAD_YABITS is not set +# CONFIG_PAYLOAD_LINUX is not set +# CONFIG_PAYLOAD_TIANOCORE is not set +CONFIG_PAYLOAD_FILE="payloads/external/SeaBIOS/seabios/out/bios.bin.elf" +# CONFIG_SEABIOS_STABLE is not set +CONFIG_SEABIOS_MASTER=y +# CONFIG_SEABIOS_REVISION is not set +# CONFIG_SEABIOS_THREAD_OPTIONROMS is not set +CONFIG_SEABIOS_BOOTORDER_FILE="" +# CONFIG_SEABIOS_ADD_SERCON_PORT_FILE is not set +CONFIG_SEABIOS_DEBUG_LEVEL=-1 + +# +# Using default SeaBIOS log level +# +CONFIG_PAYLOAD_OPTIONS="" +# CONFIG_PXE is not set +CONFIG_COMPRESSED_PAYLOAD_LZMA=y +# CONFIG_COMPRESSED_PAYLOAD_LZ4 is not set +# CONFIG_PAYLOAD_IS_FLAT_BINARY is not set +CONFIG_COMPRESS_SECONDARY_PAYLOAD=y + +# +# Secondary Payloads +# +CONFIG_COREINFO_SECONDARY_PAYLOAD=y +# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set +# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set +CONFIG_TINT_SECONDARY_PAYLOAD=y + +# +# Debugging +# + +# +# CPU Debug Settings +# + +# +# General Debug Settings +# +# CONFIG_GDB_STUB is not set +# CONFIG_FATAL_ASSERTS is not set +# CONFIG_DEBUG_CBFS is not set +# CONFIG_HAVE_DEBUG_RAM_SETUP is not set +# CONFIG_DEBUG_PIRQ is not set +# CONFIG_HAVE_DEBUG_SMBUS is not set +# CONFIG_DEBUG_MALLOC is not set +# CONFIG_DEBUG_ACPI is not set +# CONFIG_DEBUG_CONSOLE_INIT is not set +# CONFIG_X86EMU_DEBUG is not set +# CONFIG_DEBUG_SPI_FLASH is not set +# CONFIG_TRACE is not set +# CONFIG_DEBUG_BOOT_STATE is not set +# CONFIG_DEBUG_ADA_CODE is not set +# CONFIG_HAVE_EM100_SUPPORT is not set +CONFIG_NO_EDID_FILL_FB=y +# CONFIG_ENABLE_APIC_EXT_ID is not set +CONFIG_WARNINGS_ARE_ERRORS=y +# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set +# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set +# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set +# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set +# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set +# CONFIG_REG_SCRIPT is not set +# CONFIG_NO_XIP_EARLY_STAGES is not set +# CONFIG_EARLY_CBMEM_LIST is not set +CONFIG_RELOCATABLE_MODULES=y +CONFIG_BOOTBLOCK_CUSTOM=y +CONFIG_HAVE_BOOTBLOCK=y +CONFIG_HAVE_ROMSTAGE=y +CONFIG_HAVE_POSTCAR=y +CONFIG_HAVE_RAMSTAGE=y + -- To view, visit https://review.coreboot.org/c/coreboot/+/33800 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide7529762813944b4f91b2ee8b3ef327b5daffc4 Gerrit-Change-Number: 33800 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

5 38

Change in ...coreboot[master]: csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches
by Mike Banon (Code Review) 01 Jun '22

01 Jun '22

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33509 Change subject: csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches ...................................................................... csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches Conveniently and securely gets, checks SHA256 and installs some of my patches from this page - https://review.coreboot.org/q/status:open+banon - and also gets a collection of useful floppy-based operating systems. Sometimes it takes quite a long time to get a patch merged, while the people might need it today! - and this script could be really helpful. It asks a [Y/N] question for every addition, and since there are some "universal" patches as well as great floppies, you may still want to run this script - even if your board is not Lenovo G505S or not AMD. Please share your feedback/suggestions and tell about other useful patches, preferably the "universal" ones - i.e. SeaBIOS. Currently included: 1) "board-specific": G505S dGPU support, G505S config and AtomBIOS ROMs 2) "universal": SeaBIOS patches: advanced_bootmenu, multiple_floppies, writeprotected_usb ; tint build system ; and also a floppies collection : KolibriOS, FreeDOS, MichalOS, Snowdrop, Fiwix, Memtest, Tatos, Plop, FloppyBird. Run ./csb_patcher.sh help or ./csb_patcher.sh usage for more information. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I66f4f2865ac63ce0f2615669c7a3abd70a397e49 --- A csb_patcher.sh 1 file changed, 876 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/33509/1 diff --git a/csb_patcher.sh b/csb_patcher.sh new file mode 100755 index 0000000..b325f71 --- /dev/null +++ b/csb_patcher.sh @@ -0,0 +1,876 @@ +#!/bin/sh +# +# csb_patcher.sh: coreboot and SeaBIOS patcher script. +# +# Conveniently and securely gets, checks SHA256 and installs some of my +# patches from this page - https://review.coreboot.org/q/status:open+banon +# and also gets a collection of useful floppy-based operating systems. +# Please send your feedback to Mike Banon <mikebdp2(a)gmail.com> +# + +# Keys +enter=$( printf '\015' ) +ctrl_c=$( printf '\003' ) +ctrl_x=$( printf '\030' ) +ctrl_z=$( printf '\032' ) + +# Formatting +bold="\e[1m" +bred="\e[1;31m" +bgreen="\e[1;32m" +byellow="\e[1;33m" +bend="\e[0m" + +# Asks a question '$1' and waits for Y/N user input, printing a decision - with '$2' message if Y. +yesno () { + printf "$1 [Y/N] " + yesno_old_stty_cfg=$( stty -g ) + stty raw -echo + while true ; do + yesno_answer=$( head -c 1 ) + case "$yesno_answer" in + *"$ctrl_c"*|"$ctrl_x"*|"$ctrl_z"*) + stty "$yesno_old_stty_cfg" + printf "${bred}TERMINATED${bend}\n" + exit 1 + ;; + *"y"*|"Y"*) + stty "$yesno_old_stty_cfg" + printf "${bgreen}YES${bend}$2\n" + return 0 + ;; + *"n"*|"N"*) + stty "$yesno_old_stty_cfg" + printf "${byellow}NO${bend}\n" + return 1 + ;; + esac + done +} + +# Waits until a user presses Enter. +encontinue () { + printf "\npress [ENTER] to continue... " + encontinue_old_stty_cfg=$( stty -g ) + stty raw -echo + while true ; do + encontinue_answer=$( head -c 1 ) + case "$encontinue_answer" in + *"$ctrl_c"*|"$ctrl_x"*|"$ctrl_z"*) + stty "$encontinue_old_stty_cfg" + printf "${bred}TERMINATED${bend}\n" + exit 1 + ;; + *"$enter"*) + stty "$encontinue_old_stty_cfg" + printf "\n" + return 0 + ;; + esac + done +} + +# Checks if a command '$1' exists. +command_exists() { + if [ ! -x "$( command -v $1 )" ] ; then + printf "\n${bred}ERROR${bend}: command ${bold}$1${bend} is not found !\n" + encontinue + return 1 + else + return 0 + fi +} + +# Checks if a file '$1' exists. +file_exists () { + if [ ! -f "$1" ] ; then + printf "\n${byellow}WARNING${bend}: file ${bold}$1${bend} is not found !\n" + encontinue + return 1 + else + return 0 + fi +} + +# Force removes a file '$2' and then copies a file '$1' to '$2'. +copier () { + if file_exists "$1" ; then + rm -f "$2" + cp "$1" "$2" + return 0 + else + return 1 + fi +} + +# Force removes a file '$2' and then moves a file '$1' to '$2'. +mover () { + if file_exists "$1" ; then + rm -f "$2" + mv "$1" "$2" + return 0 + else + return 1 + fi +} + +# Checks if line '$1' contains the text '$2'. +checker () { + case "$1" in + *"$2"*) + return 0 + ;; + *) + return 1 + ;; + esac +} + +# Prints the lines of a file '$2' which contain the text '$1'. +grepper () { + if file_exists "$2" ; then + while IFS= read -r grepper_line + do + case "$grepper_line" in + *"$1"*) + printf '%s\n' "$grepper_line" + ;; + esac + done < "$2" + return 0 + else + return 1 + fi +} + +# Checks if a file '$2' contains the text '$1'. +grepcheck () { + if file_exists "$2" ; then + while IFS= read -r grepcheck_line + do + case "$grepcheck_line" in + *"$1"*) + return 0 + ;; + esac + done < "$2" + return 1 + else + return 1 + fi +} + +# Replaces the lines containing the text '$2' of a file '$1' with a line '$3'. +sedder () { + if file_exists "$1" ; then + csb_sedder_tmp="./.csb_sedder" + rm -f "$csb_sedder_tmp" + while IFS= read -r sedder_line + do + case "$sedder_line" in + *"$2"*) + if [ ! -z "$3" ] ; then + printf '%s\n' "$3" >> "$csb_sedder_tmp" + fi + ;; + *) + printf '%s\n' "$sedder_line" >> "$csb_sedder_tmp" + ;; + esac + done < "$1" + mover "$csb_sedder_tmp" "$1" + return 0 + else + return 1 + fi +} + +# Downloads a file '$1' from a link '$2' using the options '$3' and checks if this was successful. +wgetter () { + rm -f "$1" + if [ -z "$3" ] ; then + wget "$2" + else + wget "$3" "$2" + fi + if [ -f "$1" ] ; then + wgetter_file_size=$(($( wc -c < "$1" ))) + if [ "$wgetter_file_size" -eq "0" ] ; then + rm -f "$1" + fi + fi + if [ ! -f "$1" ] ; then + printf "\n${byellow}WARNING${bend}: can't download a ${bold}$1${bend} file !" + printf "\n Please check your Internet connection and try again.\n" + encontinue + return 1 + else + return 0 + fi +} + +# Unzips the archive '$1', optional '$2' for -j path inside the archive, and then force removes it. +unzipper () { + if file_exists "$1" ; then + if [ -z "$2" ] ; then + unzip "$1" + else + unzip -j "$1" "$2" + fi + rm -f "$1" + return 0 + else + return 1 + fi +} + +# Expands a file '$1' with zeroes using a dd to '$2' size - e.g. to a standard floppy size 1474560. +expander () { + if file_exists "$1" && [ ! -z "$2" ] ; then + expander_file_size=$(($( wc -c < "$1" ))) + if [ "$expander_file_size" -lt "$2" ] ; then + dd if=/dev/zero of=$1 bs=1 count=1 seek="$(( $2 - 1 ))" conv=notrunc iflag=nocache + fi + return 0 + else + return 1 + fi +} + +# Compares sha256sum of '$1.img' floppy image with '$2' and creates a hidden '.$1' file if matches. +floppy_verifier () { + rm -f "./.$1" + cd ".." + if [ ! -z "$2" ] ; then + if file_exists "./floppies/$1.img" ; then + floppy_verifier_sha256sum_correct="$2 ./floppies/$1.img" + floppy_verifier_sha256sum_my=$( sha256sum "./floppies/$1.img" ) + printf "\n=== sha256sum should be:\n${bold}$floppy_verifier_sha256sum_correct${bend}\n" + if [ "$floppy_verifier_sha256sum_my" = "$floppy_verifier_sha256sum_correct" ] ; then + printf "^^^ this is correct, ./floppies/${bold}$1.img${bend} is verified and could be added.\n\n" + cd "./floppies/" + touch "./.$1" + return 0 + else + printf "${bold}^^^ ! MISMATCH for ./floppies/$1.img ! Check sha256sum manually: sha256sum ./floppies/$1.img${bend}\n" + encontinue + cd "./floppies/" + return 1 + fi + else + printf "\n${byellow}WARNING${bend}: cannot find ./floppies/${bold}$1.img${bend} !\n" + printf "\n Please re-download a set of floppies.\n" + encontinue + return 1 + fi + else + printf "\n${byellow}WARNING${bend}: ./floppies/${bold}$1.img${bend} - is a rolling release, its' SHA256 checksum" + printf "\n is changing constantly and not provided by $1 project, so not checked.\n" + encontinue + cd "./floppies/" + touch "./.$1" + return 0 + fi +} + +# Downloads a collection of floppies, for the purpose of adding them later to a coreboot ROM image. +floppy_mass_downloader () { + printf "\n" + if [ ! -d "./floppies/" ]; then + mkdir "./floppies/" + fi + cd "./floppies/" + # KOLIBRI + if command_exists "7za" ; then + if wgetter "./latest-img.7z" "https://builds.kolibrios.org/eng/latest-img.7z" ; then + rm -f "./kolibri.img" + 7za x "./latest-img.7z" + rm -f "./latest-img.7z" + floppy_verifier "kolibri" "" # IS A ROLLING RELEASE, NO SHA256 VERIFICATION + fi + else + printf "\n${byellow}WARNING${bend}: cannot get ./floppies/${bold}kolibri.img${bend} without ${bold}7za${bend}\n" + encontinue + fi + # FREEDOS + if wgetter "./FD12FLOPPY.zip" "https://www.freedos.org/download/download/FD12FLOPPY.zip" ; then + unzipper "./FD12FLOPPY.zip" "FLOPPY.img" + mover "./FLOPPY.img" "./freedos.img" + floppy_verifier "freedos" "de2fb84dc2f132324549e89d58c6383497ec1af538c5b0ecde389fb748b9d537" + fi + # MICHALOS + printf "\n${byellow}WARNING${bend}: getting ./floppies/${bold}michalos.img${bend} could take a couple of minutes...\n\n" + if wgetter "./MichalOS 2.0 Source.zip" "https://sourceforge.net/p/michalos/tickets/_discuss/thread/69ab1508c3/39cd/…" "--content-disposition" ; then + unzipper "./MichalOS 2.0 Source.zip" "disk_images/michalos.img" + floppy_verifier "michalos" "139e9d08881f646156971a0a061972ddca77057b8acf4164e36366271ab3658c" + fi + # SNOWDROP + if wgetter "./snowdrop.img" "http://sebastianmihai.com/downloads/snowdrop/snowdrop.img" ; then + floppy_verifier "snowdrop" "" # IS A ROLLING RELEASE, NO SHA256 VERIFICATION + fi + # FIWIX + if wgetter "./fiwix.img" "https://www.fiwix.org/fiwix-1.0.1-i386-initrd.img" "--output-document=fiwix.img" ; then + floppy_verifier "fiwix" "dbec2994ec619c9954327ab0b983ab24cd362406a2e515c35c79c79bd6417cfd" + fi + # MEMTEST + if wgetter "./memtest86+-5.01.floppy.zip" "https://www.memtest.org/download/5.01/memtest86+-5.01.floppy.zip" ; then + unzipper "./memtest86+-5.01.floppy.zip" "floppy/memtestp.bin" + expander "./memtestp.bin" "1474560" + mover "./memtestp.bin" "./memtest.img" + floppy_verifier "memtest" "364535abd0d105da9396df6015e480c4d4c52b07dcc4e1d4756bde8ef87a30f1" + fi + # TATOS + if wgetter "./tatos.img" "https://github.com/tatimmer/tatOS/raw/master/tatOS.img" "--output-document=tatos.img" ; then + expander "./tatos.img" "1474560" + floppy_verifier "tatos" "2c66f884498a4fe7b469bc213aebfccd84a09fd7ace1b3b4b3e747e2392c35d1" + fi + # PLOP + if wgetter "./plpbt-5.0.15.zip" "https://download.plop.at/files/bootmngr/plpbt-5.0.15.zip" ; then + unzipper "./plpbt-5.0.15.zip" "plpbt-5.0.15/plpbt.img" + mover "./plpbt.img" "./plop.img" + floppy_verifier "plop" "f170759966ec4efe60c8531158344a234d7543c8de81e54c8c1bb9d2d69eaf27" + fi + # FLOPPYBIRD + if wgetter "./floppybird.img" "https://github.com/mikebdp2/floparchive/raw/master/floppies_extra/floppybir…" ; then + floppy_verifier "floppybird" "5db1b469e25e9eda7b8c0f666d6b655bab083c85618a9453ee72f1201cca840f" + fi + # Some floppies have the weird permissions after their extraction + floppy_mass_downloader_floppies=$( find . -name "*.img" ) + if [ ! -z "$floppy_mass_downloader_floppies" ] ; then + chmod 755 "./"*".img" + fi + # Return back to ./coreboot/ + cd ".." + return 0 +} + +# Adds a './pci1002,$1.rom' to coreboot '$3' ROM using '$2' cbfstool, printing '$4'/'$5'/'$6' info. +atombios_adder () { + if file_exists "$2" && file_exists "$3" ; then + if [ -f "./pci1002,$1.rom" ] ; then + atombios_adder_cbfs=$( "$2" "$3" print ) + if checker "$atombios_adder_cbfs" "pci1002,$1.rom" ; then + printf "\n${bgreen}NOTE${bend}: ./${bold}pci1002,$1.rom${bend} for ${bold}$5 : $6${bend} is already at your $3.\n" + else + if yesno "\nAdd a ./${bold}pci1002,$1.rom${bend} for ${bold}$5 : $6${bend} to your $3 now? ${bold}~$4${bend}" ", adding..." ; then + "$2" "$3" add -f "./pci1002,$1.rom" -n "pci1002,$1.rom" -t optionrom + else + printf "\n${bold}You can add it later by running:${bend}" + printf "\n${bold} $2 $3 add -f ./pci1002,$1.rom -n pci1002,$1.rom -t optionrom${bend}\n\n" + fi + fi + return 0 + else + printf "\n${byellow}WARNING${bend}: cannot find ./${bold}pci1002,$1.rom${bend} ," + printf "\n please re-apply ${bold}AMD atombios${bend} patch.\n" + encontinue + return 1 + fi + else + return 1 + fi +} + +# Adds a '$1.img' floppy image to coreboot '$3' ROM using '$2' cbfstool, printing '$4' size info. +floppy_adder () { + if file_exists "$2" && file_exists "$3" ; then + if [ -f "./floppies/$1.img" ] ; then + if [ -f "./floppies/.$1" ] ; then + floppy_adder_cbfs=$( "$2" "$3" print ) + if checker "$floppy_adder_cbfs" "floppyimg/$1.lzma" ; then + printf "\n${bgreen}NOTE${bend}: ./floppies/${bold}$1.img${bend} is already at your $3.\n" + else + if checker "$1" "plop" ; then + printf "\n${byellow}WARNING${bend}: ./floppies/${bold}$1.img${bend} - is proprietary: all its' source code is closed !" + printf "\n Add it only if you really need it and trust the author of $1 project.\n" + encontinue + fi + if yesno "\nAdd a ./floppies/${bold}$1.img${bend} to your $3 now? ${bold}~$4${bend}" ", adding..." ; then + "$2" "$3" add -f "./floppies/$1.img" -n "floppyimg/$1.lzma" -t raw -c lzma + else + printf "\n${bold}You can add it later by running:${bend}" + printf "\n${bold} $2 $3 add -f ./floppies/$1.img -n floppyimg/$1.lzma -t raw -c lzma${bend}\n\n" + fi + fi + return 0 + else + printf "\n${byellow}WARNING${bend}: there was a SHA256 mismatch for ./floppies/${bold}$1.img${bend} -" + printf "\n check sha256sum manually: sha256sum ./floppies/${bold}$1.img${bend}\n" + encontinue + return 1 + fi + else + printf "\n${byellow}WARNING${bend}: cannot find ./floppies/${bold}$1.img${bend} !\n" + printf "\n Please re-download a set of floppies.\n" + encontinue + return 1 + fi + else + return 1 + fi +} + +# Adds a set of AtomBIOS/floppies ('$1') to coreboot '$3' ROM copied to '$4', using '$2' cbfstool. +cbfs_mass_adder () { + if ! grepcheck "how to submit coreboot changes" ./MAINTAINERS ; then + printf "\n${byellow}WARNING${bend}: not sure if I am inside the coreboot directory," + printf "\n trying to add a ${bold}$1${bend} set from here - could fail.\n\n" + fi + if file_exists "$2" && file_exists "$3" ; then + if checker "$1" "atom" || checker "$1" "flop" ; then + copier "$3" "$4" + printf "\n${bold}=== $4 - initial memory map${bend}\n\n" + "$2" "$4" print + printf "\n" + if checker "$1" "atom" ; then +### +### https://review.coreboot.org/c/coreboot/+/31944 +### G505S AtomBIOS ROMs: known good binaries with a script to check their SHA256 +### + csb_patcher "atombios" "31944" "6" "78a8454" "9a8efff284bbdb81d5b912ccc8279162553e04673bde53e5288ba4bed0e4bc3d" "$1" "AMD " + atombios_adder "990b" "$2" "$4" "62K" "Lenovo G505S with A10-5750M" "iGPU HD-8650G" + atombios_adder "6663" "$2" "$4" "33K" "Lenovo G505S with A10-5750M" "dGPU HD-8570M" + atombios_adder "6665" "$2" "$4" "32K" "Lenovo G505S with A10-5750M" "dGPU R5-M230" + atombios_adder "9830" "$2" "$4" "59K" "ASUS AM1I-A with Athlon-5370" "iGPU HD-8400 / R3-Series" + atombios_adder "990c" "$2" "$4" "62K" "ASUS A88XM-E with A10-6700" "iGPU HD-8670D" + fi + if checker "$1" "flop" ; then + if [ ! -d "./floppies/" ] ; then + printf "\n" + floppy_mass_downloader + fi + # Default boot order: the last floppy added - is the first floppy to boot! + floppy_adder "floppybird" "$2" "$4" "2K" + floppy_adder "plop" "$2" "$4" "74K" + floppy_adder "tatos" "$2" "$4" "60K" + floppy_adder "memtest" "$2" "$4" "44K" + floppy_adder "fiwix" "$2" "$4" "458K" + floppy_adder "snowdrop" "$2" "$4" "126K" + floppy_adder "michalos" "$2" "$4" "256K" + floppy_adder "freedos" "$2" "$4" "698K" + floppy_adder "kolibri" "$2" "$4" "1264K" + fi + printf "\n${bold}=== $4 - final memory map${bend}\n\n" + "$2" "$4" print + printf "\nYou can use ./build/${bold}coreflop.rom${bend} now !\n\n" + return 0 + else + return 1 + fi + else + return 1 + fi +} + +# Finds the files of '$1' extension, saves the result to '$2' log and prints a message with '$3'. +csb_finder () { + csb_finder_files=$( find . -name "*.$1" ) + if [ ! -z "$csb_finder_files" ] ; then + printf "%25s\n" "*.$1 - YES" >> "$2" + printf "\n${byellow}WARNING${bend}: found ${bold}*.$1${bend} files at these locations :\n" + printf "$csb_finder_files" + printf "\n That means - Some patches $3\n" + encontinue + return 0 + else + printf "%24s\n" "*.$1 - NO" >> "$2" + return 1 + fi +} + +# Prints a csb_patcher_log '$1' with a custom highlighting. +csb_printer () { + if ! file_exists "$1" ; then + return 1 + fi + while IFS= read -r csb_printer_line + do + case "$csb_printer_line" in + *"orig - YES"*) + printf "${csb_printer_line%???}${byellow}YES" # YELLOW + ;; + *"rej - YES"*) + printf "${csb_printer_line%???}${bred}YES" # RED + ;; + *"YES"*) + printf "${csb_printer_line%???}${bgreen}YES" # GREEN + ;; + *"orig - NO"*|*"rej - NO"*) + printf "${csb_printer_line%??}${bgreen}NO" # GREEN + ;; + *"NO"*) + printf "${csb_printer_line%??}${byellow}NO" # YELLOW + ;; + *"FAILURE_1"*) + printf "${csb_printer_line%?????????}${bred}FAILURE_1" # RED + ;; + *"FAILURE_2"*) + printf "${csb_printer_line%?????????}${bred}FAILURE_2" # RED + ;; + *"FAILURE_3"*) + printf "${csb_printer_line%?????????}${bred}FAILURE_3" # RED + ;; + *"\\\\"*) + printf "${bold}${csb_printer_line%?????}\\\\\!//" # ALIEN HAIR + ;; + *) + printf "${bold}$csb_printer_line" + ;; + esac + printf "${bend}\n" + done < "$1" + return 0 +} + +# Configure some popular options of a config file '$1'. +csb_configurer () { + if file_exists "$1" ; then + csb_configurer_tmp="./.csb_configurer" + rm -f "$csb_configurer_tmp" + grepper "CONFIG_BOARD_" "$1" > "$csb_configurer_tmp" + if grepcheck "_LENOVO_G505S=y" "$csb_configurer_tmp" ; then + printf "\n\n${bgreen}[CONFIG]${bend} Questions about your Lenovo G505S\n\n" + sedder "$1" "### CSB_CONFIGURER OPTIONS" "" + printf "### CSB_CONFIGURER OPTIONS\n" >> "$1" + sedder "$1" "# CONFIG_DRIVERS_INTEL_WIFI is not set" "" + if ! yesno "Do you have an Intel WiFi adapter?" "" ; then + printf "# CONFIG_DRIVERS_INTEL_WIFI is not set\n" >> "$1" + fi + sedder "$1" "CONFIG_MULTIPLE_VGA_ADAPTERS=y" "" + sedder "$1" "CONFIG_VGA_BIOS_DGPU=y" "" + sedder "$1" "CONFIG_VGA_BIOS_DGPU_FILE=\"pci1002,6663.rom\"" "" + sedder "$1" "CONFIG_VGA_BIOS_DGPU_ID=\"1002,6663\"" "" + sedder "$1" "CONFIG_VGA_BIOS_DGPU_FILE=\"pci1002,6665.rom\"" "" + sedder "$1" "CONFIG_VGA_BIOS_DGPU_ID=\"1002,6665\"" "" + if yesno "Do you have a Discrete GPU?" "" ; then + printf "CONFIG_MULTIPLE_VGA_ADAPTERS=y\n" >> "$1" + printf "CONFIG_VGA_BIOS_DGPU=y\n" >> "$1" + if yesno "No for HD-8570M, Yes for R5-M230" "" ; then + printf "CONFIG_VGA_BIOS_DGPU_FILE=\"pci1002,6665.rom\"\n" >> "$1" + printf "CONFIG_VGA_BIOS_DGPU_ID=\"1002,6665\"\n" >> "$1" + else + printf "CONFIG_VGA_BIOS_DGPU_FILE=\"pci1002,6663.rom\"\n" >> "$1" + printf "CONFIG_VGA_BIOS_DGPU_ID=\"1002,6663\"\n" >> "$1" + fi + fi + + sedder "$1" "# NATIVE" "" + sedder "$1" "CONFIG_HUDSON_SATA_MODE=0" "" + + sedder "$1" "# RAID" "" + sedder "$1" "CONFIG_HUDSON_SATA_MODE=1" "" + sedder "$1" "CONFIG_RAID_ROM_ID=\"1022,7802\"" "" + sedder "$1" "CONFIG_RAID_ROM_FILE=\"src/southbridge/amd/agesa/hudson/raid.bin\"" "" + sedder "$1" "CONFIG_RAID_MISC_ROM_FILE=\"src/southbridge/amd/agesa/hudson/misc.bin\"" "" + sedder "$1" "CONFIG_RAID_MISC_ROM_POSITION=0xFFF00000" "" + + sedder "$1" "# AHCI" "" + sedder "$1" "CONFIG_HUDSON_SATA_MODE=2" "" + sedder "$1" "CONFIG_AHCI_ROM_ID=\"1022,7801\"" "" + sedder "$1" "# CONFIG_HUDSON_AHCI_ROM is not set" "" + + sedder "$1" "# LEGACY IDE" "" + sedder "$1" "CONFIG_HUDSON_SATA_MODE=3" "" + + sedder "$1" "# IDE to AHCI" "" + sedder "$1" "CONFIG_HUDSON_SATA_MODE=4" "" + + sedder "$1" "# AHCI7804" "" + sedder "$1" "CONFIG_HUDSON_SATA_MODE=5" "" + sedder "$1" "CONFIG_AHCI_ROM_ID=\"1022,7804\"" "" + + sedder "$1" "# IDE to AHCI7804" "" + sedder "$1" "CONFIG_HUDSON_SATA_MODE=6" "" + sedder "$1" "# CONFIG_HUDSON_AHCI_ROM is not set" "" + + if yesno "Do you have a SSD? (enable AHCI if Y)" "" ; then + printf "# AHCI\n" >> "$1" + printf "CONFIG_HUDSON_SATA_MODE=2\n" >> "$1" + printf "CONFIG_AHCI_ROM_ID=\"1022,7801\"\n" >> "$1" + printf "# CONFIG_HUDSON_AHCI_ROM is not set\n" >> "$1" + else + printf "# NATIVE\n" >> "$1" + printf "CONFIG_HUDSON_SATA_MODE=0\n" >> "$1" + fi + rm -f "$csb_configurer_tmp" + return 0 + else + printf "\n\n${byellow}WARNING${bend}: sorry, I don't know how to configure a board of ${bold}$1${bend}\n" + encontinue + return 1 + fi + else + return 1 + fi +} + +# +# Conveniently and securely gets, checks SHA256 and installs a patch. +# Arguments are the patch properties: +# $1 - new diff name, could be also a part of extracted scripts' filename +# $2 - change ID number, part of download link to review.coreboot.org +# $3 - change revision number, part of download link to review.coreboot.org +# $4 - diff filename inside the downloaded archive, will be renamed to $1 +# $5 - diff known good SHA256 checksum, will be used for SHA256 verification +# $6 - filepath where to save a csb_patcher_log which will be printed later +# $7 - info about the target of a patch, if not specified ("") it is common +# +csb_patcher () { + if ! wgetter "./patch?zip" "https://review.coreboot.org/changes/$2/revisions/$3/patch?zip" ; then + printf "${bold}^^^ ! Can't download a $7$1 patch ! Check your Internet.${bend}\n" + printf "%31s\n" "$7$1 - FAILURE_1" >> "$6" + csb_printer "$6" + exit 1 + fi + unzipper "./patch?zip" + mover "./$4.diff" "./$1.diff" + csb_patcher_sha256sum_correct="$5 ./$1.diff" + csb_patcher_sha256sum_my=$( sha256sum "./$1.diff" ) + printf "\n=== sha256sum should be:\n${bold}$csb_patcher_sha256sum_correct${bend}\n" + if [ "$csb_patcher_sha256sum_my" = "$csb_patcher_sha256sum_correct" ] ; then + printf "^^^ this is correct, " + csb_patcher_patch_title=$( grepper "Subject" "./$1.diff" ) + csb_patcher_patch_title=${csb_patcher_patch_title#?????????????????} + if [ "$1" = "dgpu" ] ; then + printf "will extract a ${bold}$7$1${bend} patch now...\n" + rm -f "./sha256sums_$1_correct.txt" + rm -f "./"*"_$1_patches.sh" + patch -p1 < "./$1.diff" + chmod +x "./"*"_$1_patches.sh" + "./get_$1_patches.sh" + if ! "./check_$1_patches.sh" ; then + printf "%31s\n" "$7$1 - FAILURE_3" >> "$6" + csb_printer "$6" + exit 1 + fi + else + printf "${bold}$7$1${bend} patch could be applied now...\n" + fi + if [ "$1" = "dgpu" ] || [ "$1" = "atombios" ] || \ + [ "$1" = "tint" ] || [ "$1" = "seabios" ] ; then + printf "\n\n${bgreen}[PATCH]${bend} $csb_patcher_patch_title\n\n" + if ! grepcheck "how to submit coreboot changes" ./MAINTAINERS ; then + printf "\n${byellow}WARNING${bend}: not sure if I am inside the coreboot directory," + printf "\n trying to add a ${bold}$1${bend} set from here - could fail.\n\n" + fi + if [ -f "./.$1" ] ; then + printf "\n${byellow}WARNING${bend}: found a '.$1' hidden file at the current directory," + printf "\n maybe you have applied this patch already.\n\n" + fi + if yesno "Apply a ${bold}$7$1${bend} patch now?" "" ; then + if [ "$1" = "dgpu" ] ; then + "./apply_$1_patches.sh" + else + if [ "$1" = "atombios" ] ; then + rm -f "./sha256sums_$1_correct.txt" + rm -f "./"*"_$1_roms.sh" + rm -f "./pci1002\,"*".rom" + rm -f "./pci1002\,"*".rom.txt" + fi + if [ "$1" = "tint" ] ; then + rm -f "./payloads/external/tint/tint.sh" + rm -f "./payloads/external/tint/"*"_core.sh" + rm -f "./payloads/external/tint/tint-0.04-nmu1_libpayload.patch" + fi + if [ "$1" = "seabios" ] ; then + rm -f "./payloads/external/SeaBIOS/"*".patch" + fi + patch -p1 < "./$1.diff" + if [ "$1" = "atombios" ] ; then + chmod +x "./"*"_$1_roms.sh" + "./extract_$1_roms.sh" + printf "\n" + if ! "./check_$1_roms.sh" ; then + printf "%31s\n" "$7$1 - FAILURE_3" >> "$6" + csb_printer "$6" + exit 1 + fi + fi + if [ "$1" = "tint" ] ; then + chmod +x "./payloads/external/tint/"*"_core.sh" + fi + fi + touch ".$1" + printf "%25s\n" "$7$1 - YES" >> "$6" + if [ "$1" = "atombios" ] ; then + encontinue + fi + else + printf "%24s\n" "$7$1 - NO" >> "$6" + printf "\n${bold}You can apply it later by running:${bend}" + if [ "$1" = "dgpu" ] ; then + printf "\n${bold} ./apply_$1_patches.sh${bend}\n" + else + printf "\n${bold} patch -p1 < ./$1.diff${bend}\n" + fi + encontinue + fi + fi + if checker "$1" "config" ; then + rm -f "./configs/$1_"* + patch -p1 < "./$1.diff" + printf "\n\n${bgreen}[PATCH]${bend} $csb_patcher_patch_title\n\n" + ls "./configs" > "./.csb_configs" + csb_patcher_config_name=$( grepper "$1" "./.csb_configs" ) + rm -f "./.csb_configs" + printf "\n${bold}$csb_patcher_config_name could now be found at ./configs/${bend}" + printf "\n${bold}To use it, it should be copied to '.config' of your ./coreboot directory.${bend}\n\n" + if [ -f "./.config" ] ; then + printf "\n${byellow}WARNING${bend}: copying it to ./.config will overwrite your current '.config'\n\n" + fi + if yesno "Copy it to ./.config now?" "" ; then + copier "./configs/$csb_patcher_config_name" "./.config" + printf "\n" + printf "%25s\n" "$7$1 - YES" >> "$6" + if yesno "Configure this ./.config now?" "" ; then + csb_configurer "./.config" + else + printf "\n${bold}You can configure it later by running:${bend}" + printf "\n${bold} ./csb_patcher.sh config${bend}\n\n" + fi + else + printf "%24s\n" "$7$1 - NO" >> "$6" + printf "\n${bold}You can copy it later by running:${bend}" + printf "\n${bold} cp ./configs/$csb_patcher_config_name ./.config${bend}\n" + fi + printf "\n${byellow}WARNING${bend}: important README at the beginning of ./$1.diff\n" + encontinue + fi + printf "\n\n" + return 0 + else + printf "${bold}^^^ ! MISMATCH for a $7$1 patch ! Check sha256sum manually: sha256sum ./$1.diff${bend}\n" + printf "%31s\n" "$7$1 - FAILURE_2" >> "$6" + csb_printer "$6" + exit 1 + fi +} + +# +# Conveniently and securely gets, checks SHA256 and applies my collection of unofficial patches. +# $1 - filepath where to save a csb_patcher_log which will be printed later +# +csb_mass_patcher () { +### +### https://review.coreboot.org/c/coreboot/+/31929 +### G505S dGPU support: scripts for applying the unofficial (not-merged-yet) patches +### + csb_patcher "dgpu" "31929" "13" "ed0c44f" "eb461931a1f34a8263405138eb1bf8d32a1f460026449c9ec1a9b9e7d8383f1c" "$1" "G505S " +### +### https://review.coreboot.org/c/coreboot/+/31944 +### G505S AtomBIOS ROMs: known good binaries with a script to check their SHA256 +### + csb_patcher "atombios" "31944" "6" "78a8454" "9a8efff284bbdb81d5b912ccc8279162553e04673bde53e5288ba4bed0e4bc3d" "$1" "AMD " +### +### https://review.coreboot.org/c/coreboot/+/23856 +### tint: introduce the new tint build system with checksum verification +### + csb_patcher "tint" "23856" "15" "14630b6" "7b9719f675d83750c7d4fb21b3abcbf1758ac6d1db20a9e8ef0db22f15761317" "$1" "" +### +### https://review.coreboot.org/c/coreboot/+/32351 +### SeaBIOS patches: advanced_bootmenu, multiple_floppies, writeprotected_usb +### + csb_patcher "seabios" "32351" "5" "4a9c3cd" "58348b0514446856d07078af443ac8a24cd3be8178290e7361a48a86d213a43b" "$1" "" +### +### https://review.coreboot.org/c/coreboot/+/32352 +### configs: add Lenovo G505S sample configuration (use with dGPU patches) +### +csb_patcher "config.lenovo_g505s" "32352" "12" "348d8ce" "5b3b663b3afe3fe5729be2632201f3665e75ed3848996901322d3528ed6dd897" "$1" "" + + return 0 +} + +# Prints a usage info for this ./csb_patcher.sh script. +csb_usage () { + printf "${bold}===============${bend} ${bgreen}USAGE${bend} ${bold}================${bend}\n\n" + printf "${bold}./csb_patcher.sh${bend}\n" + printf " patch your coreboot source code\n\n" + printf "${bold}./csb_patcher.sh${bend} ${byellow}help${bend} ${bold}|${bend} ${byellow}usage${bend}\n" + printf " print this usage info\n\n" + printf "${bold}==================== Before building :${bend}\n\n" + printf "${bold}./csb_patcher.sh ${byellow}config${bend}\n" + printf " configure some popular options\n\n" + printf "${bold}==================== After building :${bend}\n\n" + printf "${bold}./csb_patcher.sh ${byellow}atom${bend}\n" + printf " add the AtomBIOS to coreboot.rom\n\n" + printf "${bold}./csb_patcher.sh ${byellow}flop${bend}\n" + printf " add the floppies to coreboot.rom\n\n" + printf "${bold}./csb_patcher.sh ${byellow}atomflop${bend}\n" + printf " both AtomBIOS VGA ROMs and floppies\n\n" + printf "${bold}./csb_patcher.sh${bend} ${byellow}print${bend}\n" + printf " print a ./.csb_patcher log\n\n" + return 0 +} + +# +# MAIN PART OF A CSB_PATCHER SCRIPT +# + +if [ -z "$1" ] ; then + csb_patcher_log="./.csb_patcher" + rm -f "$csb_patcher_log" + if ! command_exists "wget" || \ + ! command_exists "unzip" || \ + ! command_exists "sha256sum" || \ + ! command_exists "patch" ; then + exit 1 + fi + printf '\n\n' >> "$csb_patcher_log" + printf ' \\\\!//\n' >> "$csb_patcher_log" + printf ' (o o)\n' >> "$csb_patcher_log" + printf ' oOOo-(_)-oOOo\n' >> "$csb_patcher_log" + printf 'Hi! I am coreboot and SeaBIOS patcher\n' >> "$csb_patcher_log" + printf 'Please send your feedback to\n' >> "$csb_patcher_log" + printf ' Mike Banon <mikebdp2(a)gmail.com>\n' >> "$csb_patcher_log" + csb_printer "$csb_patcher_log" + encontinue + printf '\n=== CSB_PATCHER LOG. Patches applied?\n' >> "$csb_patcher_log" + + csb_mass_patcher "$csb_patcher_log" + + if yesno "Download a ${bold}floppies${bend} collection?" "" ; then + floppy_mass_downloader + printf "%25s\n" "floppies - YES" >> "$csb_patcher_log" + else + printf "\n" + printf "%24s\n" "floppies - NO" >> "$csb_patcher_log" + fi + + printf '==================== Bad files found?\n' >> "$csb_patcher_log" + csb_finder "orig" "$csb_patcher_log" "applied correctly although at slightly different lines, can ignore it." + csb_finder "rej" "$csb_patcher_log" "perhaps failed to apply, could result in a broken build! ${bred}Please report${bend}" + + printf '\n' >> "$csb_patcher_log" + csb_printer "$csb_patcher_log" + csb_usage +else + case "$1" in + *"print"*) + csb_patcher_log="./.csb_patcher" + csb_printer "$csb_patcher_log" + ;; + *"config"*) + csb_configurer "./.config" + ;; + *"atom"*|*"flop"*) + if ! command_exists "wget" || \ + ! command_exists "unzip" || \ + ! command_exists "sha256sum" ; then + exit 1 + fi + cbfs_mass_adder "$1" "./build/cbfstool" "./build/coreboot.rom" "./build/coreflop.rom" + ;; + *"help"*|*"usage"*) + printf "\n" + csb_usage + ;; + *) + printf "\n${bred}ERROR${bend}: unknown argument ${bold}$1${bend} !\n\n" + csb_usage + exit 1 + ;; + esac +fi + +exit 0 + -- To view, visit https://review.coreboot.org/c/coreboot/+/33509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66f4f2865ac63ce0f2615669c7a3abd70a397e49 Gerrit-Change-Number: 33509 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/intel: Remove unused CPU_ADDR_BITS Kconfig option
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33169 Change subject: cpu/intel: Remove unused CPU_ADDR_BITS Kconfig option ...................................................................... cpu/intel: Remove unused CPU_ADDR_BITS Kconfig option Change-Id: Ib5529ceeec9481e05c56f20af0d201f3d20ea3f9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_106cx/Kconfig M src/lib/cbfs.c M src/mainboard/lenovo/x201/Kconfig M src/mainboard/packardbell/ms2290/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/skylake/Kconfig 6 files changed, 0 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/33169/1 diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index f365cf1..91b5189 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -14,10 +14,4 @@ select SERIALIZED_SMM_INITIALIZATION select CPU_INTEL_COMMON -if CPU_INTEL_MODEL_106CX - -config CPU_ADDR_BITS - int - default 32 - endif diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 91368fb..d4433df 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -273,7 +273,6 @@ memset(&load[fsize], 0, stage.memlen - fsize); prog_segment_loaded((uintptr_t)load, stage.memlen, SEG_FINAL); - out: prog_set_area(pstage, load, stage.memlen); prog_set_entry(pstage, entry, NULL); diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index 69e2038..ad22cc4 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -47,10 +47,6 @@ int default 4 -config CPU_ADDR_BITS - int - default 36 - # Without the Intel ME's EFFS partition some PCIe devices (like the USB and SATA # controllers) don't work as expected config ME_CLEANER_ARGS diff --git a/src/mainboard/packardbell/ms2290/Kconfig b/src/mainboard/packardbell/ms2290/Kconfig index c6a1e12..20b520d 100644 --- a/src/mainboard/packardbell/ms2290/Kconfig +++ b/src/mainboard/packardbell/ms2290/Kconfig @@ -49,8 +49,4 @@ int default 4 -config CPU_ADDR_BITS - int - default 36 - endif diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 217d1ea..91476c1 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -158,10 +158,6 @@ The amount of anticipated stack usage in CAR by bootblock and other stages. -config CPU_ADDR_BITS - int - default 39 - config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ int default 100 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index fcfe2b6..b67ddd7 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -116,10 +116,6 @@ hex default 0x200000 -config CPU_ADDR_BITS - int - default 36 - config DCACHE_RAM_BASE hex default 0xfef00000 -- To view, visit https://review.coreboot.org/c/coreboot/+/33169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5529ceeec9481e05c56f20af0d201f3d20ea3f9 Gerrit-Change-Number: 33169 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

4 5

Change in ...coreboot[master]: [WIP]Makefile.inc: Simplify generating the default fmap
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33275 Change subject: [WIP]Makefile.inc: Simplify generating the default fmap ...................................................................... [WIP]Makefile.inc: Simplify generating the default fmap Apparently you don't always need to specify base/size as fmap tool fills in the gaps, so make use of that to remove some ugly Makefile arithmetics. Change-Id: Ib138249140fc87307c3dc76692f343587117c7e0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.inc M util/cbfstool/default-x86.fmd 2 files changed, 7 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/33275/1 diff --git a/Makefile.inc b/Makefile.inc index d4f7597..13cb6ed 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -865,10 +865,9 @@ # X86 CONSOLE FMAP region # # position, size and entry line of CONSOLE relative to BIOS_BASE, if enabled -FMAP_CONSOLE_BASE := 0 ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) FMAP_CONSOLE_SIZE := $(CONFIG_CONSOLE_SPI_FLASH_BUFFER_SIZE) -FMAP_CONSOLE_ENTRY := CONSOLE@$(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE) +FMAP_CONSOLE_ENTRY := CONSOLE $(FMAP_CONSOLE_SIZE) else # ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y) FMAP_CONSOLE_SIZE := 0 FMAP_CONSOLE_ENTRY := @@ -879,12 +878,9 @@ # # position, size and entry line of MRC_CACHE relative to BIOS_BASE, if enabled ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) -FMAP_MRC_CACHE_BASE := $(call int-align, $(call int-add, $(FMAP_CONSOLE_BASE) \ - $(FMAP_CONSOLE_SIZE)), 0x10000) FMAP_MRC_CACHE_SIZE := $(CONFIG_MRC_SETTINGS_CACHE_SIZE) -FMAP_MRC_CACHE_ENTRY := RW_MRC_CACHE@$(FMAP_MRC_CACHE_BASE) $(FMAP_MRC_CACHE_SIZE) +FMAP_MRC_CACHE_ENTRY := RW_MRC_CACHE $(FMAP_MRC_CACHE_SIZE) else # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) -FMAP_MRC_CACHE_BASE := 0 FMAP_MRC_CACHE_SIZE := 0 FMAP_MRC_CACHE_ENTRY := endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) @@ -894,12 +890,9 @@ # # position, size and entry line of SMMSTORE relative to BIOS_BASE, if enabled ifeq ($(CONFIG_SMMSTORE),y) -FMAP_SMMSTORE_BASE := $(call int-align, $(call int-add, $(FMAP_CONSOLE_BASE) \ - $(FMAP_CONSOLE_SIZE) $(FMAP_MRC_CACHE_SIZE)), 0x10000) FMAP_SMMSTORE_SIZE := $(CONFIG_SMMSTORE_SIZE) -FMAP_SMMSTORE_ENTRY := SMMSTORE@$(FMAP_SMMSTORE_BASE) $(FMAP_SMMSTORE_SIZE) +FMAP_SMMSTORE_ENTRY := SMMSTORE $(FMAP_SMMSTORE_SIZE) else # ifeq ($(CONFIG_SMMSTORE),y) -FMAP_SMMSTORE_BASE := 0 FMAP_SMMSTORE_SIZE := 0 FMAP_SMMSTORE_ENTRY := endif # ifeq ($(CONFIG_CACHE_MRC_SETTINGS),y) @@ -909,16 +902,14 @@ # # # position, size -FMAP_FMAP_BASE := $(call int-add, $(FMAP_CONSOLE_BASE) $(FMAP_CONSOLE_SIZE) \ - $(FMAP_MRC_CACHE_SIZE) $(FMAP_SMMSTORE_SIZE)) FMAP_FMAP_SIZE := 0x200 # # X86 COREBOOT default cbfs FMAP region # # position and size of CBFS, relative to BIOS_BASE -FMAP_CBFS_BASE := $(call int-add, $(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE)) -FMAP_CBFS_SIZE := $(call int-subtract, $(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE)) +FMAP_CBFS_SIZE := $(shell echo $($(FMAP_BIOS_SIZE) - $(FMAP_FMAP_SIZE) \ + - $(FMAP_CONSOLE_SIZE) - $(FMAP_MRC_CACHE_SIZE) - $(FMAP_SMMSTORE_SIZE))) else # ifeq ($(CONFIG_ARCH_X86),y) DEFAULT_FLASHMAP:=$(top)/util/cbfstool/default.fmd # entire flash diff --git a/util/cbfstool/default-x86.fmd b/util/cbfstool/default-x86.fmd index f0143e9..1d1fec9 100644 --- a/util/cbfstool/default-x86.fmd +++ b/util/cbfstool/default-x86.fmd @@ -12,7 +12,7 @@ ##CONSOLE_ENTRY## ##MRC_CACHE_ENTRY## ##SMMSTORE_ENTRY## - FMAP@##FMAP_BASE## ##FMAP_SIZE## - COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## + FMAP ##FMAP_SIZE## + COREBOOT(CBFS) ##CBFS_SIZE## } } -- To view, visit https://review.coreboot.org/c/coreboot/+/33275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib138249140fc87307c3dc76692f343587117c7e0 Gerrit-Change-Number: 33275 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP]mb/lenovo/x220/vboot-rwa.fmd: Remove unneeded offsets/sizes
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33276 Change subject: [WIP]mb/lenovo/x220/vboot-rwa.fmd: Remove unneeded offsets/sizes ...................................................................... [WIP]mb/lenovo/x220/vboot-rwa.fmd: Remove unneeded offsets/sizes fmaptool can deal with it and it makes the file more readable. Not defining WR_RO and COREBOOT(CBFS) insures the bootblock is at the bottom of the flash. Change-Id: I4ed789acc8716942212fc5ab97fd722c8ea8c20d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/lenovo/x220/vboot-rwa.fmd 1 file changed, 17 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/33276/1 diff --git a/src/mainboard/lenovo/x220/vboot-rwa.fmd b/src/mainboard/lenovo/x220/vboot-rwa.fmd index 8a4cd3b..be06484 100644 --- a/src/mainboard/lenovo/x220/vboot-rwa.fmd +++ b/src/mainboard/lenovo/x220/vboot-rwa.fmd @@ -5,25 +5,25 @@ SI_ME@0x3000 0x4ed000 } SI_BIOS@0x500000 0x300000 { - RW_SECTION_A@0x00000 0x180000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x16ffc0 - RW_FWID_A@0x17ffc0 0x40 + RW_SECTION_A 0x180000 { + VBLOCK_A 0x10000 + FW_MAIN_A(CBFS) + RW_FWID_A 0x40 } - UNIFIED_MRC_CACHE@0x180000 0x20000 { - RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 } - RW_VPD(PRESERVE)@0x1a0000 0x1000 - SMMSTORE(PRESERVE)@0x1a1000 0x40000 + RW_VPD(PRESERVE) 0x1000 + SMMSTORE(PRESERVE) 0x40000 - WP_RO@0x1e1000 0x11f000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_PADDING@0x840 0x7c0 - RO_VPD(PRESERVE)@0x1000 0x1000 - GBB@0x2000 0x1e000 - COREBOOT(CBFS)@0x20000 0xff000 - } + WP_RO { + FMAP 0x800 + RO_FRID 0x40 + RO_PADDING 0x7c0 + RO_VPD(PRESERVE) 0x1000 + GBB 0x1e000 + COREBOOT(CBFS) + } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/33276 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4ed789acc8716942212fc5ab97fd722c8ea8c20d Gerrit-Change-Number: 33276 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP]Makefile.inc: Add Macro to generate cbfs int files
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33353 Change subject: [WIP]Makefile.inc: Add Macro to generate cbfs int files ...................................................................... [WIP]Makefile.inc: Add Macro to generate cbfs int files Add the makefile function 'add-cbfs-int' to generate cbfs files containing a little endian integer. Adding cbfs files containing a 64 bit is usually done with cbfstool add-int, but this requires the coreboot.rom image to be already build which clutters the Makefile. Instead add a method to cleanly generate the cbfsfile containing a 64bit little endian int which integrates better with the rest of the makefile. Change-Id: I443e74f823cd29b4c181975bdbca89839931b3a3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Makefile.inc M payloads/external/Makefile.inc 2 files changed, 26 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/33353/1 diff --git a/Makefile.inc b/Makefile.inc index d4f7597..d0f47e9 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -788,6 +788,20 @@ $(call cbfs-add-cmd-for-region,$(1),$(2)) endef +# add-cbfs-int (little endian) +# $(call add-cbfs-int, +# integer +# cbfs-file-name) +define add-cbfs-int + $(eval tmp_int:=$(shell mktemp -u int_file.XXXX)) + $(eval $(obj)/$(tmp_int): + echo -n -e $$$$(printf "%016x" $$$$(($(1))) \ + | sed -re "s/(..)(..)(..)(..)(..)(..)(..)(..)/\\\x\8\\\x\7\\\x\6\\\x\5\\\x\4\\\x\3\\\x\2\\\x\1/") > $$@) + cbfs-files-y += $(2) + $(2)-file := $(obj)/$(tmp_int) + $(2)-type := raw +endef + # list of files to add (using their file system names, not CBFS names), # for dependencies etc. prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) @@ -1064,18 +1078,6 @@ # file (filled with \377 = 0xff) and copy the CBFS image over it. dd if=/dev/zero bs=$(call _toint,$(CONFIG_ROM_SIZE)) count=1 2> /dev/null | tr '\000' '\377' > $@.tmp dd if=$(obj)/coreboot.pre of=$@.tmp bs=8192 conv=notrunc 2> /dev/null -ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) -ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) -ifneq ($(CONFIG_UPDATE_IMAGE),y) - @printf " SeaBIOS Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n" - $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_PS2_TIMEOUT) -n etc/ps2-keyboard-spinup -endif -endif -endif -ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y) - @printf " SeaBIOS Add sercon-port file\n" - $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port -endif ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) @printf " UPDATE-FIT\n" diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 9c34efa..24eeba6 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -110,6 +110,18 @@ bootorder-type := raw endif +# Add SeaBIOS PS2 timeout file +ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) +ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) +$(eval $(call add-cbfs-int,$(CONFIG_SEABIOS_PS2_TIMEOUT),etc/ps2-keyboard-spinup)) +endif +endif + +# Add SeaBIOS Sercon port file +ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y) +$(eval $(call add-cbfs-int,$(CONFIG_SEABIOS_SERCON_PORT_ADDR),etc/sercon-port)) +endif + # Depthcharge payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(DOTCONFIG) $(CBFSTOOL) -- To view, visit https://review.coreboot.org/c/coreboot/+/33353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I443e74f823cd29b4c181975bdbca89839931b3a3 Gerrit-Change-Number: 33353 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[4.8_branch]: mb/asus/m2v-mx_se: Allow use of native graphic init
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30474 Change subject: mb/asus/m2v-mx_se: Allow use of native graphic init ...................................................................... mb/asus/m2v-mx_se: Allow use of native graphic init Change-Id: Ib1faee6a71c276f4f9125e39e04aad660fa3ceb8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asus/m2v-mx_se/Kconfig M src/southbridge/via/k8t890/Kconfig M src/southbridge/via/k8t890/chrome.c 3 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/30474/1 diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig b/src/mainboard/asus/m2v-mx_se/Kconfig index 60ed865..856cbe5 100644 --- a/src/mainboard/asus/m2v-mx_se/Kconfig +++ b/src/mainboard/asus/m2v-mx_se/Kconfig @@ -30,6 +30,7 @@ select VGA select HAVE_ACPI_RESUME select SET_FIDVID + select MAINBOARD_HAS_NATIVE_VGA_INIT config MAINBOARD_DIR string diff --git a/src/southbridge/via/k8t890/Kconfig b/src/southbridge/via/k8t890/Kconfig index f6e51dc..ecbd1d3 100644 --- a/src/southbridge/via/k8t890/Kconfig +++ b/src/southbridge/via/k8t890/Kconfig @@ -23,6 +23,7 @@ depends on SOUTHBRIDGE_VIA_SUBTYPE_K8M890 select VGA select GFXUMA + select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT choice prompt "Framebuffer size" diff --git a/src/southbridge/via/k8t890/chrome.c b/src/southbridge/via/k8t890/chrome.c index 5b6d6d2..ec59715 100644 --- a/src/southbridge/via/k8t890/chrome.c +++ b/src/southbridge/via/k8t890/chrome.c @@ -135,7 +135,7 @@ //k8m890_host_fb_direct_set(fb_address); - if (IS_ENABLED(SOUTHBRIDGE_VIA_K8M890_VGA_EN)) { + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { /* Now set up the VGA console */ vga_io_init(); /* Enable full IO access */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.8_branch Gerrit-Change-Id: Ib1faee6a71c276f4f9125e39e04aad660fa3ceb8 Gerrit-Change-Number: 30474 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/block/cpu: Add a MP init choice selection
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33361 Change subject: soc/intel/block/cpu: Add a MP init choice selection ...................................................................... soc/intel/block/cpu: Add a MP init choice selection Add a choice to select the MP init method for clarity. Change-Id: I2a7490948f729f1ae9fd2537bf6cbe9ada51f968 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/Kconfig 1 file changed, 21 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/33361/1 diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 8cc572d..6082ce3 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -51,18 +51,34 @@ ENHANCED NEM guarantees that modified data is always kept in cache while clean data is replaced. -config USE_INTEL_FSP_MP_INIT +choice + prompt "Multiple Processor (MP) Initialization Options" + default MP_USE_COREBOOT_NATIVE_MP_INIT if !PLATFORM_USES_FSP2_1 + default MP_USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI if PLATFORM_USES_FSP2_1 + +config MP_USE_COREBOOT_NATIVE_MP_INIT + bool "Perform MP Initialization by coreboot" + +config MP_USE_INTEL_FSP_MP_INIT bool "Perform MP Initialization by FSP" - default n + select USE_INTEL_FSP_MP_INIT + +config MP_USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI + bool "Perform MP Initialization by FSP using coreboot MP PPI service" + depends on FSP_USES_MP_SERVICES_PPI + select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI + +endchoice + +config USE_INTEL_FSP_MP_INIT + bool depends on !USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI help This option allows FSP to perform multiprocessor initialization. config USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI - bool "Perform MP Initialization by FSP using coreboot MP PPI service" + bool depends on FSP_USES_MP_SERVICES_PPI - default y if PLATFORM_USES_FSP2_1 - default n help This option allows FSP to make use of MP services PPI published by coreboot to perform multiprocessor initialization. -- To view, visit https://review.coreboot.org/c/coreboot/+/33361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a7490948f729f1ae9fd2537bf6cbe9ada51f968 Gerrit-Change-Number: 33361 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/cbfstool/fit.c: Bail out when there are not enough FIT entries
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33555 Change subject: util/cbfstool/fit.c: Bail out when there are not enough FIT entries ...................................................................... util/cbfstool/fit.c: Bail out when there are not enough FIT entries Bail out when there are not enough empty FIT enties to add all microcode entries. Change-Id: If86678a1eaaa0c5ff571f25bd6bfdb26ac93a946 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/cbfstool/fit.c 1 file changed, 8 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/33555/1 diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c index aeb1755..2fee9e3 100644 --- a/util/cbfstool/fit.c +++ b/util/cbfstool/fit.c @@ -238,7 +238,7 @@ static int parse_microcode_blob(struct cbfs_image *image, struct cbfs_file *mcode_file, struct microcode_entry *mcus, - int total_entries, int *mcus_found) + int *mcus_found) { int num_mcus; uint32_t current_offset; @@ -272,9 +272,6 @@ file_length -= mcus[num_mcus].size; num_mcus++; - /* Reached limit of FIT entries. */ - if (num_mcus == total_entries) - break; if (file_length < sizeof(struct microcode_header)) break; } @@ -319,13 +316,18 @@ return 1; } - if (parse_microcode_blob(image, mcode_file, mcus, empty_entries, - &mcus_found)) { + if (parse_microcode_blob(image, mcode_file, mcus, &mcus_found)) { ERROR("Couldn't parse microcode blob.\n"); ret = 1; goto out; } + if (mcus_found > empty_entries) { + ERROR("Not enough empty FIT entries for all microcode update entries.\n"); + ret = 1; + goto out; + } + add_microcodde_entries(fit, image, mcus_found, mcus, offset_fn, 0); update_fit_checksum(fit); -- To view, visit https://review.coreboot.org/c/coreboot/+/33555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If86678a1eaaa0c5ff571f25bd6bfdb26ac93a946 Gerrit-Change-Number: 33555 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/apple: Add MacBook Pro 8,1 support
by Evgeny Zinoviev (Code Review) 18 Apr '22

18 Apr '22

Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33151 Change subject: mb/apple: Add MacBook Pro 8,1 support ...................................................................... mb/apple: Add MacBook Pro 8,1 support MacBook Pro 13'' Early 2011 (A1278). Works: - Graphics initialization (libgfxinit) - GRUB payload - Linux (it boots) Mostly untested for now. This board has SOIC-8 chip, 25Q064A in my case. WARNING: do not just use a clip to flash the chip as usual. There is a capacitor and a resistor right near the VCC pin. They prevent the clip from being properly attached. You can very easily break them. Either cut off some plasic from the clip so that it doesn't touch them, or don't use clip at all. Change-Id: I7a7dc6d6c16751403ce276d2778dc915cd69f3f2 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io> --- A src/mainboard/apple/macbookpro8_1/Kconfig A src/mainboard/apple/macbookpro8_1/Kconfig.name A src/mainboard/apple/macbookpro8_1/Makefile.inc A src/mainboard/apple/macbookpro8_1/acpi/ec.asl A src/mainboard/apple/macbookpro8_1/acpi/platform.asl A src/mainboard/apple/macbookpro8_1/acpi/superio.asl A src/mainboard/apple/macbookpro8_1/acpi_tables.c A src/mainboard/apple/macbookpro8_1/board_info.txt A src/mainboard/apple/macbookpro8_1/cmos.default A src/mainboard/apple/macbookpro8_1/cmos.layout A src/mainboard/apple/macbookpro8_1/devicetree.cb A src/mainboard/apple/macbookpro8_1/dsdt.asl A src/mainboard/apple/macbookpro8_1/gpio.c A src/mainboard/apple/macbookpro8_1/hda_verb.c A src/mainboard/apple/macbookpro8_1/mainboard.c A src/mainboard/apple/macbookpro8_1/romstage.c 16 files changed, 816 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/33151/1 diff --git a/src/mainboard/apple/macbookpro8_1/Kconfig b/src/mainboard/apple/macbookpro8_1/Kconfig new file mode 100644 index 0000000..c838bea --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/Kconfig @@ -0,0 +1,43 @@ +if BOARD_APPLE_MACBOOKPRO8_1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select EC_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_INT15 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_BD82X6X + select SYSTEM_TYPE_LAPTOP + select USE_NATIVE_RAMINIT + select MAINBOARD_HAS_LIBGFXINIT + select GFX_GMA_INTERNAL_IS_LVDS + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + +config MAINBOARD_DIR + string + default apple/macbookpro8_1 + +config MAINBOARD_PART_NUMBER + string + default "MacBookPro8,1" + +config VGA_BIOS_FILE + string + default "pci8086,0126.rom" + +config VGA_BIOS_ID + string + default "8086,0126" + +config DRAM_RESET_GATE_GPIO + int + default 28 + +config MAX_CPUS + int + default 8 +endif diff --git a/src/mainboard/apple/macbookpro8_1/Kconfig.name b/src/mainboard/apple/macbookpro8_1/Kconfig.name new file mode 100644 index 0000000..06a7de5 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_APPLE_MACBOOKPRO8_1 + bool "MacBookPro8,1" diff --git a/src/mainboard/apple/macbookpro8_1/Makefile.inc b/src/mainboard/apple/macbookpro8_1/Makefile.inc new file mode 100644 index 0000000..ebe01ae --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/Makefile.inc @@ -0,0 +1,2 @@ +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/apple/macbookpro8_1/acpi/ec.asl b/src/mainboard/apple/macbookpro8_1/acpi/ec.asl new file mode 100644 index 0000000..cd74865 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/acpi/ec.asl @@ -0,0 +1,18 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <ec/apple/acpi/ec.asl> +#include <ec/apple/acpi/ac_60.asl> +#include <ec/apple/acpi/lid_60.asl> diff --git a/src/mainboard/apple/macbookpro8_1/acpi/platform.asl b/src/mainboard/apple/macbookpro8_1/acpi/platform.asl new file mode 100644 index 0000000..3603581 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/acpi/platform.asl @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ +} diff --git a/src/mainboard/apple/macbookpro8_1/acpi/superio.asl b/src/mainboard/apple/macbookpro8_1/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/acpi/superio.asl diff --git a/src/mainboard/apple/macbookpro8_1/acpi_tables.c b/src/mainboard/apple/macbookpro8_1/acpi_tables.c new file mode 100644 index 0000000..6b731cc --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/acpi_tables.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +/* FIXME: check this function. */ +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + // the lid is open by default. + gnvs->lids = 1; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/apple/macbookpro8_1/board_info.txt b/src/mainboard/apple/macbookpro8_1/board_info.txt new file mode 100644 index 0000000..8e0e321 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +ROM protocol: SPI +Flashrom support: n +ROM package: SOIC-8 +ROM socketed: n +Release year: 2011 diff --git a/src/mainboard/apple/macbookpro8_1/cmos.default b/src/mainboard/apple/macbookpro8_1/cmos.default new file mode 100644 index 0000000..53e85a3 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/cmos.default @@ -0,0 +1 @@ +debug_level=Debug diff --git a/src/mainboard/apple/macbookpro8_1/cmos.layout b/src/mainboard/apple/macbookpro8_1/cmos.layout new file mode 100644 index 0000000..aa9f563 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/cmos.layout @@ -0,0 +1,114 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +#400 8 r 0 reserved for century byte + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: EC +#411 1 e 8 first_battery +#412 1 e 1 bluetooth +#413 1 e 1 wwan +#414 1 e 1 touchpad +#415 1 e 1 wlan +#416 1 e 1 trackpoint +#417 1 e 1 fn_ctrl_swap +#418 1 e 1 sticky_fn +#419 2 e 13 usb_always_on +#421 1 e 9 sata_mode +#422 2 e 10 backlight + +# coreboot config options: cpu +#424 8 r 0 unused + +# coreboot config options: northbridge +#432 5 e 11 gfx_uma_size +#437 3 r 0 unused +#440 8 h 0 volume + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep + +# ----------------------------------------------------------------- +checksums + +checksum 392 447 984 diff --git a/src/mainboard/apple/macbookpro8_1/devicetree.cb b/src/mainboard/apple/macbookpro8_1/devicetree.cb new file mode 100644 index 0000000..db21a62 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/devicetree.cb @@ -0,0 +1,113 @@ +chip northbridge/intel/sandybridge # FIXME: check gfx.ndid and gfx.did + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.ndid" = "3" + register "gfx.use_spread_spectrum_clock" = "1" + register "gpu_cpu_backlight" = "0x00001312" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "gpu_panel_port_select" = "0" + register "gpu_panel_power_backlight_off_delay" = "2000" + register "gpu_panel_power_backlight_on_delay" = "2000" + register "gpu_panel_power_cycle_delay" = "5" + register "gpu_panel_power_down_delay" = "500" + register "gpu_panel_power_up_delay" = "600" + register "gpu_pch_backlight" = "0x13121312" + + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on + end + device lapic 0xacac off + end + end + end + + register "pci_mmio_size" = "2048" + + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x001c0301" + register "gen4_dec" = "0x00fc0701" + register "gpi7_routing" = "2" + register "p_cnt_throttling_supported" = "1" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x3" + register "spi_lvscc" = "0x0" + register "spi_uvscc" = "0x2005" + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x8086 0x7270 + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on # USB2 EHCI #2 Unsupported PCI device 8086:1c2c + subsystemid 0x8086 0x7270 + end + device pci 1b.0 on # High Definition Audio Audio controller + subsystemid 0x8086 0x7270 + end + device pci 1c.0 on # PCIe Port #1 + subsystemid 0x8086 0x7270 + end + device pci 1c.1 on # PCIe Port #2 + subsystemid 0x8086 0x7270 + end + device pci 1c.2 on # PCIe Port #3 + subsystemid 0x8086 0x7270 + end + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 off end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on # USB2 EHCI #1 Unsupported PCI device 8086:1c27 + subsystemid 0x8086 0x7270 + end + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge PCI-LPC bridge + subsystemid 0x8086 0x7270 + end + device pci 1f.2 on # SATA Controller 1 + subsystemid 0x8086 0x7270 + end + device pci 1f.3 on # SMBus + subsystemid 0x8086 0x7270 + end + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + device pci 00.0 on # Host bridge Host bridge + subsystemid 0x106b 0x00db + end + device pci 01.0 off # PCIe Bridge for discrete graphics + subsystemid 0x106b 0x00db + end + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x106b 0x00db + end + device pci 01.1 on + subsystemid 0x106b 0x00db + end + device pci 1a.7 on + subsystemid 0x8086 0x7270 + end + device pci 1d.7 on + subsystemid 0x8086 0x7270 + end + end +end diff --git a/src/mainboard/apple/macbookpro8_1/dsdt.asl b/src/mainboard/apple/macbookpro8_1/dsdt.asl new file mode 100644 index 0000000..455ac17 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/dsdt.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/apple/macbookpro8_1/gpio.c b/src/mainboard/apple/macbookpro8_1/gpio.c new file mode 100644 index 0000000..d3555ef --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/gpio.c @@ -0,0 +1,231 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_GPIO, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_GPIO, + .gpio12 = GPIO_MODE_GPIO, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_GPIO, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_GPIO, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_GPIO, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_INPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_INPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_INPUT, + .gpio16 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_OUTPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_INPUT, + .gpio29 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio16 = GPIO_LEVEL_LOW, + .gpio21 = GPIO_LEVEL_LOW, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio1 = GPIO_INVERT, + .gpio4 = GPIO_INVERT, + .gpio5 = GPIO_INVERT, + .gpio7 = GPIO_INVERT, + .gpio9 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_GPIO, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_GPIO, + .gpio44 = GPIO_MODE_GPIO, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_GPIO, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_GPIO, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_OUTPUT, + .gpio35 = GPIO_DIR_INPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_OUTPUT, + .gpio38 = GPIO_DIR_OUTPUT, + .gpio39 = GPIO_DIR_OUTPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_INPUT, + .gpio42 = GPIO_DIR_INPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio33 = GPIO_LEVEL_LOW, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_LOW, + .gpio39 = GPIO_LEVEL_LOW, + .gpio45 = GPIO_LEVEL_LOW, + .gpio48 = GPIO_LEVEL_HIGH, + .gpio49 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_GPIO, + .gpio65 = GPIO_MODE_GPIO, + .gpio66 = GPIO_MODE_GPIO, + .gpio67 = GPIO_MODE_GPIO, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_GPIO, + .gpio71 = GPIO_MODE_GPIO, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_INPUT, + .gpio65 = GPIO_DIR_INPUT, + .gpio66 = GPIO_DIR_INPUT, + .gpio67 = GPIO_DIR_INPUT, + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio70 = GPIO_DIR_INPUT, + .gpio71 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/apple/macbookpro8_1/hda_verb.c b/src/mainboard/apple/macbookpro8_1/hda_verb.c new file mode 100644 index 0000000..d6cb85e --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/hda_verb.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10134206, /* Codec Vendor / Device ID: Cirrus */ + 0x106b1c00, /* Subsystem ID */ + + 0x0000000b, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x106b1c00), + + /* NID 0x09. */ + AZALIA_PIN_CFG(0x0, 0x09, 0x012b4030), + + /* NID 0x0a. */ + AZALIA_PIN_CFG(0x0, 0x0a, 0x90100121), + + /* NID 0x0b. */ + AZALIA_PIN_CFG(0x0, 0x0b, 0x90100120), + + /* NID 0x0c. */ + AZALIA_PIN_CFG(0x0, 0x0c, 0x400000f0), + + /* NID 0x0d. */ + AZALIA_PIN_CFG(0x0, 0x0d, 0x90a00110), + + /* NID 0x0e. */ + AZALIA_PIN_CFG(0x0, 0x0e, 0x400000f0), + + /* NID 0x0f. */ + AZALIA_PIN_CFG(0x0, 0x0f, 0x400000f0), + + /* NID 0x10. */ + AZALIA_PIN_CFG(0x0, 0x10, 0x004be040), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x400000f0), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x400000f0), + 0x80862805, /* Codec Vendor / Device ID: Intel */ + 0x80860101, /* Subsystem ID */ + + 0x00000004, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x3, 0x80860101), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560010), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560010), + + /* NID 0x07. */ + AZALIA_PIN_CFG(0x3, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/apple/macbookpro8_1/mainboard.c b/src/mainboard/apple/macbookpro8_1/mainboard.c new file mode 100644 index 0000000..fe63303 --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/mainboard.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <ec/acpi/ec.h> +#include <console/console.h> + +static void mainboard_init(struct device *dev) +{ + RCBA32(0x38c8) = 0x00002005; + RCBA32(0x38c4) = 0x00800000; +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/apple/macbookpro8_1/romstage.c b/src/mainboard/apple/macbookpro8_1/romstage.c new file mode 100644 index 0000000..4dffacb --- /dev/null +++ b/src/mainboard/apple/macbookpro8_1/romstage.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2019 Evgeny Zinoviev <me(a)ch1p.io> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <arch/byteorder.h> +#include <device/pci_ops.h> +#include <device/pnp_ops.h> +#include <console/console.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> + +void pch_enable_lpc(void) +{ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0681); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x001c0301); + pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00fc0701); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, + { 1, 0, -1 }, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33151 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a7dc6d6c16751403ce276d2778dc915cd69f3f2 Gerrit-Change-Number: 33151 Gerrit-PatchSet: 1 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-MessageType: newchange

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coreboot-gerrit July 2019