coreboot-gerrit July 2019

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Change in ...coreboot[4.8_branch]: mb/asus/m2v-mx_se: Allow use of native graphic init
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30474 Change subject: mb/asus/m2v-mx_se: Allow use of native graphic init ...................................................................... mb/asus/m2v-mx_se: Allow use of native graphic init Change-Id: Ib1faee6a71c276f4f9125e39e04aad660fa3ceb8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asus/m2v-mx_se/Kconfig M src/southbridge/via/k8t890/Kconfig M src/southbridge/via/k8t890/chrome.c 3 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/30474/1 diff --git a/src/mainboard/asus/m2v-mx_se/Kconfig b/src/mainboard/asus/m2v-mx_se/Kconfig index 60ed865..856cbe5 100644 --- a/src/mainboard/asus/m2v-mx_se/Kconfig +++ b/src/mainboard/asus/m2v-mx_se/Kconfig @@ -30,6 +30,7 @@ select VGA select HAVE_ACPI_RESUME select SET_FIDVID + select MAINBOARD_HAS_NATIVE_VGA_INIT config MAINBOARD_DIR string diff --git a/src/southbridge/via/k8t890/Kconfig b/src/southbridge/via/k8t890/Kconfig index f6e51dc..ecbd1d3 100644 --- a/src/southbridge/via/k8t890/Kconfig +++ b/src/southbridge/via/k8t890/Kconfig @@ -23,6 +23,7 @@ depends on SOUTHBRIDGE_VIA_SUBTYPE_K8M890 select VGA select GFXUMA + select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT choice prompt "Framebuffer size" diff --git a/src/southbridge/via/k8t890/chrome.c b/src/southbridge/via/k8t890/chrome.c index 5b6d6d2..ec59715 100644 --- a/src/southbridge/via/k8t890/chrome.c +++ b/src/southbridge/via/k8t890/chrome.c @@ -135,7 +135,7 @@ //k8m890_host_fb_direct_set(fb_address); - if (IS_ENABLED(SOUTHBRIDGE_VIA_K8M890_VGA_EN)) { + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { /* Now set up the VGA console */ vga_io_init(); /* Enable full IO access */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30474 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.8_branch Gerrit-Change-Id: Ib1faee6a71c276f4f9125e39e04aad660fa3ceb8 Gerrit-Change-Number: 30474 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/block/cpu: Add a MP init choice selection
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33361 Change subject: soc/intel/block/cpu: Add a MP init choice selection ...................................................................... soc/intel/block/cpu: Add a MP init choice selection Add a choice to select the MP init method for clarity. Change-Id: I2a7490948f729f1ae9fd2537bf6cbe9ada51f968 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/common/block/cpu/Kconfig 1 file changed, 21 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/33361/1 diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig index 8cc572d..6082ce3 100644 --- a/src/soc/intel/common/block/cpu/Kconfig +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -51,18 +51,34 @@ ENHANCED NEM guarantees that modified data is always kept in cache while clean data is replaced. -config USE_INTEL_FSP_MP_INIT +choice + prompt "Multiple Processor (MP) Initialization Options" + default MP_USE_COREBOOT_NATIVE_MP_INIT if !PLATFORM_USES_FSP2_1 + default MP_USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI if PLATFORM_USES_FSP2_1 + +config MP_USE_COREBOOT_NATIVE_MP_INIT + bool "Perform MP Initialization by coreboot" + +config MP_USE_INTEL_FSP_MP_INIT bool "Perform MP Initialization by FSP" - default n + select USE_INTEL_FSP_MP_INIT + +config MP_USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI + bool "Perform MP Initialization by FSP using coreboot MP PPI service" + depends on FSP_USES_MP_SERVICES_PPI + select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI + +endchoice + +config USE_INTEL_FSP_MP_INIT + bool depends on !USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI help This option allows FSP to perform multiprocessor initialization. config USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI - bool "Perform MP Initialization by FSP using coreboot MP PPI service" + bool depends on FSP_USES_MP_SERVICES_PPI - default y if PLATFORM_USES_FSP2_1 - default n help This option allows FSP to make use of MP services PPI published by coreboot to perform multiprocessor initialization. -- To view, visit https://review.coreboot.org/c/coreboot/+/33361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a7490948f729f1ae9fd2537bf6cbe9ada51f968 Gerrit-Change-Number: 33361 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/cbfstool/fit.c: Bail out when there are not enough FIT entries
by Arthur Heymans (Code Review) 21 Apr '22

21 Apr '22

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33555 Change subject: util/cbfstool/fit.c: Bail out when there are not enough FIT entries ...................................................................... util/cbfstool/fit.c: Bail out when there are not enough FIT entries Bail out when there are not enough empty FIT enties to add all microcode entries. Change-Id: If86678a1eaaa0c5ff571f25bd6bfdb26ac93a946 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/cbfstool/fit.c 1 file changed, 8 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/33555/1 diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c index aeb1755..2fee9e3 100644 --- a/util/cbfstool/fit.c +++ b/util/cbfstool/fit.c @@ -238,7 +238,7 @@ static int parse_microcode_blob(struct cbfs_image *image, struct cbfs_file *mcode_file, struct microcode_entry *mcus, - int total_entries, int *mcus_found) + int *mcus_found) { int num_mcus; uint32_t current_offset; @@ -272,9 +272,6 @@ file_length -= mcus[num_mcus].size; num_mcus++; - /* Reached limit of FIT entries. */ - if (num_mcus == total_entries) - break; if (file_length < sizeof(struct microcode_header)) break; } @@ -319,13 +316,18 @@ return 1; } - if (parse_microcode_blob(image, mcode_file, mcus, empty_entries, - &mcus_found)) { + if (parse_microcode_blob(image, mcode_file, mcus, &mcus_found)) { ERROR("Couldn't parse microcode blob.\n"); ret = 1; goto out; } + if (mcus_found > empty_entries) { + ERROR("Not enough empty FIT entries for all microcode update entries.\n"); + ret = 1; + goto out; + } + add_microcodde_entries(fit, image, mcus_found, mcus, offset_fn, 0); update_fit_checksum(fit); -- To view, visit https://review.coreboot.org/c/coreboot/+/33555 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If86678a1eaaa0c5ff571f25bd6bfdb26ac93a946 Gerrit-Change-Number: 33555 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: WIP: mediatek/me8183: Refactor dsi driver as common code
by jitao shi (Code Review) 31 Mar '22

31 Mar '22

jitao shi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34562 ) Change subject: WIP: mediatek/me8183: Refactor dsi driver as common code ...................................................................... WIP: mediatek/me8183: Refactor dsi driver as common code BUG=b:80501386,b:117254947 BRANCH=none TEST=build pass Change-Id: I242d7a4f75057c0a955c9284a79c385a667ce7bd --- A src/soc/mediatek/common/dsi.c M src/soc/mediatek/mt8173/Makefile.inc M src/soc/mediatek/mt8173/dsi.c M src/soc/mediatek/mt8173/include/soc/dsi.h M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/dsi.c M src/soc/mediatek/mt8183/include/soc/dsi.h 7 files changed, 604 insertions(+), 1,050 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/34562/1 diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c new file mode 100644 index 0000000..cf6d228 --- /dev/null +++ b/src/soc/mediatek/common/dsi.c @@ -0,0 +1,226 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/mmio.h> +#include <console/console.h> +#include <delay.h> +#include <soc/addressmap.h> +#include <soc/dsi.h> +#include <timer.h> + +void dsi_write32(void *a, uint32_t v) +{ + write32(a, v); +} + +void dsi_clrsetbits_le32(void *a, uint32_t m, uint32_t v) +{ + clrsetbits_le32(a, m, v); +} + +void dsi_clrbits_le32(void *a, uint32_t m) +{ + clrbits_le32(a, m); +} + +void dsi_setbits_le32(void *a, uint32_t m) +{ + setbits_le32(a, m); +} + +void mtk_dsi_reset(u32 dsi_id) +{ + struct dsi_regs *const dsi0 = getdsi_regbase(dsi_id); + + dsi_write32(&dsi0->dsi_con_ctrl, 1); + dsi_write32(&dsi0->dsi_con_ctrl, 0); +} + +void mtk_dsi_clk_hs_mode_enable(u32 dsi_id) +{ + struct dsi_regs *const dsi0 = getdsi_regbase(dsi_id); + + dsi_setbits_le32(&dsi0->dsi_phy_lccon, 1); +} + +void mtk_dsi_set_mode(u32 dsi_id, u32 mode_flags) +{ + u32 tmp_reg1 = 0; + struct dsi_regs *const dsi0 = getdsi_regbase(dsi_id); + + if (mode_flags & MIPI_DSI_MODE_VIDEO) { + tmp_reg1 = SYNC_PULSE_MODE; + + if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) + tmp_reg1 = BURST_MODE; + + if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) + tmp_reg1 = SYNC_PULSE_MODE; + } + + dsi_write32(&dsi0->dsi_mode_ctrl, tmp_reg1); +} + +void mtk_dsi_rxtx_control(u32 dsi_id, u32 mode_flags, u32 lanes) +{ + u32 tmp_reg = 0; + struct dsi_regs *const dsi0 = getdsi_regbase(dsi_id); + + switch (lanes) { + case 1: + tmp_reg = 1 << 2; + break; + case 2: + tmp_reg = 3 << 2; + break; + case 3: + tmp_reg = 7 << 2; + break; + case 4: + default: + tmp_reg = 0xf << 2; + break; + } + + tmp_reg |= (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6; + tmp_reg |= (mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3; + + dsi_write32(&dsi0->dsi_txrx_ctrl, tmp_reg); +} + +void mtk_dsi_start(u32 dsi_id) +{ + struct dsi_regs *const dsi0 = getdsi_regbase(dsi_id); + + dsi_clrbits_le32(&dsi0->dsi_start, 1); + dsi_setbits_le32(&dsi0->dsi_start, 1); +} + +static void mtk_dsi_cmdq(u8 *data, u8 len, u32 type) +{ + struct stopwatch sw; + u8 *tx_buf = data; + u8 cmdq_size; + u32 reg_val, cmdq_mask, i, config, cmdq_off, intsta_0; + struct dsi_regs *const dsi0 = getdsi_regbase(0); + + while (read32(&dsi0->dsi_intsta) & (1 << 31)) { + printk(BIOS_ERR, "%s wait dsi no busy\n", __func__); + mdelay(20); + } + + dsi_write32(&dsi0->dsi_intsta, 0); + + if (MTK_DSI_HOST_IS_READ(type)) + config = BTA; + else + config = (len > 2) ? LONG_PACKET : SHORT_PACKET; + + if (len > 2) { + cmdq_size = 1 + (len + 3) / 4; + cmdq_off = 4; + cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1; + reg_val = (len << 16) | (type << 8) | config; + } else { + cmdq_size = 1; + cmdq_off = 2; + cmdq_mask = CONFIG | DATA_ID; + reg_val = (type << 8) | config; + } + + for (i = 0; i < 0x20; i = i + 4) + dsi_write32((void *)DSI_BASE + 0x200 + i, 0); + + for (i = 0; i < len; i++) { + dsi_clrsetbits_le32((void *)DSI_BASE + 0x200 + + ((cmdq_off + i) & (0xfffffffc)), + (0xff << (((i + cmdq_off) & 3) * 8)), + tx_buf[i] << (((i + cmdq_off) & 3) * 8)); + } + + dsi_clrsetbits_le32(&dsi0->dsi_cmdq0, cmdq_mask, reg_val); + dsi_clrsetbits_le32(&dsi0->dsi_cmdq_size, CMDQ_SIZE, cmdq_size); + mtk_dsi_start(0); + + stopwatch_init_usecs_expire(&sw, 400); + do { + intsta_0 = read32(&dsi0->dsi_intsta); + if (intsta_0 & CMD_DONE_INT_FLAG) + break; + udelay(4); + } while (!stopwatch_expired(&sw)); + + if (!(intsta_0 & CMD_DONE_INT_FLAG)) + printk(BIOS_ERR, "dsi send cmd time-out(400uS)\n"); +} + +void push_table(struct lcm_init_table *init_cmd) +{ + u32 cmd, i; + u32 type; + + for (i = 0; ; i++) { + cmd = init_cmd[i].cmd; + + switch (cmd) { + case DELAY_CMD: + mdelay(init_cmd[i].len); + break; + + case END_OF_TABLE: + return; + + case INIT_DCS_CMD: + switch (init_cmd[i].len) { + case 0: + return; + + case 1: + type = MIPI_DSI_DCS_SHORT_WRITE; + break; + + case 2: + type = MIPI_DSI_DCS_SHORT_WRITE_PARAM; + break; + + default: + type = MIPI_DSI_DCS_LONG_WRITE; + break; + } + mtk_dsi_cmdq(init_cmd[i].data, init_cmd[i].len, type); + break; + + case INIT_GENENIC_CMD: + default: + switch (init_cmd[i].len) { + case 0: + type = MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM; + break; + case 1: + type = MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM; + break; + case 2: + type = MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM; + break; + default: + type = MIPI_DSI_GENERIC_LONG_WRITE; + break; + } + mtk_dsi_cmdq(init_cmd[i].data, init_cmd[i].len, type); + break; + } + } +} + diff --git a/src/soc/mediatek/mt8173/Makefile.inc b/src/soc/mediatek/mt8173/Makefile.inc index 0ffa196..7e43138 100644 --- a/src/soc/mediatek/mt8173/Makefile.inc +++ b/src/soc/mediatek/mt8173/Makefile.inc @@ -82,7 +82,7 @@ ramstage-y += ../common/usb.c usb.c ramstage-y += ddp.c -ramstage-y += dsi.c +ramstage-y += ../common/dsi.c dsi.c ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += bl31_plat_params.c diff --git a/src/soc/mediatek/mt8173/dsi.c b/src/soc/mediatek/mt8173/dsi.c index b2279ea..23be800 100644 --- a/src/soc/mediatek/mt8173/dsi.c +++ b/src/soc/mediatek/mt8173/dsi.c @@ -25,71 +25,7 @@ static bool dual_dsi_mode; -static void mipi_write32(void *a, uint32_t v) -{ - void *a1 = a + (MIPI_TX1_BASE - MIPI_TX0_BASE); - write32(a, v); - if (dual_dsi_mode) - write32(a1, v); -} - -static void mipi_clrsetbits_le32(void *a, uint32_t m, uint32_t v) -{ - void *a1 = a + (MIPI_TX1_BASE - MIPI_TX0_BASE); - clrsetbits_le32(a, m, v); - if (dual_dsi_mode) - clrsetbits_le32(a1, m, v); -} - -static void mipi_clrbits_le32(void *a, uint32_t m) -{ - void *a1 = a + (MIPI_TX1_BASE - MIPI_TX0_BASE); - clrbits_le32(a, m); - if (dual_dsi_mode) - clrbits_le32(a1, m); -} - -static void mipi_setbits_le32(void *a, uint32_t m) -{ - void *a1 = a + (MIPI_TX1_BASE - MIPI_TX0_BASE); - setbits_le32(a, m); - if (dual_dsi_mode) - setbits_le32(a1, m); -} - -static void dsi_write32(void *a, uint32_t v) -{ - void *a1 = a + (DSI1_BASE - DSI0_BASE); - write32(a, v); - if (dual_dsi_mode) - write32(a1, v); -} - -static void dsi_clrsetbits_le32(void *a, uint32_t m, uint32_t v) -{ - void *a1 = a + (DSI1_BASE - DSI0_BASE); - clrsetbits_le32(a, m, v); - if (dual_dsi_mode) - clrsetbits_le32(a1, m, v); -} - -static void dsi_clrbits_le32(void *a, uint32_t m) -{ - void *a1 = a + (DSI1_BASE - DSI0_BASE); - clrbits_le32(a, m); - if (dual_dsi_mode) - clrbits_le32(a1, m); -} - -static void dsi_setbits_le32(void *a, uint32_t m) -{ - void *a1 = a + (DSI1_BASE - DSI0_BASE); - setbits_le32(a, m); - if (dual_dsi_mode) - setbits_le32(a1, m); -} - -static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes, +static int mtk_dsi_phy_clk_setting(u32 dsi_id, u32 format, u32 lanes, const struct edid *edid) { u32 txdiv0, txdiv1; @@ -97,6 +33,7 @@ u32 reg; u32 bit_per_pixel; int i, data_rate, mipi_tx_rate; + struct mipi_tx_regs *const mipi_tx0 = getmipitx_regbase(dsi_id); reg = read32(&mipi_tx0->dsi_bg_con); @@ -111,16 +48,16 @@ mipi_write32(&mipi_tx0->dsi_bg_con, reg); udelay(30); - mipi_clrsetbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_LNT_IMP_CAL_CODE, + dsi_clrsetbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_LNT_IMP_CAL_CODE, 8 << 4 | RG_DSI_LNT_HS_BIAS_EN); - mipi_setbits_le32(&mipi_tx0->dsi_con, + dsi_setbits_le32(&mipi_tx0->dsi_con, RG_DSI0_CKG_LDOOUT_EN | RG_DSI0_LDOCORE_EN); - mipi_clrsetbits_le32(&mipi_tx0->dsi_pll_pwr, RG_DSI_MPPLL_SDM_ISO_EN, + dsi_clrsetbits_le32(&mipi_tx0->dsi_pll_pwr, RG_DSI_MPPLL_SDM_ISO_EN, RG_DSI_MPPLL_SDM_PWR_ON); - mipi_clrbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); + dsi_clrbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); switch (format) { case MIPI_DSI_FMT_RGB565: @@ -171,7 +108,7 @@ return -1; } - mipi_clrsetbits_le32(&mipi_tx0->dsi_pll_con0, + dsi_clrsetbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_TXDIV1 | RG_DSI0_MPPLL_TXDIV0 | RG_DSI0_MPPLL_PREDIV, txdiv1 << 5 | txdiv0 << 3); @@ -185,29 +122,47 @@ */ pcw = (u64)(data_rate * (1 << txdiv0) * (1 << txdiv1)) << 24; pcw /= 13; - mipi_write32(&mipi_tx0->dsi_pll_con2, pcw); + dsi_write32(&mipi_tx0->dsi_pll_con2, pcw); - mipi_setbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_FRA_EN); + dsi_setbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_FRA_EN); - mipi_setbits_le32(&mipi_tx0->dsi_clock_lane, LDOOUT_EN); + dsi_setbits_le32(&mipi_tx0->dsi_clock_lane, LDOOUT_EN); for (i = 0; i < lanes; i++) - mipi_setbits_le32(&mipi_tx0->dsi_data_lane[i], LDOOUT_EN); + dsi_setbits_le32(&mipi_tx0->dsi_data_lane[i], LDOOUT_EN); - mipi_setbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); + dsi_setbits_le32(&mipi_tx0->dsi_pll_con0, RG_DSI0_MPPLL_PLL_EN); udelay(40); - mipi_clrbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_SSC_EN); - mipi_clrbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_PAD_TIE_LOW_EN); + dsi_clrbits_le32(&mipi_tx0->dsi_pll_con1, RG_DSI0_MPPLL_SDM_SSC_EN); + dsi_clrbits_le32(&mipi_tx0->dsi_top_con, RG_DSI_PAD_TIE_LOW_EN); return mipi_tx_rate; } -static void mtk_dsi_phy_timconfig(u32 data_rate) +static void mtk_dsi_phy_timconfig(u32 dsi_id, u32 format, u32 lanes, const struct edid *edid) { u32 timcon0, timcon1, timcon2, timcon3; u32 cycle_time, ui, lpx; + struct dsi_regs *const dsi0 = getdsi_regbase(dsi_id); + + switch (format) { + case MIPI_DSI_FMT_RGB565: + bit_per_pixel = 16; + break; + case MIPI_DSI_FMT_RGB666: + case MIPI_DSI_FMT_RGB666_PACKED: + bit_per_pixel = 18; + break; + case MIPI_DSI_FMT_RGB888: + default: + bit_per_pixel = 24; + break; + } + + data_rate = edid->mode.pixel_clock * 102 * bit_per_pixel / + (lanes * 1000 * 100); ui = 1000 / data_rate + 0x01; cycle_time = 8000 / data_rate + 0x01; @@ -228,67 +183,13 @@ dsi_write32(&dsi0->dsi_phy_timecon3, timcon3); } -static void mtk_dsi_reset(void) +static void mtk_dsi_config_timing(u32 dsi_id, u32 mode_flags, u32 format, u32 lanes, const struct edid *edid) { - dsi_setbits_le32(&dsi0->dsi_con_ctrl, 3); - dsi_clrbits_le32(&dsi0->dsi_con_ctrl, 1); + mtk_dsi_phy_timconfig(dsi_id, format, lanes, edid); + mtk_dsi_config_vdo_timing(dsi_id, mode_flags, format, edid); } -static void mtk_dsi_clk_hs_mode_enable(void) -{ - dsi_setbits_le32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN); -} - -static void mtk_dsi_clk_hs_mode_disable(void) -{ - dsi_clrbits_le32(&dsi0->dsi_phy_lccon, LC_HS_TX_EN); -} - -static void mtk_dsi_set_mode(u32 mode_flags) -{ - u32 tmp_reg1 = 0; - - if (mode_flags & MIPI_DSI_MODE_VIDEO) { - tmp_reg1 = SYNC_PULSE_MODE; - - if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) - tmp_reg1 = BURST_MODE; - - if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) - tmp_reg1 = SYNC_PULSE_MODE; - } - - dsi_write32(&dsi0->dsi_mode_ctrl, tmp_reg1); -} - -static void mtk_dsi_rxtx_control(u32 mode_flags, u32 lanes) -{ - u32 tmp_reg = 0; - - switch (lanes) { - case 1: - tmp_reg = 1 << 2; - break; - case 2: - tmp_reg = 3 << 2; - break; - case 3: - tmp_reg = 7 << 2; - break; - case 4: - default: - tmp_reg = 0xf << 2; - break; - } - - tmp_reg |= (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6; - tmp_reg |= (mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3; - - dsi_write32(&dsi0->dsi_txrx_ctrl, tmp_reg); -} - -static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, - const struct edid *edid) +static void mtk_dsi_config_vdo_timing(u32 dsi_id, u32 mode_flags, u32 format, const struct edid *edid) { u32 hsync_active_byte; u32 hbp_byte; @@ -298,6 +199,7 @@ u32 bpp; u32 packet_fmt; u32 hactive; + struct dsi_regs *const dsi0 = getdsi_regbase(dsi_id); if (format == MIPI_DSI_FMT_RGB565) bpp = 2; @@ -353,18 +255,12 @@ dsi_write32(&dsi0->dsi_psctrl, packet_fmt); } -static void mtk_dsi_start(void) -{ - dsi_write32(&dsi0->dsi_start, 0); - /* Only start master DSI */ - write32(&dsi0->dsi_start, 1); -} - static void mtk_dsi_tx_cmd_type0(u8 cmd) { struct stopwatch sw; u32 cmdq0; u32 intsta_0, intsta_1; + struct dsi_regs *const dsi0 = getdsi_regbase(0); cmdq0 = (MIPI_DSI_DCS_SHORT_WRITE << 8) | SHORT_PACKET | (cmd << 16); @@ -406,10 +302,9 @@ return -1; mtk_dsi_reset(); - mtk_dsi_phy_timconfig(data_rate); - mtk_dsi_rxtx_control(mode_flags, lanes); - mtk_dsi_clk_hs_mode_disable(); - mtk_dsi_config_vdo_timing(mode_flags, format, edid); + mtk_dsi_config_timing(0, mode_flags, format, lanes, edid); + mtk_dsi_rxtx_control(0, mode_flags, lanes); + mtk_dsi_set_mode(mode_flags); mtk_dsi_clk_hs_mode_enable(); @@ -455,3 +350,11 @@ mipi_clrbits_le32(&lvds_tx1->vopll_ctl3, RG_DA_LVDS_ISO_EN); } + +void *const getmipitx_regbase(u32 dsi_id){ + return dsi_id ? (void *)MIPI_TX1_BASE : (void *)MIPI_TX0_BASE; +} + +void *const getdsi_regbase(u32 dsi_id){ + return dsi_id ? (void *)DSI1_BASE : (void *)DSI0_BASE; +} \ No newline at end of file diff --git a/src/soc/mediatek/mt8173/include/soc/dsi.h b/src/soc/mediatek/mt8173/include/soc/dsi.h index ca35bd1..9b4f5db 100644 --- a/src/soc/mediatek/mt8173/include/soc/dsi.h +++ b/src/soc/mediatek/mt8173/include/soc/dsi.h @@ -17,431 +17,12 @@ #define _DSI_REG_H_ #include <edid.h> +#include <soc/dsi_common.h> #include <types.h> -enum mipi_dsi_pixel_format { - MIPI_DSI_FMT_RGB888, - MIPI_DSI_FMT_RGB666, - MIPI_DSI_FMT_RGB666_PACKED, - MIPI_DSI_FMT_RGB565 -}; - -/* video mode */ -enum { - MIPI_DSI_MODE_VIDEO = BIT(0), - /* video burst mode */ - MIPI_DSI_MODE_VIDEO_BURST = BIT(1), - /* video pulse mode */ - MIPI_DSI_MODE_VIDEO_SYNC_PULSE = BIT(2), - /* enable auto vertical count mode */ - MIPI_DSI_MODE_VIDEO_AUTO_VERT = BIT(3), - /* enable hsync-end packets in vsync-pulse and v-porch area */ - MIPI_DSI_MODE_VIDEO_HSE = BIT(4), - /* disable hfront-porch area */ - MIPI_DSI_MODE_VIDEO_HFP = BIT(5), - /* disable hback-porch area */ - MIPI_DSI_MODE_VIDEO_HBP = BIT(6), - /* disable hsync-active area */ - MIPI_DSI_MODE_VIDEO_HSA = BIT(7), - /* flush display FIFO on vsync pulse */ - MIPI_DSI_MODE_VSYNC_FLUSH = BIT(8), - /* disable EoT packets in HS mode */ - MIPI_DSI_MODE_EOT_PACKET = BIT(9), - /* device supports non-continuous clock behavior (DSI spec 5.6.1) */ - MIPI_DSI_CLOCK_NON_CONTINUOUS = BIT(10), - /* transmit data in low power */ - MIPI_DSI_MODE_LPM = BIT(11) -}; - -struct dsi_regs { - u32 dsi_start; - u8 reserved0[4]; - u32 dsi_inten; - u32 dsi_intsta; - u32 dsi_con_ctrl; - u32 dsi_mode_ctrl; - u32 dsi_txrx_ctrl; - u32 dsi_psctrl; - u32 dsi_vsa_nl; - u32 dsi_vbp_nl; - u32 dsi_vfp_nl; - u32 dsi_vact_nl; - u8 reserved1[32]; - u32 dsi_hsa_wc; - u32 dsi_hbp_wc; - u32 dsi_hfp_wc; - u32 dsi_bllp_wc; - u32 dsi_cmdq_size; - u32 dsi_hstx_cklp_wc; - u8 reserved2[156]; - u32 dsi_phy_lccon; - u32 dsi_phy_ld0con; - u8 reserved3[4]; - u32 dsi_phy_timecon0; - u32 dsi_phy_timecon1; - u32 dsi_phy_timecon2; - u32 dsi_phy_timecon3; - u8 reserved4[16]; - u32 dsi_vm_cmd_con; - u8 reserved5[204]; - u32 dsi_cmdq0; -}; - -check_member(dsi_regs, dsi_phy_lccon, 0x104); -check_member(dsi_regs, dsi_phy_timecon3, 0x11c); -check_member(dsi_regs, dsi_vm_cmd_con, 0x130); -check_member(dsi_regs, dsi_cmdq0, 0x200); -static struct dsi_regs *const dsi0 = (void *)DSI0_BASE; -static struct dsi_regs *const dsi1 = (void *)DSI1_BASE; - -/* DSI_INTSTA */ -enum { - LPRX_RD_RDY_INT_FLAG = BIT(0), - CMD_DONE_INT_FLAG = BIT(1), - TE_RDY_INT_FLAG = BIT(2), - VM_DONE_INT_FLAG = BIT(3), - EXT_TE_RDY_INT_FLAG = BIT(4), - DSI_BUSY = BIT(31), -}; - -/* DSI_CON_CTRL */ -enum { - DSI_RESET = BIT(0), - DSI_EN = BIT(1), - DSI_DUAL = BIT(4), -}; - -/* DSI_MODE_CTRL */ -enum { - MODE = 3, - CMD_MODE = 0, - SYNC_PULSE_MODE = 1, - SYNC_EVENT_MODE = 2, - BURST_MODE = 3, - FRM_MODE = BIT(16), - MIX_MODE = BIT(17) -}; - -/* DSI_PSCTRL */ -enum { - DSI_PS_WC = 0x3fff, - DSI_PS_SEL = (3 << 16), - PACKED_PS_16BIT_RGB565 = (0 << 16), - LOOSELY_PS_18BIT_RGB666 = (1 << 16), - PACKED_PS_18BIT_RGB666 = (2 << 16), - PACKED_PS_24BIT_RGB888 = (3 << 16) -}; - -/* DSI_CMDQ_SIZE */ -enum { - CMDQ_SIZE = 0x3f, -}; - -/* DSI_PHY_LCCON */ -enum { - LC_HS_TX_EN = BIT(0), - LC_ULPM_EN = BIT(1), - LC_WAKEUP_EN = BIT(2) -}; - -/*DSI_PHY_LD0CON */ -enum { - LD0_RM_TRIG_EN = BIT(0), - LD0_ULPM_EN = BIT(1), - LD0_WAKEUP_EN = BIT(2) -}; - -enum { - LPX = (0xff << 0), - HS_PRPR = (0xff << 8), - HS_ZERO = (0xff << 16), - HS_TRAIL = (0xff << 24) -}; - -enum { - TA_GO = (0xff << 0), - TA_SURE = (0xff << 8), - TA_GET = (0xff << 16), - DA_HS_EXIT = (0xff << 24) -}; - -enum { - CONT_DET = (0xff << 0), - CLK_ZERO = (0xf << 16), - CLK_TRAIL = (0xff << 24) -}; - -enum { - CLK_HS_PRPR = (0xff << 0), - CLK_HS_POST = (0xff << 8), - CLK_HS_EXIT = (0xf << 16) -}; - -/* DSI_VM_CMD_CON */ -enum { - VM_CMD_EN = BIT(0), - TS_VFP_EN = BIT(5), -}; - -/* DSI_CMDQ0 */ -enum { - CONFIG = (0xff << 0), - SHORT_PACKET = 0, - LONG_PACKET = 2, - BTA = BIT(2), - DATA_ID = (0xff << 8), - DATA_0 = (0xff << 16), - DATA_1 = (0xff << 24), -}; - -/* MIPITX_REG */ -struct mipi_tx_regs { - u32 dsi_con; - u32 dsi_clock_lane; - u32 dsi_data_lane[4]; - u8 reserved0[40]; - u32 dsi_top_con; - u32 dsi_bg_con; - u8 reserved1[8]; - u32 dsi_pll_con0; - u32 dsi_pll_con1; - u32 dsi_pll_con2; - u32 dsi_pll_con3; - u32 dsi_pll_chg; - u32 dsi_pll_top; - u32 dsi_pll_pwr; - u8 reserved2[4]; - u32 dsi_rgs; - u32 dsi_gpi_en; - u32 dsi_gpi_pull; - u32 dsi_phy_sel; - u32 dsi_sw_ctrl_en; - u32 dsi_sw_ctrl_con0; - u32 dsi_sw_ctrl_con1; - u32 dsi_sw_ctrl_con2; - u32 dsi_dbg_con; - u32 dsi_dbg_out; - u32 dsi_apb_async_sta; -}; - -check_member(mipi_tx_regs, dsi_top_con, 0x40); -check_member(mipi_tx_regs, dsi_pll_pwr, 0x68); - -static struct mipi_tx_regs *const mipi_tx0 = (void *)MIPI_TX0_BASE; -static struct mipi_tx_regs *const mipi_tx1 = (void *)MIPI_TX0_BASE; - -/* MIPITX_DSI0_CON */ -enum { - RG_DSI0_LDOCORE_EN = BIT(0), - RG_DSI0_CKG_LDOOUT_EN = BIT(1), - RG_DSI0_BCLK_SEL = (3 << 2), - RG_DSI0_LD_IDX_SEL = (7 << 4), - RG_DSI0_PHYCLK_SEL = (2 << 8), - RG_DSI0_DSICLK_FREQ_SEL = BIT(10), - RG_DSI0_LPTX_CLMP_EN = BIT(11) -}; - -/* MIPITX_DSI0_CLOCK_LANE */ -enum { - LDOOUT_EN = BIT(0), - CKLANE_EN = BIT(1), - IPLUS1 = BIT(2), - LPTX_IPLUS2 = BIT(3), - LPTX_IMINUS = BIT(4), - LPCD_IPLUS = BIT(5), - LPCD_IMLUS = BIT(6), - RT_CODE = (0xf << 8) -}; - -/* MIPITX_DSI_TOP_CON */ -enum { - RG_DSI_LNT_INTR_EN = BIT(0), - RG_DSI_LNT_HS_BIAS_EN = BIT(1), - RG_DSI_LNT_IMP_CAL_EN = BIT(2), - RG_DSI_LNT_TESTMODE_EN = BIT(3), - RG_DSI_LNT_IMP_CAL_CODE = (0xf << 4), - RG_DSI_LNT_AIO_SEL = (7 << 8), - RG_DSI_PAD_TIE_LOW_EN = BIT(11), - RG_DSI_DEBUG_INPUT_EN = BIT(12), - RG_DSI_PRESERVE = (7 << 13) -}; - -/* MIPITX_DSI_BG_CON */ -enum { - RG_DSI_BG_CORE_EN = BIT(0), - RG_DSI_BG_CKEN = BIT(1), - RG_DSI_BG_DIV = (0x3 << 2), - RG_DSI_BG_FAST_CHARGE = BIT(4), - RG_DSI_V12_SEL = (7 << 5), - RG_DSI_V10_SEL = (7 << 8), - RG_DSI_V072_SEL = (7 << 11), - RG_DSI_V04_SEL = (7 << 14), - RG_DSI_V032_SEL = (7 << 17), - RG_DSI_V02_SEL = (7 << 20), - rsv_23 = BIT(23), - RG_DSI_BG_R1_TRIM = (0xf << 24), - RG_DSI_BG_R2_TRIM = (0xf << 28) -}; - -/* MIPITX_DSI_PLL_CON0 */ -enum { - RG_DSI0_MPPLL_PLL_EN = BIT(0), - RG_DSI0_MPPLL_PREDIV = (3 << 1), - RG_DSI0_MPPLL_TXDIV0 = (3 << 3), - RG_DSI0_MPPLL_TXDIV1 = (3 << 5), - RG_DSI0_MPPLL_POSDIV = (7 << 7), - RG_DSI0_MPPLL_MONVC_EN = BIT(10), - RG_DSI0_MPPLL_MONREF_EN = BIT(11), - RG_DSI0_MPPLL_VOD_EN = BIT(12) -}; - -/* MIPITX_DSI_PLL_CON1 */ -enum { - RG_DSI0_MPPLL_SDM_FRA_EN = BIT(0), - RG_DSI0_MPPLL_SDM_SSC_PH_INIT = BIT(1), - RG_DSI0_MPPLL_SDM_SSC_EN = BIT(2), - RG_DSI0_MPPLL_SDM_SSC_PRD = (0xffff << 16) -}; - -/* MIPITX_DSI_PLL_PWR */ -enum { - RG_DSI_MPPLL_SDM_PWR_ON = BIT(0), - RG_DSI_MPPLL_SDM_ISO_EN = BIT(1), - RG_DSI_MPPLL_SDM_PWR_ACK = BIT(8) -}; - -/* LVDS_TX1_REG */ -struct lvds_tx1_regs { - u32 lvdstx1_ctl1; - u32 lvdstx1_ctl2; - u32 lvdstx1_ctl3; - u32 lvdstx1_ctl4; - u32 lvdstx1_ctl5; - u32 vopll_ctl1; - u32 vopll_ctl2; - u32 vopll_ctl3; -}; - static struct lvds_tx1_regs *const lvds_tx1 = (void *)(MIPI_TX0_BASE + 0x800); static struct lvds_tx1_regs *const lvds_tx2 = (void *)(MIPI_TX1_BASE + 0x800); -/* LVDS_VOPLL_CTRL3 */ -enum { - RG_LVDSTX_21EDG = BIT(0), - RG_LVDSTX_21LEV = BIT(1), - RG_LVDSTX_51EDG = BIT(2), - RG_LVDSTX_51LEV = BIT(3), - RG_AD_LVDSTX_PWR_ACK = BIT(4), - RG_DA_LVDS_ISO_EN = BIT(8), - RG_DA_LVDSTX_PWR_ON = BIT(9) -}; - -/* MIPI DSI Processor-to-Peripheral transaction types */ -enum { - MIPI_DSI_V_SYNC_START = 0x01, - MIPI_DSI_V_SYNC_END = 0x11, - MIPI_DSI_H_SYNC_START = 0x21, - MIPI_DSI_H_SYNC_END = 0x31, - - MIPI_DSI_COLOR_MODE_OFF = 0x02, - MIPI_DSI_COLOR_MODE_ON = 0x12, - MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22, - MIPI_DSI_TURN_ON_PERIPHERAL = 0x32, - - MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03, - MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13, - MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23, - - MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04, - MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14, - MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24, - - MIPI_DSI_DCS_SHORT_WRITE = 0x05, - MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15, - - MIPI_DSI_DCS_READ = 0x06, - - MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37, - - MIPI_DSI_END_OF_TRANSMISSION = 0x08, - - MIPI_DSI_NULL_PACKET = 0x09, - MIPI_DSI_BLANKING_PACKET = 0x19, - MIPI_DSI_GENERIC_LONG_WRITE = 0x29, - MIPI_DSI_DCS_LONG_WRITE = 0x39, - - MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c, - MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c, - MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c, - - MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d, - MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d, - MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d, - - MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e, - MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e, - MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e, - MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e, -}; - -/* MIPI DSI Peripheral-to-Processor transaction types */ -enum { - MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT = 0x02, - MIPI_DSI_RX_END_OF_TRANSMISSION = 0x08, - MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE = 0x11, - MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE = 0x12, - MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE = 0x1a, - MIPI_DSI_RX_DCS_LONG_READ_RESPONSE = 0x1c, - MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE = 0x21, - MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE = 0x22, -}; - -/* MIPI DCS commands */ -enum { - MIPI_DCS_NOP = 0x00, - MIPI_DCS_SOFT_RESET = 0x01, - MIPI_DCS_GET_DISPLAY_ID = 0x04, - MIPI_DCS_GET_RED_CHANNEL = 0x06, - MIPI_DCS_GET_GREEN_CHANNEL = 0x07, - MIPI_DCS_GET_BLUE_CHANNEL = 0x08, - MIPI_DCS_GET_DISPLAY_STATUS = 0x09, - MIPI_DCS_GET_POWER_MODE = 0x0A, - MIPI_DCS_GET_ADDRESS_MODE = 0x0B, - MIPI_DCS_GET_PIXEL_FORMAT = 0x0C, - MIPI_DCS_GET_DISPLAY_MODE = 0x0D, - MIPI_DCS_GET_SIGNAL_MODE = 0x0E, - MIPI_DCS_GET_DIAGNOSTIC_RESULT = 0x0F, - MIPI_DCS_ENTER_SLEEP_MODE = 0x10, - MIPI_DCS_EXIT_SLEEP_MODE = 0x11, - MIPI_DCS_ENTER_PARTIAL_MODE = 0x12, - MIPI_DCS_ENTER_NORMAL_MODE = 0x13, - MIPI_DCS_EXIT_INVERT_MODE = 0x20, - MIPI_DCS_ENTER_INVERT_MODE = 0x21, - MIPI_DCS_SET_GAMMA_CURVE = 0x26, - MIPI_DCS_SET_DISPLAY_OFF = 0x28, - MIPI_DCS_SET_DISPLAY_ON = 0x29, - MIPI_DCS_SET_COLUMN_ADDRESS = 0x2A, - MIPI_DCS_SET_PAGE_ADDRESS = 0x2B, - MIPI_DCS_WRITE_MEMORY_START = 0x2C, - MIPI_DCS_WRITE_LUT = 0x2D, - MIPI_DCS_READ_MEMORY_START = 0x2E, - MIPI_DCS_SET_PARTIAL_AREA = 0x30, - MIPI_DCS_SET_SCROLL_AREA = 0x33, - MIPI_DCS_SET_TEAR_OFF = 0x34, - MIPI_DCS_SET_TEAR_ON = 0x35, - MIPI_DCS_SET_ADDRESS_MODE = 0x36, - MIPI_DCS_SET_SCROLL_START = 0x37, - MIPI_DCS_EXIT_IDLE_MODE = 0x38, - MIPI_DCS_ENTER_IDLE_MODE = 0x39, - MIPI_DCS_SET_PIXEL_FORMAT = 0x3A, - MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C, - MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E, - MIPI_DCS_SET_TEAR_SCANLINE = 0x44, - MIPI_DCS_GET_SCANLINE = 0x45, - MIPI_DCS_READ_DDB_START = 0xA1, - MIPI_DCS_READ_DDB_CONTINUE = 0xA8, -}; - int mtk_dsi_init(u32 mode_flags, enum mipi_dsi_pixel_format format, u32 lanes, bool dual_dsi_mode, const struct edid *edid); void mtk_dsi_pin_drv_ctrl(void); diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 15ad154..355c889 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -43,7 +43,7 @@ ramstage-y += auxadc.c ramstage-y += ../common/cbmem.c emi.c ramstage-y += ddp.c -ramstage-y += dsi.c +ramstage-y += ../common/dsi.c dsi.c ramstage-y += ../common/gpio.c gpio.c ramstage-y += ../common/mmu_operations.c mmu_operations.c ramstage-y += ../common/mtcmos.c mtcmos.c diff --git a/src/soc/mediatek/mt8183/dsi.c b/src/soc/mediatek/mt8183/dsi.c index 30057c7..383f79e 100644 --- a/src/soc/mediatek/mt8183/dsi.c +++ b/src/soc/mediatek/mt8183/dsi.c @@ -1,481 +1,310 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 MediaTek Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/mmio.h> -#include <console/console.h> -#include <delay.h> -#include <soc/addressmap.h> -#include <soc/dsi.h> -#include <timer.h> - -static void dsi_write32(void *a, uint32_t v) -{ - write32(a, v); -} - -static void dsi_clrsetbits_le32(void *a, uint32_t m, uint32_t v) -{ - clrsetbits_le32(a, m, v); -} - -static void dsi_clrbits_le32(void *a, uint32_t m) -{ - clrbits_le32(a, m); -} - -static void dsi_setbits_le32(void *a, uint32_t m) -{ - setbits_le32(a, m); -} - -static int mtk_dsi_phy_clk_setting(u32 format, u32 lanes, - const struct edid *edid) -{ - unsigned int txdiv, txdiv0, txdiv1; - u64 pcw; - int data_rate; - u32 bpp; - - switch (format) { - case MIPI_DSI_FMT_RGB565: - bpp = 16; - break; - case MIPI_DSI_FMT_RGB666: - case MIPI_DSI_FMT_RGB666_PACKED: - bpp = 18; - break; - case MIPI_DSI_FMT_RGB888: - default: - bpp = 24; - break; - } - - data_rate = (u64)(edid->mode.pixel_clock * 1000 * bpp) / lanes; - - printk(BIOS_INFO, "data_rate: %u bps\n", data_rate); - - if (data_rate >= 2000000000) { - txdiv = 1; - txdiv0 = 0; - txdiv1 = 0; - } else if (data_rate >= 1000000000) { - txdiv = 2; - txdiv0 = 1; - txdiv1 = 0; - } else if (data_rate >= 500000000) { - txdiv = 4; - txdiv0 = 2; - txdiv1 = 0; - } else if (data_rate > 250000000) { - txdiv = 8; - txdiv0 = 3; - txdiv1 = 0; - } else if (data_rate >= 125000000) { - txdiv = 16; - txdiv0 = 4; - txdiv1 = 0; - } else { - printk(BIOS_ERR, "data rate (%u) must be >=50. Please check " - "pixel clock (%u), bpp (%u), number of lanes (%u)\n", - data_rate, edid->mode.pixel_clock, bpp, - lanes); - return -1; - } - - dsi_clrbits_le32(mipi_tx + MIPITX_PLL_CON4, BIT(11) | BIT(10)); - - dsi_setbits_le32(mipi_tx + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON); - udelay(30); - dsi_clrbits_le32(mipi_tx + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN); - - pcw = (u64)((data_rate / 1000000) * (1 << txdiv0) * (1 << txdiv1)); - pcw <<= 24; - pcw /= 26; - - dsi_write32(mipi_tx + MIPITX_PLL_CON0, pcw); - dsi_clrsetbits_le32(mipi_tx + MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV, - txdiv0 << 8); - udelay(30); - dsi_setbits_le32(mipi_tx + MIPITX_PLL_CON1, RG_DSI_PLL_EN); - - /* BG_LPF_EN / BG_CORE_EN */ - dsi_write32(mipi_tx + MIPITX_LANE_CON, 0x3FFF0180); - udelay(40); - dsi_write32(mipi_tx + MIPITX_LANE_CON, 0x3FFF00c0); - - /* Switch OFF each Lane */ - dsi_clrbits_le32(mipi_tx + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN); - dsi_clrbits_le32(mipi_tx + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN); - dsi_clrbits_le32(mipi_tx + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN); - dsi_clrbits_le32(mipi_tx + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN); - dsi_clrbits_le32(mipi_tx + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN); - - dsi_setbits_le32(mipi_tx + MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN); - - return data_rate; -} - -static void mtk_dsi_phy_timconfig(u32 data_rate, - struct mtk_phy_timing *phy_timing) -{ - u32 timcon0, timcon1, timcon2, timcon3; - - timcon0 = phy_timing->lpx | phy_timing->da_hs_prepare << 8 | - phy_timing->da_hs_zero << 16 | phy_timing->da_hs_trail << 24; - timcon1 = phy_timing->ta_go | phy_timing->ta_sure << 8 | - phy_timing->ta_get << 16 | phy_timing->da_hs_exit << 24; - timcon2 = 1 << 8 | phy_timing->clk_hs_zero << 16 | - phy_timing->clk_hs_trail << 24; - timcon3 = phy_timing->clk_hs_prepare | phy_timing->clk_hs_post << 8 | - phy_timing->clk_hs_exit << 16; - - dsi_write32(&dsi->dsi_phy_timecon0, timcon0); - dsi_write32(&dsi->dsi_phy_timecon1, timcon1); - dsi_write32(&dsi->dsi_phy_timecon2, timcon2); - dsi_write32(&dsi->dsi_phy_timecon3, timcon3); -} - -static void mtk_dsi_reset(void) -{ - dsi_write32(&dsi->dsi_con_ctrl, 1); - dsi_write32(&dsi->dsi_con_ctrl, 0); -} - -static void mtk_dsi_clk_hs_mode_enable(void) -{ - dsi_setbits_le32(&dsi->dsi_phy_lccon, 1); -} - -static void mtk_dsi_set_mode(u32 mode_flags) -{ - u32 tmp_reg1 = 0; - - if (mode_flags & MIPI_DSI_MODE_VIDEO) { - tmp_reg1 = SYNC_PULSE_MODE; - - if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) - tmp_reg1 = BURST_MODE; - - if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) - tmp_reg1 = SYNC_PULSE_MODE; - } - - dsi_write32(&dsi->dsi_mode_ctrl, tmp_reg1); -} - -static void mtk_dsi_phy_timing_calc(u32 format, u32 lanes, - const struct edid *edid, - struct mtk_phy_timing *phy_timing) -{ - u32 ui, cycle_time, data_rate; - u32 bit_per_pixel; - - switch (format) { - case MIPI_DSI_FMT_RGB565: - bit_per_pixel = 16; - break; - case MIPI_DSI_FMT_RGB666: - case MIPI_DSI_FMT_RGB666_PACKED: - bit_per_pixel = 18; - break; - case MIPI_DSI_FMT_RGB888: - default: - bit_per_pixel = 24; - break; - } - - data_rate = edid->mode.pixel_clock * bit_per_pixel / lanes; - - ui = 1000 / (data_rate / 1000) + 1U; - cycle_time = 8000 / (data_rate / 1000) + 1U; - - phy_timing->lpx = DIV_ROUND_UP(60, cycle_time); - phy_timing->da_hs_prepare = DIV_ROUND_UP((40 + 5 * ui), cycle_time); - phy_timing->da_hs_zero = DIV_ROUND_UP((110 + 6 * ui), cycle_time); - phy_timing->da_hs_trail = DIV_ROUND_UP(((4 * ui) + 80), cycle_time); - - phy_timing->ta_go = 4U * phy_timing->lpx; - phy_timing->ta_sure = 3U * phy_timing->lpx / 2U; - phy_timing->ta_get = 5U * phy_timing->lpx; - phy_timing->da_hs_exit = 2U * phy_timing->lpx; - - phy_timing->clk_hs_zero = DIV_ROUND_UP(0x150U, cycle_time); - phy_timing->clk_hs_trail = DIV_ROUND_UP(0x64U, cycle_time) + 0xaU; - - phy_timing->clk_hs_prepare = DIV_ROUND_UP(0x40U, cycle_time); - phy_timing->clk_hs_post = DIV_ROUND_UP(80U + 52U * ui, cycle_time); - phy_timing->clk_hs_exit = 2U * phy_timing->lpx; -} - -static void mtk_dsi_rxtx_control(u32 mode_flags, u32 lanes) -{ - u32 tmp_reg = 0; - - switch (lanes) { - case 1: - tmp_reg = 1 << 2; - break; - case 2: - tmp_reg = 3 << 2; - break; - case 3: - tmp_reg = 7 << 2; - break; - case 4: - default: - tmp_reg = 0xf << 2; - break; - } - - tmp_reg |= (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6; - tmp_reg |= (mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3; - - dsi_write32(&dsi->dsi_txrx_ctrl, tmp_reg); -} - -static void mtk_dsi_config_vdo_timing(u32 mode_flags, u32 format, - const struct edid *edid, - struct mtk_phy_timing *phy_timing, - u32 lanes) -{ - u32 hsync_active_byte; - u32 hbp_byte; - u32 hfp_byte, tmp_hfp_byte; - u32 vbp_byte; - u32 vfp_byte; - u32 bpp; - u32 packet_fmt; - u32 hactive; - u32 data_phy_cycles; - - if (format == MIPI_DSI_FMT_RGB565) - bpp = 2; - else - bpp = 3; - - vbp_byte = edid->mode.vbl - edid->mode.vso - edid->mode.vspw - - edid->mode.vborder; - vfp_byte = edid->mode.vso - edid->mode.vborder; - - dsi_write32(&dsi->dsi_vsa_nl, edid->mode.vspw); - dsi_write32(&dsi->dsi_vbp_nl, vbp_byte); - dsi_write32(&dsi->dsi_vfp_nl, vfp_byte); - dsi_write32(&dsi->dsi_vact_nl, edid->mode.va); - - if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) - hbp_byte = (edid->mode.hbl - edid->mode.hso - edid->mode.hspw - - edid->mode.hborder) * bpp - 10; - else - hbp_byte = (edid->mode.hbl - edid->mode.hso - - edid->mode.hborder) * bpp - 10; - - hsync_active_byte = edid->mode.hspw * bpp - 10; - - data_phy_cycles = phy_timing->lpx + phy_timing->da_hs_prepare + - phy_timing->da_hs_zero + phy_timing->da_hs_exit + 2; - - tmp_hfp_byte = (edid->mode.hso - edid->mode.hborder) * bpp; - - if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { - if (tmp_hfp_byte > data_phy_cycles * lanes + 18) { - hfp_byte = tmp_hfp_byte - data_phy_cycles * lanes - 18; - } else { - printk(BIOS_ERR, "HFP less than d-phy, FPS will under 60Hz\n"); - hfp_byte = tmp_hfp_byte; - } - } else { - if (tmp_hfp_byte > data_phy_cycles * lanes + 12) { - hfp_byte = tmp_hfp_byte - data_phy_cycles * lanes - 12; - } else { - printk(BIOS_ERR, "HFP less than d-phy, FPS will under 60Hz\n"); - hfp_byte = tmp_hfp_byte; - } - } - - dsi_write32(&dsi->dsi_hsa_wc, hsync_active_byte); - dsi_write32(&dsi->dsi_hbp_wc, hbp_byte); - dsi_write32(&dsi->dsi_hfp_wc, hfp_byte); - - switch (format) { - case MIPI_DSI_FMT_RGB888: - packet_fmt = PACKED_PS_24BIT_RGB888; - break; - case MIPI_DSI_FMT_RGB666: - packet_fmt = LOOSELY_PS_18BIT_RGB666; - break; - case MIPI_DSI_FMT_RGB666_PACKED: - packet_fmt = PACKED_PS_18BIT_RGB666; - break; - case MIPI_DSI_FMT_RGB565: - packet_fmt = PACKED_PS_16BIT_RGB565; - break; - default: - packet_fmt = PACKED_PS_24BIT_RGB888; - break; - } - - hactive = edid->mode.ha; - packet_fmt |= (hactive * bpp) & DSI_PS_WC; - - dsi_write32(&dsi->dsi_psctrl, 0x2c << 24 | packet_fmt); - dsi_write32(&dsi->dsi_size_con, edid->mode.va << 16 | hactive); -} - -static void mtk_dsi_start(void) -{ - dsi_clrbits_le32(&dsi->dsi_start, 1); - dsi_setbits_le32(&dsi->dsi_start, 1); -} - -static void mtk_dsi_cmdq(u8 *data, u8 len, u32 type) -{ - struct stopwatch sw; - u8 *tx_buf = data; - u8 cmdq_size; - u32 reg_val, cmdq_mask, i, config, cmdq_off, intsta_0; - - while (read32(&dsi->dsi_intsta) & (1 << 31)) { - printk(BIOS_ERR, "%s wait dsi no busy\n", __func__); - mdelay(20); - } - - dsi_write32(&dsi->dsi_intsta, 0); - - if (MTK_DSI_HOST_IS_READ(type)) - config = BTA; - else - config = (len > 2) ? LONG_PACKET : SHORT_PACKET; - - if (len > 2) { - cmdq_size = 1 + (len + 3) / 4; - cmdq_off = 4; - cmdq_mask = CONFIG | DATA_ID | DATA_0 | DATA_1; - reg_val = (len << 16) | (type << 8) | config; - } else { - cmdq_size = 1; - cmdq_off = 2; - cmdq_mask = CONFIG | DATA_ID; - reg_val = (type << 8) | config; - } - - for (i = 0; i < 0x20; i = i + 4) - dsi_write32((void *)DSI_BASE + 0x200 + i, 0); - - for (i = 0; i < len; i++) { - dsi_clrsetbits_le32((void *)DSI_BASE + 0x200 + - ((cmdq_off + i) & (0xfffffffc)), - (0xff << (((i + cmdq_off) & 3) * 8)), - tx_buf[i] << (((i + cmdq_off) & 3) * 8)); - } - - dsi_clrsetbits_le32(&dsi->dsi_cmdq0, cmdq_mask, reg_val); - dsi_clrsetbits_le32(&dsi->dsi_cmdq_size, CMDQ_SIZE, cmdq_size); - mtk_dsi_start(); - - stopwatch_init_usecs_expire(&sw, 400); - do { - intsta_0 = read32(&dsi->dsi_intsta); - if (intsta_0 & CMD_DONE_INT_FLAG) - break; - udelay(4); - } while (!stopwatch_expired(&sw)); - - if (!(intsta_0 & CMD_DONE_INT_FLAG)) - printk(BIOS_ERR, "dsi send cmd time-out(400uS)\n"); -} - -static void push_table(struct lcm_init_table *init_cmd) -{ - u32 cmd, i; - u32 type; - - for (i = 0; ; i++) { - cmd = init_cmd[i].cmd; - - switch (cmd) { - case DELAY_CMD: - mdelay(init_cmd[i].len); - break; - - case END_OF_TABLE: - return; - - case INIT_DCS_CMD: - switch (init_cmd[i].len) { - case 0: - return; - - case 1: - type = MIPI_DSI_DCS_SHORT_WRITE; - break; - - case 2: - type = MIPI_DSI_DCS_SHORT_WRITE_PARAM; - break; - - default: - type = MIPI_DSI_DCS_LONG_WRITE; - break; - } - mtk_dsi_cmdq(init_cmd[i].data, init_cmd[i].len, type); - break; - - case INIT_GENENIC_CMD: - default: - switch (init_cmd[i].len) { - case 0: - type = MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM; - break; - case 1: - type = MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM; - break; - case 2: - type = MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM; - break; - default: - type = MIPI_DSI_GENERIC_LONG_WRITE; - break; - } - mtk_dsi_cmdq(init_cmd[i].data, init_cmd[i].len, type); - break; - } - } -} - -int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, bool dual, - const struct edid *edid, struct lcm_init_table *init_cmd) -{ - int data_rate; - struct mtk_phy_timing phy_timing; - - mtk_dsi_phy_timing_calc(format, lanes, edid, &phy_timing); - - data_rate = mtk_dsi_phy_clk_setting(format, lanes, edid); - - if (data_rate < 0) - return -1; - - dsi_write32(&dsi->dsi_force_commit, 3); - mtk_dsi_reset(); - mtk_dsi_phy_timconfig(data_rate, &phy_timing); - mtk_dsi_rxtx_control(mode_flags, lanes); - mtk_dsi_config_vdo_timing(mode_flags, format, edid, &phy_timing, lanes); - mtk_dsi_clk_hs_mode_enable(); - push_table(init_cmd); - mtk_dsi_set_mode(mode_flags); - mtk_dsi_start(); - - return 0; -} +/* + * This file is part of the coreboot project. + * + * Copyright 2015 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/mmio.h> +#include <console/console.h> +#include <delay.h> +#include <soc/addressmap.h> +#include <soc/dsi.h> +#include <timer.h> + +void *getmipitx_regbase(u32 dsi_id) +{ + return dsi_id ? NULL : (void *)MIPITX_BASE; +} + +void *getdsi_regbase(u32 dsi_id) +{ + return dsi_id ? NULL : (void *)DSI_BASE; +} + +static void mtk_dsi_phy_timconfig(u32 dsi_id, u32 format, u32 lanes, const struct edid *edid, struct mtk_phy_timing *phy_timing) +{ + u32 timcon0, timcon1, timcon2, timcon3; + u32 ui, cycle_time, data_rate, bit_per_pixel; + struct dsi_regs *const dsi0 = getdsi_regbase(dsi_id); + + switch (format) { + case MIPI_DSI_FMT_RGB565: + bit_per_pixel = 16; + break; + case MIPI_DSI_FMT_RGB666: + case MIPI_DSI_FMT_RGB666_PACKED: + bit_per_pixel = 18; + break; + case MIPI_DSI_FMT_RGB888: + default: + bit_per_pixel = 24; + break; + } + + data_rate = edid->mode.pixel_clock * bit_per_pixel / lanes; + + ui = 1000 / (data_rate / 1000) + 1U; + cycle_time = 8000 / (data_rate / 1000) + 1U; + + phy_timing->lpx = DIV_ROUND_UP(60, cycle_time); + phy_timing->da_hs_prepare = DIV_ROUND_UP((40 + 5 * ui), cycle_time); + phy_timing->da_hs_zero = DIV_ROUND_UP((110 + 6 * ui), cycle_time); + phy_timing->da_hs_trail = DIV_ROUND_UP(((4 * ui) + 80), cycle_time); + + phy_timing->ta_go = 4U * phy_timing->lpx; + phy_timing->ta_sure = 3U * phy_timing->lpx / 2U; + phy_timing->ta_get = 5U * phy_timing->lpx; + phy_timing->da_hs_exit = 2U * phy_timing->lpx; + + phy_timing->clk_hs_zero = DIV_ROUND_UP(0x150U, cycle_time); + phy_timing->clk_hs_trail = DIV_ROUND_UP(0x64U, cycle_time) + 0xaU; + + phy_timing->clk_hs_prepare = DIV_ROUND_UP(0x40U, cycle_time); + phy_timing->clk_hs_post = DIV_ROUND_UP(80U + 52U * ui, cycle_time); + phy_timing->clk_hs_exit = 2U * phy_timing->lpx; + + + timcon0 = phy_timing->lpx | phy_timing->da_hs_prepare << 8 | + phy_timing->da_hs_zero << 16 | phy_timing->da_hs_trail << 24; + timcon1 = phy_timing->ta_go | phy_timing->ta_sure << 8 | + phy_timing->ta_get << 16 | phy_timing->da_hs_exit << 24; + timcon2 = 1 << 8 | phy_timing->clk_hs_zero << 16 | + phy_timing->clk_hs_trail << 24; + timcon3 = phy_timing->clk_hs_prepare | phy_timing->clk_hs_post << 8 | + phy_timing->clk_hs_exit << 16; + + dsi_write32(&dsi0->dsi_phy_timecon0, timcon0); + dsi_write32(&dsi0->dsi_phy_timecon1, timcon1); + dsi_write32(&dsi0->dsi_phy_timecon2, timcon2); + dsi_write32(&dsi0->dsi_phy_timecon3, timcon3); +} + +static int mtk_dsi_phy_clk_setting(u32 dsi_id, u32 format, u32 lanes, + const struct edid *edid) +{ + unsigned int txdiv, txdiv0, txdiv1; + u64 pcw; + int data_rate; + u32 bpp; + void *mipi_tx0 = getmipitx_regbase(dsi_id); + + if (dsi_id > 0) { + printk(BIOS_ERR, "No support dual dsi, please check you panel config\n"); + return -1; + } + + switch (format) { + case MIPI_DSI_FMT_RGB565: + bpp = 16; + break; + case MIPI_DSI_FMT_RGB666: + case MIPI_DSI_FMT_RGB666_PACKED: + bpp = 18; + break; + case MIPI_DSI_FMT_RGB888: + default: + bpp = 24; + break; + } + + data_rate = (u64)(edid->mode.pixel_clock * 1000 * bpp) / lanes; + + printk(BIOS_INFO, "data_rate: %u bps\n", data_rate); + + if (data_rate >= 2000000000) { + txdiv = 1; + txdiv0 = 0; + txdiv1 = 0; + } else if (data_rate >= 1000000000) { + txdiv = 2; + txdiv0 = 1; + txdiv1 = 0; + } else if (data_rate >= 500000000) { + txdiv = 4; + txdiv0 = 2; + txdiv1 = 0; + } else if (data_rate > 250000000) { + txdiv = 8; + txdiv0 = 3; + txdiv1 = 0; + } else if (data_rate >= 125000000) { + txdiv = 16; + txdiv0 = 4; + txdiv1 = 0; + } else { + printk(BIOS_ERR, "data rate (%u) must be >=50. Please check " + "pixel clock (%u), bpp (%u), number of lanes (%u)\n", + data_rate, edid->mode.pixel_clock, bpp, + lanes); + return -1; + } + + dsi_clrbits_le32(mipi_tx0 + MIPITX_PLL_CON4, BIT(11) | BIT(10)); + + dsi_setbits_le32(mipi_tx0 + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON); + udelay(30); + dsi_clrbits_le32(mipi_tx0 + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN); + + pcw = (u64)((data_rate / 1000000) * (1 << txdiv0) * (1 << txdiv1)); + pcw <<= 24; + pcw /= 26; + + dsi_write32(mipi_tx0 + MIPITX_PLL_CON0, pcw); + dsi_clrsetbits_le32(mipi_tx0 + MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV, + txdiv0 << 8); + udelay(30); + dsi_setbits_le32(mipi_tx0 + MIPITX_PLL_CON1, RG_DSI_PLL_EN); + + /* BG_LPF_EN / BG_CORE_EN */ + dsi_write32(mipi_tx0 + MIPITX_LANE_CON, 0x3FFF0180); + udelay(40); + dsi_write32(mipi_tx0 + MIPITX_LANE_CON, 0x3FFF00c0); + + /* Switch OFF each Lane */ + dsi_clrbits_le32(mipi_tx0 + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN); + dsi_clrbits_le32(mipi_tx0 + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN); + dsi_clrbits_le32(mipi_tx0 + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN); + dsi_clrbits_le32(mipi_tx0 + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN); + dsi_clrbits_le32(mipi_tx0 + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN); + + dsi_setbits_le32(mipi_tx0 + MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN); + + return data_rate; +} + +static void mtk_dsi_config_vdo_timing(u32 dsi_id, u32 mode_flags, u32 format, u32 lanes, + const struct edid *edid, struct mtk_phy_timing *phy_timing) +{ + u32 hsync_active_byte; + u32 hbp_byte; + u32 hfp_byte, tmp_hfp_byte; + u32 vbp_byte; + u32 vfp_byte; + u32 bpp; + u32 packet_fmt; + u32 hactive; + u32 data_phy_cycles; + struct dsi_regs *const dsi0 = getdsi_regbase(dsi_id); + + if (format == MIPI_DSI_FMT_RGB565) + bpp = 2; + else + bpp = 3; + + vbp_byte = edid->mode.vbl - edid->mode.vso - edid->mode.vspw - + edid->mode.vborder; + vfp_byte = edid->mode.vso - edid->mode.vborder; + + dsi_write32(&dsi0->dsi_vsa_nl, edid->mode.vspw); + dsi_write32(&dsi0->dsi_vbp_nl, vbp_byte); + dsi_write32(&dsi0->dsi_vfp_nl, vfp_byte); + dsi_write32(&dsi0->dsi_vact_nl, edid->mode.va); + + if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) + hbp_byte = (edid->mode.hbl - edid->mode.hso - edid->mode.hspw - + edid->mode.hborder) * bpp - 10; + else + hbp_byte = (edid->mode.hbl - edid->mode.hso - + edid->mode.hborder) * bpp - 10; + + hsync_active_byte = edid->mode.hspw * bpp - 10; + + data_phy_cycles = phy_timing->lpx + phy_timing->da_hs_prepare + + phy_timing->da_hs_zero + phy_timing->da_hs_exit + 2; + + tmp_hfp_byte = (edid->mode.hso - edid->mode.hborder) * bpp; + + if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { + if (tmp_hfp_byte > data_phy_cycles * lanes + 18) { + hfp_byte = tmp_hfp_byte - data_phy_cycles * lanes - 18; + } else { + printk(BIOS_ERR, "HFP less than d-phy, FPS will under 60Hz\n"); + hfp_byte = tmp_hfp_byte; + } + } else { + if (tmp_hfp_byte > data_phy_cycles * lanes + 12) { + hfp_byte = tmp_hfp_byte - data_phy_cycles * lanes - 12; + } else { + printk(BIOS_ERR, "HFP less than d-phy, FPS will under 60Hz\n"); + hfp_byte = tmp_hfp_byte; + } + } + + dsi_write32(&dsi0->dsi_hsa_wc, hsync_active_byte); + dsi_write32(&dsi0->dsi_hbp_wc, hbp_byte); + dsi_write32(&dsi0->dsi_hfp_wc, hfp_byte); + + switch (format) { + case MIPI_DSI_FMT_RGB888: + packet_fmt = PACKED_PS_24BIT_RGB888; + break; + case MIPI_DSI_FMT_RGB666: + packet_fmt = LOOSELY_PS_18BIT_RGB666; + break; + case MIPI_DSI_FMT_RGB666_PACKED: + packet_fmt = PACKED_PS_18BIT_RGB666; + break; + case MIPI_DSI_FMT_RGB565: + packet_fmt = PACKED_PS_16BIT_RGB565; + break; + default: + packet_fmt = PACKED_PS_24BIT_RGB888; + break; + } + + hactive = edid->mode.ha; + packet_fmt |= (hactive * bpp) & DSI_PS_WC; + + dsi_write32(&dsi0->dsi_psctrl, 0x2c << 24 | packet_fmt); + dsi_write32(&dsi0->dsi_size_con, edid->mode.va << 16 | hactive); + dsi_write32(&dsi0->dsi_force_commit, 3); +} + +int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, bool dual, + const struct edid *edid, struct lcm_init_table *init_cmd) +{ + int data_rate; + struct dsi_regs *const dsi0 = getdsi_regbase(0); + struct mtk_phy_timing *phy_timing = NULL; + + data_rate = mtk_dsi_phy_clk_setting(0, format, lanes, edid); + + if (data_rate < 0) + return -1; + + if (dual) { + data_rate = mtk_dsi_phy_clk_setting(1, format, lanes, edid); + if (data_rate < 0) + return -1; + } + + mtk_dsi_reset(0); + if (dual) + mtk_dsi_reset(1); + + mtk_dsi_rxtx_control(0, mode_flags, lanes); + mtk_dsi_phy_timconfig(0, format, lanes, edid, phy_timing); + mtk_dsi_config_vdo_timing(0, mode_flags, format, lanes, edid, phy_timing); + mtk_dsi_clk_hs_mode_enable(0); + + push_table(init_cmd); + + mtk_dsi_set_mode(0, mode_flags); + if (dual) { + mtk_dsi_set_mode(1, mode_flags); + dsi_write32(&dsi0->dsi_con_ctrl, DSI_EN | DSI_DUAL); + } + mtk_dsi_start(0); + + return 0; +} + diff --git a/src/soc/mediatek/mt8183/include/soc/dsi.h b/src/soc/mediatek/mt8183/include/soc/dsi.h index 1fb3509..5f614034 100644 --- a/src/soc/mediatek/mt8183/include/soc/dsi.h +++ b/src/soc/mediatek/mt8183/include/soc/dsi.h @@ -483,4 +483,19 @@ const struct edid *edid, struct lcm_init_table *init_cmd); +void *getmipitx_regbase(u32 dsi_id); +void *getdsi_regbase(u32 dsi_id); + +void dsi_write32(void *a, uint32_t v); +void dsi_clrsetbits_le32(void *a, uint32_t m, uint32_t v); +void dsi_clrbits_le32(void *a, uint32_t m); +void dsi_setbits_le32(void *a, uint32_t m); +void mtk_dsi_reset(u32 dsi_id); +void mtk_dsi_clk_hs_mode_enable(u32 dsi_id); +void mtk_dsi_set_mode(u32 dsi_id, u32 mode_flags); +void mtk_dsi_rxtx_control(u32 dsi_id, u32 mode_flags, u32 lanes); +void mtk_dsi_start(u32 dsi_id); +void push_table(struct lcm_init_table *init_cmd); + + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/34562 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I242d7a4f75057c0a955c9284a79c385a667ce7bd Gerrit-Change-Number: 34562 Gerrit-PatchSet: 1 Gerrit-Owner: jitao shi <jitao.shi(a)mediatek.com> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: WIP: mediatek/mt8183: Add SCP work support
by Erin Lo (Code Review) 31 Mar '22

31 Mar '22

Erin Lo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34382 ) Change subject: WIP: mediatek/mt8183: Add SCP work support ...................................................................... WIP: mediatek/mt8183: Add SCP work support Load SCP firmware to SCP's sram since buffer size is limited so load splitted binaries. After SCP works done, disable it Test=Build pass Change-Id: I0801eac078aa9d6237142dcd92a3c3e9237a86ee Signed-off-by: Erin Lo <erin.lo(a)mediatek.com> --- M src/mainboard/google/kukui/Makefile.inc M src/mainboard/google/kukui/romstage.c M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/addressmap.h A src/soc/mediatek/mt8183/include/soc/scp.h A src/soc/mediatek/mt8183/scp.c 6 files changed, 123 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/34382/1 diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc index a0556c1..f8a5bab 100644 --- a/src/mainboard/google/kukui/Makefile.inc +++ b/src/mainboard/google/kukui/Makefile.inc @@ -25,3 +25,18 @@ ramstage-y += mainboard.c ramstage-y += memlayout.ld ramstage-y += reset.c + +cbfs-files-y += scp_0.bin +scp_0.bin-file := 3rdparty/blobs/mainboard/google/kukui/scp_0.bin +scp_0.bin-type := raw +scp_0.bin-compression := none + +cbfs-files-y += scp_1.bin +scp_1.bin-file := 3rdparty/blobs/mainboard/google/kukui/scp_1.bin +scp_1.bin-type := raw +scp_1.bin-compression := none + +cbfs-files-y += scp_2.bin +scp_2.bin-file := 3rdparty/blobs/mainboard/google/kukui/scp_2.bin +scp_2.bin-type := raw +scp_2.bin-compression := none diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c index 1465243..cf3572d 100644 --- a/src/mainboard/google/kukui/romstage.c +++ b/src/mainboard/google/kukui/romstage.c @@ -19,7 +19,7 @@ #include <soc/mt6358.h> #include <soc/pll.h> #include <soc/rtc.h> - +#include <soc/scp.h> #include "early_init.h" void platform_romstage_main(void) @@ -33,6 +33,7 @@ pmic_set_vsim2_cali(2700); mt_pll_raise_ca53_freq(1989 * MHz); rtc_boot(); + scp_work(); mt_mem_init(get_sdram_config()); mtk_mmu_after_dram(); } diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index d35a07e..0543552 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -35,6 +35,7 @@ romstage-y += ../common/pll.c pll.c romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6358.c romstage-y += ../common/rtc.c rtc.c +romstage-y += scp.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c romstage-y += ../common/timer.c romstage-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index e9f80d1..affc776 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -34,6 +34,9 @@ EMI_BASE = IO_PHYS + 0x00219000, EMI_MPU_BASE = IO_PHYS + 0x00226000, DRAMC_CH_BASE = IO_PHYS + 0x00228000, + SCP_SRAM_BASE = IO_PHYS + 0x00500000, + SCP_CFG_BASE = IO_PHYS + 0x005C0000, + SCP_CLK_CTRL_BASE = IO_PHYS + 0x005C4000, AUXADC_BASE = IO_PHYS + 0x01001000, UART0_BASE = IO_PHYS + 0x01002000, SPI0_BASE = IO_PHYS + 0x0100A000, diff --git a/src/soc/mediatek/mt8183/include/soc/scp.h b/src/soc/mediatek/mt8183/include/soc/scp.h new file mode 100644 index 0000000..a3003bd --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/scp.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_MEDIATEK_MT8183_SCP_H +#define SOC_MEDIATEK_MT8183_SCP_H + +#include <soc/addressmap.h> +#include <types.h> + +struct mt8183_scp_regs { + u32 sw_rstn; + u32 reserved[19]; + u32 gpr0; +}; + +struct mt8183_scp_clk_ctrl_regs { + u32 reserved[11]; + u32 sram_pdn; +}; + +static struct mt8183_scp_regs *const mt8183_scp = (void *)SCP_CFG_BASE; +static struct mt8183_scp_clk_ctrl_regs *const mt8183_scp_clk_ctrl = (void *)SCP_CLK_CTRL_BASE; +void scp_work(void); +#endif /* SOC_MEDIATEK_MT8183_SCP_H */ diff --git a/src/soc/mediatek/mt8183/scp.c b/src/soc/mediatek/mt8183/scp.c new file mode 100644 index 0000000..150eeba --- /dev/null +++ b/src/soc/mediatek/mt8183/scp.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/barrier.h> +#include <cbfs.h> +#include <console/console.h> +#include <arch/mmio.h> +#include <soc/scp.h> +#include <string.h> + +#define BUF_SIZE (40 * KiB) +static uint8_t scp_bin[BUF_SIZE] __aligned(8); + +void scp_work(void) +{ + size_t fw_size; + + write32(&mt8183_scp_clk_ctrl->sram_pdn, 0x0); + mb(); + + fw_size = cbfs_boot_load_file("scp_0.bin", + scp_bin, + sizeof(scp_bin), + CBFS_TYPE_RAW); + if (fw_size == 0) + die("SCP file :scp_0.bin not found."); + memcpy((void *)SCP_SRAM_BASE + 0x0, scp_bin, fw_size); + + fw_size = cbfs_boot_load_file("scp_1.bin", + scp_bin, + sizeof(scp_bin), + CBFS_TYPE_RAW); + memcpy((void *)SCP_SRAM_BASE + BUF_SIZE, scp_bin, fw_size); + if (fw_size == 0) + die("SCP file :scp_1.bin not found."); + + fw_size = cbfs_boot_load_file("scp_2.bin", + scp_bin, + sizeof(scp_bin), + CBFS_TYPE_RAW); + if (fw_size == 0) + die("SCP file :scp_2.bin not found."); + memcpy((void *)SCP_SRAM_BASE + BUF_SIZE*2, scp_bin, fw_size); + + + /* Memory barrier to ensure that all fw code is loaded + before we release the reset pin. */ + mb(); + write32(&mt8183_scp->sw_rstn, 0x1); + while (read32(&mt8183_scp->gpr0) != 0xaaaa){} + mb(); + write32(&mt8183_scp->sw_rstn, 0x0); + printk(BIOS_DEBUG, "scp finished \n"); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/34382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0801eac078aa9d6237142dcd92a3c3e9237a86ee Gerrit-Change-Number: 34382 Gerrit-PatchSet: 1 Gerrit-Owner: Erin Lo <erin.lo(a)mediatek.com> Gerrit-MessageType: newchange

4 6

Change in ...coreboot[master]: WIP: libpayload: add initial support for RISC-V
by Philipp Hug (Code Review) 03 Mar '22

03 Mar '22

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31356 Change subject: WIP: libpayload: add initial support for RISC-V ...................................................................... WIP: libpayload: add initial support for RISC-V Parse fdt provided by a2 and extract coreboot tables from it. Change-Id: I91df02069a0f8fd8771f73de0e866e9cea05cded Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M payloads/libpayload/Kconfig M payloads/libpayload/Makefile M payloads/libpayload/Makefile.inc A payloads/libpayload/arch/riscv/Kconfig A payloads/libpayload/arch/riscv/Makefile.inc A payloads/libpayload/arch/riscv/coreboot.c A payloads/libpayload/arch/riscv/head.S A payloads/libpayload/arch/riscv/libpayload.ldscript A payloads/libpayload/arch/riscv/main.c A payloads/libpayload/arch/riscv/sysinfo.c A payloads/libpayload/arch/riscv/timer.c A payloads/libpayload/arch/riscv/util.S A payloads/libpayload/arch/riscv/virtual.c M payloads/libpayload/bin/lpgcc A payloads/libpayload/configs/config.riscv A payloads/libpayload/configs/defconfig-riscv A payloads/libpayload/include/riscv/arch/asm.h A payloads/libpayload/include/riscv/arch/barrier.h A payloads/libpayload/include/riscv/arch/cache.h A payloads/libpayload/include/riscv/arch/io.h A payloads/libpayload/include/riscv/arch/types.h A payloads/libpayload/include/riscv/arch/virtual.h 22 files changed, 1,094 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/31356/1 diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index 5bfbd54..846280d 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -119,6 +119,11 @@ help Support the MIPS architecture +config ARCH_RISCV + bool "RISCV" + help + Support the RISCV architecture + endchoice config MULTIBOOT @@ -148,12 +153,13 @@ default 0x04000000 if ARCH_ARM default 0x80100000 if ARCH_ARM64 default 0x00000000 if ARCH_MIPS + default 0x81000000 if ARCH_RISCV default 0x00100000 if ARCH_X86 help This is the base address for the payload. If unsure, set to 0x00100000 on x86, 0x00000000 on MIPS, - 0x04000000 on ARM or 0x80100000 on ARM64. + 0x04000000 on ARM or 0x80100000 on ARM64 or 0x81000000 on RISCV. endmenu @@ -451,4 +457,5 @@ source "arch/arm/Kconfig" source "arch/arm64/Kconfig" source "arch/mips/Kconfig" +source "arch/riscv/Kconfig" source "arch/x86/Kconfig" diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile index 1a0acf1..e01115e 100644 --- a/payloads/libpayload/Makefile +++ b/payloads/libpayload/Makefile @@ -96,6 +96,7 @@ ARCHDIR-$(CONFIG_LP_ARCH_ARM) := arm ARCHDIR-$(CONFIG_LP_ARCH_ARM64) := arm64 ARCHDIR-$(CONFIG_LP_ARCH_MIPS) := mips +ARCHDIR-$(CONFIG_LP_ARCH_RISCV) := riscv ARCHDIR-$(CONFIG_LP_ARCH_X86) := x86 ARCH-y := $(ARCHDIR-y) @@ -105,6 +106,7 @@ ARCH-$(CONFIG_LP_ARCH_ARM) := arm ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64 ARCH-$(CONFIG_LP_ARCH_X86) := x86_32 +ARCH-$(CONFIG_LP_ARCH_RISCV) := riscv ARCH-$(CONFIG_LP_ARCH_MIPS) := mips # Three cases where we don't need fully populated $(obj) lists: diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index 052a3f0..8ea0810 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -34,6 +34,7 @@ ARCHDIR-$(CONFIG_LP_ARCH_ARM) := arm ARCHDIR-$(CONFIG_LP_ARCH_ARM64) := arm64 ARCHDIR-$(CONFIG_LP_ARCH_MIPS) := mips +ARCHDIR-$(CONFIG_LP_ARCH_RISCV) := riscv ARCHDIR-$(CONFIG_LP_ARCH_X86) := x86 DESTDIR ?= install @@ -61,12 +62,15 @@ INCLUDES := -Iinclude -Iinclude/$(ARCHDIR-y) -I$(obj) -include include/kconfig.h +ARCHCFLAGS-$(CONFIG_LP_ARCH_RISCV) := -mcmodel=medany + CFLAGS += $(EXTRA_CFLAGS) $(INCLUDES) -Os -pipe -nostdinc -ggdb3 CFLAGS += -nostdlib -fno-builtin -ffreestanding -fomit-frame-pointer CFLAGS += -ffunction-sections -fdata-sections CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs CFLAGS += -Wstrict-aliasing -Wshadow -Werror +CFLAGS += $(ARCHCFLAGS-y) $(obj)/libpayload-config.h: $(KCONFIG_AUTOHEADER) cmp $@ $< 2>/dev/null || cp $< $@ diff --git a/payloads/libpayload/arch/riscv/Kconfig b/payloads/libpayload/arch/riscv/Kconfig new file mode 100644 index 0000000..6352ff0 --- /dev/null +++ b/payloads/libpayload/arch/riscv/Kconfig @@ -0,0 +1,37 @@ +## +## This file is part of the libpayload project. +## +## Copyright (c) 2012 Google Inc. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions +## are met: +## 1. Redistributions of source code must retain the above copyright +## notice, this list of conditions and the following disclaimer. +## 2. Redistributions in binary form must reproduce the above copyright +## notice, this list of conditions and the following disclaimer in the +## documentation and/or other materials provided with the distribution. +## 3. The name of the author may not be used to endorse or promote products +## derived from this software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +## SUCH DAMAGE. +## + +if ARCH_RISCV + +config ARCH_SPECIFIC_OPTIONS # dummy + def_bool y + select LITTLE_ENDIAN + select FDT + +endif diff --git a/payloads/libpayload/arch/riscv/Makefile.inc b/payloads/libpayload/arch/riscv/Makefile.inc new file mode 100644 index 0000000..01d6bd8 --- /dev/null +++ b/payloads/libpayload/arch/riscv/Makefile.inc @@ -0,0 +1,34 @@ +## +## This file is part of the libpayload project. +## +## Copyright (C) 2008 Advanced Micro Devices, Inc. +## +## Redistribution and use in source and binary forms, with or without +## modification, are permitted provided that the following conditions +## are met: +## 1. Redistributions of source code must retain the above copyright +## notice, this list of conditions and the following disclaimer. +## 2. Redistributions in binary form must reproduce the above copyright +## notice, this list of conditions and the following disclaimer in the +## documentation and/or other materials provided with the distribution. +## 3. The name of the author may not be used to endorse or promote products +## derived from this software without specific prior written permission. +## +## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +## SUCH DAMAGE. +## + +head.o-y += head.S + +libc-y += main.c sysinfo.c +libc-y += timer.c coreboot.c util.S +libc-y += virtual.c diff --git a/payloads/libpayload/arch/riscv/coreboot.c b/payloads/libpayload/arch/riscv/coreboot.c new file mode 100644 index 0000000..ea21c51 --- /dev/null +++ b/payloads/libpayload/arch/riscv/coreboot.c @@ -0,0 +1,94 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2019 Philipp Hug <philipp(a)hug.cx> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <libpayload-config.h> +#include <libpayload.h> +#include <coreboot_tables.h> +#include <libfdt.h> + +/* This pointer gets set in head.S and is passed in from coreboot. */ +void *fdt_ptr; +int hart_id; + +/* == Architecture specific == */ + +int cb_parse_arch_specific(struct cb_record *rec, struct sysinfo_t *info) +{ + switch (rec->tag) { + default: + return 0; + } + return 1; +} + +int get_coreboot_info(struct sysinfo_t *info) +{ + void *cb_header_ptr = get_cb_header_ptr(); + if (cb_header_ptr == NULL) + return 1; + return cb_parse_header(cb_header_ptr, 1, info); +} + +void *get_cb_header_ptr(void) +{ + int offset; + int len; + const struct fdt_property *prop; + + /* + * coreboot tables are provides within the fdt which was passes as + * a2 to the entry point + */ + + if (fdt_check_header(fdt_ptr) != 0) { + printf("fdt: invalid header\n"); + return NULL; + } + + // search for coreboot node + offset = fdt_node_offset_by_compatible(fdt_ptr, -1, "coreboot"); + if (offset < 0) { + printf("fdt: coreboot node not found\n"); + return NULL; + } + + /* + * get reg property and extract the pointer to the coreboot tables + * TODO: parse cell info and fix for RV32 + */ + prop = fdt_get_property(fdt_ptr, offset, "reg", &len); + if (len != 32) { + printf("fdt: invalid reg property\n"); + return NULL; + } + + return (void *)fdt64_ld((fdt64_t *)prop->data); +} diff --git a/payloads/libpayload/arch/riscv/head.S b/payloads/libpayload/arch/riscv/head.S new file mode 100644 index 0000000..c46b20b --- /dev/null +++ b/payloads/libpayload/arch/riscv/head.S @@ -0,0 +1,74 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2019 Philipp Hug <philipp(a)hug.cx> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <arch/asm.h> + +/* + * Our entry point + */ +ENTRY(_entry) + + /* Save off hart id in a0 */ + la t0, hart_id + sd a0, 0(t0) + + /* Save off device tree pointer in a1 */ + la t0, fdt_ptr + sd a1, 0(t0) + + /* + * busy-loop for harts != 0 + * TODO: add support hart > 0 + */ + li a3, 0 + beq a0, a3, _hart_zero +_hart_loop: + j _hart_loop +_hart_zero: + + /* + * Setup new stack + * TODO, use stack per hart + */ + la t0, _stack + li t1, 0xDEADBEEF + sd t1, 0(t0) + add sp, t0, 0 + + /* Let's rock. */ + tail start_main + +ENDPROC(_entry) + +.align 4 +1: +.quad fdt_ptr +2: +.quad _stack diff --git a/payloads/libpayload/arch/riscv/libpayload.ldscript b/payloads/libpayload/arch/riscv/libpayload.ldscript new file mode 100644 index 0000000..1929549 --- /dev/null +++ b/payloads/libpayload/arch/riscv/libpayload.ldscript @@ -0,0 +1,91 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv","elf64-littleriscv") +OUTPUT_ARCH(riscv) + +ENTRY(_entry) + +SECTIONS +{ + . = CONFIG_LP_BASE_ADDRESS; + + . = ALIGN(16); + _start = .; + + .text : { + *(.text._entry) + *(.text) + *(.text.*) + } + + .rodata : { + *(.rodata) + *(.rodata.*) + } + + .data : { + *(.data) + *(.data.*) + } + + _edata = .; + + .bss : { + *(.sbss) + *(.sbss.*) + *(.bss) + *(.bss.*) + *(COMMON) + + /* Stack and heap */ + + . = ALIGN(16); + _heap = .; + . += CONFIG_LP_HEAP_SIZE; + . = ALIGN(16); + _eheap = .; + + _estack = .; + . += CONFIG_LP_STACK_SIZE; + . = ALIGN(16); + _stack = .; + } + .debug : { + *(.debug) + } + + _end = .; + + /DISCARD/ : { + *(.comment) + *(.note*) + } +} diff --git a/payloads/libpayload/arch/riscv/main.c b/payloads/libpayload/arch/riscv/main.c new file mode 100644 index 0000000..83fb841 --- /dev/null +++ b/payloads/libpayload/arch/riscv/main.c @@ -0,0 +1,72 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <libpayload.h> + +unsigned int main_argc; /**< The argc value to pass to main() */ + +/** The argv value to pass to main() */ +char *main_argv[MAX_ARGC_COUNT]; + +/** + * This is our C entry function - set up the system + * and jump into the payload entry point. + */ +void start_main(void); +void start_main(void) +{ + extern int main(int argc, char **argv); + + /* Gather system information. */ + lib_get_sysinfo(); + +#if !IS_ENABLED(CONFIG_LP_SKIP_CONSOLE_INIT) + console_init(); +#endif + + // TODO: implement exceptions + // exception_init(); + + /* + * Any other system init that has to happen before the + * user gets control goes here. + */ + + /* + * Go to the entry point. + * In the future we may care about the return value. + */ + + (void)main(main_argc, (main_argc != 0) ? main_argv : NULL); + + /* + * Returning here will go to the _leave function to return + * us to the original context. + */ +} diff --git a/payloads/libpayload/arch/riscv/sysinfo.c b/payloads/libpayload/arch/riscv/sysinfo.c new file mode 100644 index 0000000..575b7da --- /dev/null +++ b/payloads/libpayload/arch/riscv/sysinfo.c @@ -0,0 +1,79 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <libpayload-config.h> +#include <libpayload.h> +#include <coreboot_tables.h> + +/** + * This is a global structure that is used through the library - we set it + * up initially with some dummy values - hopefully they will be overridden. + * Also set some defaults for the console in case the fdt is messed up. + */ +struct cb_serial serial_info = { + .baseaddr = 0x10000000, + .type = CB_SERIAL_TYPE_MEMORY_MAPPED, + .regwidth = 1, +}; + +struct sysinfo_t lib_sysinfo = { + .cpu_khz = 1000, + .serial = &serial_info, +}; + +int lib_get_sysinfo(void) +{ + int ret; + + /* Get the CPU speed (for delays). */ + lib_sysinfo.cpu_khz = get_cpu_speed(); + + /* Get information from the coreboot tables, + * if they exist */ + + ret = get_coreboot_info(&lib_sysinfo); + + if (!lib_sysinfo.n_memranges) { + /* If we can't get a good memory range, use the default. */ + lib_sysinfo.n_memranges = 1; + + lib_sysinfo.memrange[0].base = 0x80000000u; + lib_sysinfo.memrange[0].size = 1024 * 1024; + lib_sysinfo.memrange[0].type = CB_MEM_RAM; + } + + return ret; +} + +void lib_sysinfo_get_memranges(struct memrange **ranges, + uint64_t *nranges) +{ + *ranges = &lib_sysinfo.memrange[0]; + *nranges = lib_sysinfo.n_memranges; +} diff --git a/payloads/libpayload/arch/riscv/timer.c b/payloads/libpayload/arch/riscv/timer.c new file mode 100644 index 0000000..d233ddc --- /dev/null +++ b/payloads/libpayload/arch/riscv/timer.c @@ -0,0 +1,54 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +/** + * @file riscv/timer.c + * RISC-V specific timer routines + */ + +#include <libpayload.h> + +/** + * @ingroup arch + * Global variable containing the speed of the processor in KHz. + */ +u32 cpu_khz; + +/** + * Calculate the speed of the processor for use in delays. + * + * @return The CPU speed in kHz. + */ +unsigned int get_cpu_speed(void) +{ + /* FIXME */ + cpu_khz = 1000000U; + + return cpu_khz; +} diff --git a/payloads/libpayload/arch/riscv/util.S b/payloads/libpayload/arch/riscv/util.S new file mode 100644 index 0000000..dde2099 --- /dev/null +++ b/payloads/libpayload/arch/riscv/util.S @@ -0,0 +1,35 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2012 Google, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <arch/asm.h> + +/* This function puts the system into a halt. */ +ENTRY(halt) + j halt +ENDPROC(halt) diff --git a/payloads/libpayload/arch/riscv/virtual.c b/payloads/libpayload/arch/riscv/virtual.c new file mode 100644 index 0000000..c3f4aa7 --- /dev/null +++ b/payloads/libpayload/arch/riscv/virtual.c @@ -0,0 +1,40 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2008 coresystems GmbH + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <libpayload.h> +#include <assert.h> +#include <die.h> +#include <stdlib.h> +#include <unistd.h> +#include <arch/cache.h> +#include <arch/virtual.h> +#include <arch/io.h> + +unsigned long virtual_offset = 0; +extern char _end[]; diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index b3ef342..2faf113 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -86,6 +86,12 @@ _ARCHEXTRA="" _ARCH=mips fi +if [ "$CONFIG_LP_ARCH_RISCV" = "y" ]; then + _ARCHINCDIR=$_INCDIR/riscv + _ARCHLIBDIR=$_LIBDIR/riscv + _ARCHEXTRA="" + _ARCH=riscv +fi if [ "$CONFIG_LP_ARCH_X86" = "y" ]; then _ARCHINCDIR=$_INCDIR/x86 _ARCHLIBDIR=$_LIBDIR/x86 diff --git a/payloads/libpayload/configs/config.riscv b/payloads/libpayload/configs/config.riscv new file mode 100644 index 0000000..7982b4a --- /dev/null +++ b/payloads/libpayload/configs/config.riscv @@ -0,0 +1,81 @@ +# +# Automatically generated file; DO NOT EDIT. +# Libpayload Configuration +# + +# +# Generic Options +# +# CONFIG_LP_GPL is not set +# CONFIG_LP_EXPERIMENTAL is not set +# CONFIG_LP_DEVELOPER is not set +# CONFIG_LP_CHROMEOS is not set +CONFIG_LP_COMPILER_GCC=y +# CONFIG_LP_COMPILER_LLVM_CLANG is not set +# CONFIG_LP_MEMMAP_RAM_ONLY is not set + +# +# Architecture Options +# +# CONFIG_LP_ARCH_ARM is not set +# CONFIG_LP_ARCH_X86 is not set +# CONFIG_LP_ARCH_ARM64 is not set +# CONFIG_LP_ARCH_MIPS is not set +CONFIG_LP_ARCH_RISCV=y +CONFIG_LP_HEAP_SIZE=131072 +CONFIG_LP_STACK_SIZE=16384 +CONFIG_LP_BASE_ADDRESS=0x80100000 + +# +# Standard Libraries +# +CONFIG_LP_LIBC=y +# CONFIG_LP_CURSES is not set +CONFIG_LP_CBFS=y +CONFIG_LP_LZMA=y +CONFIG_LP_LZ4=y + +# +# Console Options +# +# CONFIG_LP_SKIP_CONSOLE_INIT is not set +CONFIG_LP_CBMEM_CONSOLE=y +# CONFIG_LP_SERIAL_CONSOLE is not set +CONFIG_LP_VIDEO_CONSOLE=y +# CONFIG_LP_COREBOOT_VIDEO_CONSOLE is not set +# CONFIG_LP_PC_I8042 is not set +# CONFIG_LP_PC_MOUSE is not set +# CONFIG_LP_PC_KEYBOARD is not set + +# +# Drivers +# +# CONFIG_LP_MOUSE_CURSOR is not set +# CONFIG_LP_RTC_PORT_EXTENDED_VIA is not set +CONFIG_LP_TIMER_NONE=y +# CONFIG_LP_TIMER_MCT is not set +# CONFIG_LP_TIMER_TEGRA_1US is not set +# CONFIG_LP_TIMER_IPQ806X is not set +# CONFIG_LP_TIMER_ARMADA38X is not set +# CONFIG_LP_TIMER_IPQ40XX is not set +# CONFIG_LP_TIMER_ARM64_ARCH is not set +# CONFIG_LP_TIMER_RK3288 is not set +# CONFIG_LP_TIMER_RK3399 is not set +# CONFIG_LP_TIMER_CYGNUS is not set +# CONFIG_LP_TIMER_IMG_PISTACHIO is not set +# CONFIG_LP_TIMER_MTK is not set +# CONFIG_LP_TIMER_MVMAP2315 is not set +CONFIG_LP_TIMER_GENERIC_HZ=100000 +CONFIG_LP_TIMER_GENERIC_REG=0x0 +CONFIG_LP_TIMER_GENERIC_HIGH_REG=0x0 +CONFIG_LP_STORAGE=y +# CONFIG_LP_STORAGE_64BIT_LBA is not set +CONFIG_LP_STORAGE_ATA=y +CONFIG_LP_STORAGE_ATAPI=y +# CONFIG_LP_USB is not set +# CONFIG_LP_USB_GEN_HUB is not set +# CONFIG_LP_UDC is not set +# CONFIG_LP_BIG_ENDIAN is not set +CONFIG_LP_LITTLE_ENDIAN=y +# CONFIG_LP_IO_ADDRESS_SPACE is not set +CONFIG_LP_ARCH_SPECIFIC_OPTIONS=y diff --git a/payloads/libpayload/configs/defconfig-riscv b/payloads/libpayload/configs/defconfig-riscv new file mode 100644 index 0000000..2ce2bc5 --- /dev/null +++ b/payloads/libpayload/configs/defconfig-riscv @@ -0,0 +1,3 @@ +CONFIG_LP_ARCH_RISCV=y +CONFIG_LP_TINYCURSES=n +CONFIG_LP_USB=n diff --git a/payloads/libpayload/include/riscv/arch/asm.h b/payloads/libpayload/include/riscv/arch/asm.h new file mode 100644 index 0000000..842fb0d --- /dev/null +++ b/payloads/libpayload/include/riscv/arch/asm.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + */ + +#ifndef __RISCV_ASM_H +#define __RISCV_ASM_H + +# define RISCV(x...) x +# define W(instr) instr + +#define ALIGN .align 2 + +#define ENDPROC(name) \ + .type name, %function; \ + END(name) + +#define ENTRY(name) \ + .section .text.name, "ax", %progbits; \ + .global name; \ + ALIGN; \ + name: + +#define END(name) \ + .size name, .-name + +#endif /* __RISCV_ASM_H */ diff --git a/payloads/libpayload/include/riscv/arch/barrier.h b/payloads/libpayload/include/riscv/arch/barrier.h new file mode 100644 index 0000000..0b55df6 --- /dev/null +++ b/payloads/libpayload/include/riscv/arch/barrier.h @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * Copyright (C) 2003-2004 Olivier Houchard + * Copyright (C) 1994-1997 Mark Brinicombe + * Copyright (C) 1994 Brini + * All rights reserved. + * + * This code is derived from software written for Brini by Mark Brinicombe + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + */ + +#ifndef __ARCH_BARRIER_H_ +#define __ARCH_BARRIER_H__ + +#include <arch/cache.h> + +/* + * Description of different memory barriers introduced: + * + * Memory barrier(mb) - Guarantees that all memory accesses specified before the + * barrier will happen before all memory accesses specified after the barrier + * + * Read memory barrier (rmb) - Guarantees that all read memory accesses + * specified before the barrier will happen before all read memory accesses + * specified after the barrier + * + * Write memory barrier (wmb) - Guarantees that all write memory accesses + * specified before the barrier will happen before all write memory accesses + * specified after the barrier + */ + +#define mb() +#define rmb() +#define wmb() + +#endif /* __ARCH_BARRIER_H__ */ diff --git a/payloads/libpayload/include/riscv/arch/cache.h b/payloads/libpayload/include/riscv/arch/cache.h new file mode 100644 index 0000000..820bee9 --- /dev/null +++ b/payloads/libpayload/include/riscv/arch/cache.h @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + * + * cache.h: Cache maintenance API for RISCV + */ + +#ifndef RISCV_CACHE_H +#define RISCV_CACHE_H + +#include <stddef.h> +#include <stdint.h> + +/* + * Cache maintenance API + */ + +/* dcache clean and invalidate all (on current level given by CCSELR) */ +void dcache_clean_invalidate_all(void); + +/* dcache clean by virtual address to PoC */ +void dcache_clean_by_mva(void const *addr, size_t len); + +/* dcache clean and invalidate by virtual address to PoC */ +void dcache_clean_invalidate_by_mva(void const *addr, size_t len); + +/* dcache invalidate by virtual address to PoC */ +void dcache_invalidate_by_mva(void const *addr, size_t len); + +void dcache_clean_all(void); + +/* dcache invalidate all (on current level given by CCSELR) */ +void dcache_invalidate_all(void); + +/* returns number of bytes per cache line */ +unsigned int dcache_line_bytes(void); + +/* dcache and MMU disable */ +void dcache_mmu_disable(void); + +/* dcache and MMU enable */ +void dcache_mmu_enable(void); + +/* perform all icache/dcache maintenance needed after loading new code */ +void cache_sync_instructions(void); + +/* Ensure that loaded program segment is synced back from cache to PoC */ +void arch_program_segment_loaded(void const *addr, size_t len); + +/* tlb invalidate all */ +void tlb_invalidate_all(void); + +/* Invalidate all of the instruction cache for PE to PoU. */ +static inline void icache_invalidate_all(void) +{ + return; +} + +#endif /* RISCV_CACHE_H */ diff --git a/payloads/libpayload/include/riscv/arch/io.h b/payloads/libpayload/include/riscv/arch/io.h new file mode 100644 index 0000000..8413b61 --- /dev/null +++ b/payloads/libpayload/include/riscv/arch/io.h @@ -0,0 +1,106 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2008 coresystems GmbH + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _ARCH_IO_H +#define _ARCH_IO_H + +#include <stdint.h> +#include <arch/cache.h> +//#include <arch/lib_helpers.h> + +/* + * readb/w/l writeb/w/l are deprecated. use read8/16/32 and write8/16/32 + * instead for future development. + * + * TODO: make the existing code use read8/16/32 and write8/16/32 then remove + * readb/w/l and writeb/w/l. + */ + +static inline uint8_t readb(volatile const void *_a) +{ + return *(volatile const uint8_t *)_a; +} + +static inline uint16_t readw(volatile const void *_a) +{ + return *(volatile const uint16_t *)_a; +} + +static inline uint32_t readl(volatile const void *_a) +{ + return *(volatile const uint32_t *)_a; +} + +static inline void writeb(uint8_t _v, volatile void *_a) +{ + *(volatile uint8_t *)_a = _v; +} + +static inline void writew(uint16_t _v, volatile void *_a) +{ + *(volatile uint16_t *)_a = _v; +} + +static inline void writel(uint32_t _v, volatile void *_a) +{ + *(volatile uint32_t *)_a = _v; +} + +static inline uint8_t read8(const void *addr) +{ + return *(volatile uint8_t *)addr; +} + +static inline uint16_t read16(const void *addr) +{ + return *(volatile uint16_t *)addr; +} + +static inline uint32_t read32(const void *addr) +{ + return *(volatile uint32_t *)addr; +} + +static inline void write8(void *addr, uint8_t val) +{ + *(volatile uint8_t *)addr = val; +} + +static inline void write16(void *addr, uint16_t val) +{ + *(volatile uint16_t *)addr = val; +} + +static inline void write32(void *addr, uint32_t val) +{ + *(volatile uint32_t *)addr = val; +} + +#endif diff --git a/payloads/libpayload/include/riscv/arch/types.h b/payloads/libpayload/include/riscv/arch/types.h new file mode 100644 index 0000000..1bd815b --- /dev/null +++ b/payloads/libpayload/include/riscv/arch/types.h @@ -0,0 +1,60 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _ARCH_TYPES_H +#define _ARCH_TYPES_H + +typedef unsigned char uint8_t; +typedef unsigned char u8; +typedef signed char int8_t; +typedef signed char s8; + +typedef unsigned short uint16_t; +typedef unsigned short u16; +typedef signed short int16_t; +typedef signed short s16; + +typedef unsigned int uint32_t; +typedef unsigned int u32; +typedef signed int int32_t; +typedef signed int s32; + +typedef unsigned long long uint64_t; +typedef unsigned long long u64; +typedef signed long long int64_t; +typedef signed long long s64; + +typedef long time_t; +typedef long suseconds_t; + +#ifndef NULL +#define NULL ((void *)0) +#endif + +#endif diff --git a/payloads/libpayload/include/riscv/arch/virtual.h b/payloads/libpayload/include/riscv/arch/virtual.h new file mode 100644 index 0000000..dac3480 --- /dev/null +++ b/payloads/libpayload/include/riscv/arch/virtual.h @@ -0,0 +1,41 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2008 coresystems GmbH + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _ARCH_VIRTUAL_H +#define _ARCH_VIRTUAL_H + +extern unsigned long virtual_offset; + +#define virt_to_phys(virt) ((unsigned long)(virt) + virtual_offset) +#define phys_to_virt(phys) ((void *)((unsigned long)(phys)-virtual_offset)) + +#define virt_to_bus(addr) virt_to_phys(addr) +#define bus_to_virt(addr) phys_to_virt(addr) + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I91df02069a0f8fd8771f73de0e866e9cea05cded Gerrit-Change-Number: 31356 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: newchange

4 5

Change in ...coreboot[master]: Documentation: Document PMH known registers
by Patrick Rudolph (Code Review) 20 Feb '22

20 Feb '22

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32253 Change subject: Documentation: Document PMH known registers ...................................................................... Documentation: Document PMH known registers Document what is known of Lenovo's PMH. Change-Id: I1891a6370123d9ee29d9e37e4b7b78b677343aed Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/pmh.md 2 files changed, 70 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/32253/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index d94c23e..adfe877 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -54,6 +54,7 @@ - [Hardware Maintenance Manual of ThinkPads](lenovo/thinkpad_hmm.md) - [T4xx common](lenovo/t4xx_series.md) - [X2xx common](lenovo/x2xx_series.md) +- [PMH](lenovo/pmh.md) ### Sandy Bridge series diff --git a/Documentation/mainboard/lenovo/pmh.md b/Documentation/mainboard/lenovo/pmh.md new file mode 100644 index 0000000..06c595d --- /dev/null +++ b/Documentation/mainboard/lenovo/pmh.md @@ -0,0 +1,69 @@ +# Lenovo's Power Management Hub + +The *Power Management Hub* or *PMH* originally was a CPLD connected to the EC +to controll power rails and reset lines on the lenovo mainboard. +Starting with Ivy Bridge series, the CPLD was removed and an EC with higher +pincount does the same job. The IO space to configure the PMH is still +the same. + +## PMH access + +The PMH register can be accessed using the IO region: + + IO region address: 0x15e0 + IO region size: 16 + +The IO region has the following layout: + +```eval_rst ++-------------------+---------------------------------------+ +| Offset | Register function | ++-------------------+---------------------------------------+ +| 0xc | ADDR_L: Low address into PMH space | ++-------------------+---------------------------------------+ +| 0xd | ADDR_H: High address into PMH space | ++-------------------+---------------------------------------+ +| 0xe | DATA: The data to read/write in PMH | ++-------------------+---------------------------------------+ +``` + +The PMH register space allows to access 512bytes. +The following registers are known: + +```eval_rst ++-------------------+---------------------------------------+ +| Offset | Register function | ++-------------------+---------------------------------------+ +| 0x50 | BIT3: dGPU power enable | +| +---------------------------------------+ +| | BIT5: Backlight enable | +| +---------------------------------------+ +| | BIT7: dGPU !reset | ++-------------------+---------------------------------------+ +| 0x51 | BIT0: Trackpoint enable | +| +---------------------------------------+ +| | BIT2: Touchpad enable | ++-------------------+---------------------------------------+ +| 0x60 | BIT3: Dock event enable | ++-------------------+---------------------------------------+ +| 0x62 | BIT0: Ultrabay power enable | ++-------------------+---------------------------------------+ +| 0xc2 | ID: ID of PMH | ++-------------------+---------------------------------------+ +| 0xc3 | REV: Revision of PMH | ++-------------------+---------------------------------------+ +``` + +The revision at 0xc3 seems to increment over time: + +```eval_rst ++-------------------+---------------------------------------+ +| Revision | Mainboard generation | ++-------------------+---------------------------------------+ +| 4 | T520 and T420s | ++-------------------+---------------------------------------+ +| 5 | W530 | ++-------------------+---------------------------------------+ +| 6 | T470p | ++-------------------+---------------------------------------+ +``` -- To view, visit https://review.coreboot.org/c/coreboot/+/32253 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1891a6370123d9ee29d9e37e4b7b78b677343aed Gerrit-Change-Number: 32253 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 12

Change in ...coreboot[master]: soc/intel/apl: enable lpc at bootblock
by Thomas Heijligen (Code Review) 01 Feb '22

01 Feb '22

Hello Nico Huber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31371 to review the following change. Change subject: soc/intel/apl: enable lpc at bootblock ...................................................................... soc/intel/apl: enable lpc at bootblock Serial console can be attached to lpc bus. Enable it for early debug Change-Id: Ib3d09e4eb23655825b7603f49f0bad31116ac6e1 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Signed-off-by: Thomas Heijligen <thomas.heijligen(a)secunet.com> --- M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/chip.h M src/soc/intel/apollolake/lpc.c M src/soc/intel/common/block/lpc/lpc_lib.c 4 files changed, 21 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/31371/1 diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index cf3e839..e0217ef 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -20,6 +20,7 @@ #include <device/pci.h> #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> +#include <intelblocks/lpc_lib.h> #include <intelblocks/p2sb.h> #include <intelblocks/pcr.h> #include <intelblocks/rtc.h> @@ -120,4 +121,6 @@ paging_set_default_pat(); paging_enable_for_car("pdpt", "pt"); } + + pch_enable_lpc(); } diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index b8f9f8c..2f25a3b 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -44,6 +44,9 @@ /* Common structure containing soc config data required by common code*/ struct soc_intel_common_config common_soc_config; + /* Generic i/o decode ranges routed to LPC */ + uint32_t lpc_gen_dec[4]; + /* * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has * four CLKREQ inputs, but six root ports. Root ports without an diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index a20b82a..ffa4cf5 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -42,6 +42,18 @@ return apl_lpc_fixed_mmio_ranges; } +void soc_get_gen_io_dec_range(const struct device *dev, uint32_t *gen_io_dec) +{ + const struct soc_intel_apollolake_config *const config = dev->chip_info; + + if (!config) { + memset(gen_io_dec, 0x00, sizeof(config->lpc_gen_dec)); + return; + } + + memcpy(gen_io_dec, config->lpc_gen_dec, sizeof(config->lpc_gen_dec)); +} + static const struct pad_config lpc_gpios[] = { #if IS_ENABLED(CONFIG_SOC_INTEL_GLK) #if !IS_ENABLED(CONFIG_SOC_ESPI) diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c index fb50b74..d584d2c 100644 --- a/src/soc/intel/common/block/lpc/lpc_lib.c +++ b/src/soc/intel/common/block/lpc/lpc_lib.c @@ -24,6 +24,9 @@ #include <lib.h> #include "lpc_def.h" #include <soc/pci_devs.h> +#include <stdint.h> + +__weak void soc_setup_dmi_pcr_io_dec(uint32_t *gen_io_dec) {} uint16_t lpc_enable_fixed_io_ranges(uint16_t io_enables) { -- To view, visit https://review.coreboot.org/c/coreboot/+/31371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3d09e4eb23655825b7603f49f0bad31116ac6e1 Gerrit-Change-Number: 31371 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarein: Add power control for Sarien touchscreen
by EricR Lai (Code Review) 21 Dec '21

21 Dec '21

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32330 Change subject: mb/google/sarein: Add power control for Sarien touchscreen ...................................................................... mb/google/sarein: Add power control for Sarien touchscreen This change will save touchscreen power leakage 2-3mW in S0iX and increase T2 display time delay to meet display panel requirement. BUG=b:129899315 TEST= Measure touchscreen power from Sarien during S0iX Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I48419132ba734f20ad5cf484c2dda609570a6dd0 --- M src/mainboard/google/sarien/variants/sarien/devicetree.cb 1 file changed, 14 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/32330/1 diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index e4a92a9..bdd134a 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -311,10 +311,12 @@ register "generic.desc" = ""Touchscreen"" register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "generic.reset_delay_ms" = "10" register "generic.enable_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" - register "generic.enable_delay_ms" = "5" - register "generic.enable_off_delay_ms" = "100" + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + register "generic.enable_delay_ms" = "55" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x0" device i2c 10 on end @@ -324,10 +326,12 @@ register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "generic.reset_delay_ms" = "10" register "generic.enable_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" - register "generic.enable_delay_ms" = "5" - register "generic.enable_off_delay_ms" = "100" + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + register "generic.enable_delay_ms" = "55" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 10 on end @@ -337,8 +341,10 @@ register "desc" = ""Melfas Touchscreen"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" register "probed" = "1" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" - register "enable_delay_ms" = "5" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" + register "reset_delay_ms" = "10" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + register "enable_delay_ms" = "55" register "has_power_resource" = "1" device i2c 34 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/32330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I48419132ba734f20ad5cf484c2dda609570a6dd0 Gerrit-Change-Number: 32330 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: libpayload: Enable -Wconversion
by Patrick Georgi (Code Review) 19 Nov '21

19 Nov '21

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32185 Change subject: libpayload: Enable -Wconversion ...................................................................... libpayload: Enable -Wconversion Together with -Werror this ensures that no new conversion related issues can appear. BUG=b:111443775 BRANCH=none TEST=make junit.xml has no failed builds Change-Id: Idc37c50cae90d283bd6ec240dd7de3546485a9a9 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M payloads/libpayload/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/32185/1 diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index 7787762..ceac4ca 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -64,7 +64,7 @@ CFLAGS += -ffunction-sections -fdata-sections CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -CFLAGS += -Wstrict-aliasing -Wshadow -Werror +CFLAGS += -Wstrict-aliasing -Wshadow -Werror -Wconversion $(obj)/libpayload-config.h: $(KCONFIG_AUTOHEADER) cmp $@ $< 2>/dev/null || cp $< $@ -- To view, visit https://review.coreboot.org/c/coreboot/+/32185 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc37c50cae90d283bd6ec240dd7de3546485a9a9 Gerrit-Change-Number: 32185 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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