Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33361
Change subject: soc/intel/block/cpu: Add a MP init choice selection
......................................................................
soc/intel/block/cpu: Add a MP init choice selection
Add a choice to select the MP init method for clarity.
Change-Id: I2a7490948f729f1ae9fd2537bf6cbe9ada51f968
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/intel/common/block/cpu/Kconfig
1 file changed, 21 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/33361/1
diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig
index 8cc572d..6082ce3 100644
--- a/src/soc/intel/common/block/cpu/Kconfig
+++ b/src/soc/intel/common/block/cpu/Kconfig
@@ -51,18 +51,34 @@
ENHANCED NEM guarantees that modified data is always
kept in cache while clean data is replaced.
-config USE_INTEL_FSP_MP_INIT
+choice
+ prompt "Multiple Processor (MP) Initialization Options"
+ default MP_USE_COREBOOT_NATIVE_MP_INIT if !PLATFORM_USES_FSP2_1
+ default MP_USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI if PLATFORM_USES_FSP2_1
+
+config MP_USE_COREBOOT_NATIVE_MP_INIT
+ bool "Perform MP Initialization by coreboot"
+
+config MP_USE_INTEL_FSP_MP_INIT
bool "Perform MP Initialization by FSP"
- default n
+ select USE_INTEL_FSP_MP_INIT
+
+config MP_USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI
+ bool "Perform MP Initialization by FSP using coreboot MP PPI service"
+ depends on FSP_USES_MP_SERVICES_PPI
+ select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI
+
+endchoice
+
+config USE_INTEL_FSP_MP_INIT
+ bool
depends on !USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI
help
This option allows FSP to perform multiprocessor initialization.
config USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI
- bool "Perform MP Initialization by FSP using coreboot MP PPI service"
+ bool
depends on FSP_USES_MP_SERVICES_PPI
- default y if PLATFORM_USES_FSP2_1
- default n
help
This option allows FSP to make use of MP services PPI published by
coreboot to perform multiprocessor initialization.
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I2a7490948f729f1ae9fd2537bf6cbe9ada51f968
Gerrit-Change-Number: 33361
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-MessageType: newchange
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33555
Change subject: util/cbfstool/fit.c: Bail out when there are not enough FIT entries
......................................................................
util/cbfstool/fit.c: Bail out when there are not enough FIT entries
Bail out when there are not enough empty FIT enties to add all
microcode entries.
Change-Id: If86678a1eaaa0c5ff571f25bd6bfdb26ac93a946
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M util/cbfstool/fit.c
1 file changed, 8 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/33555/1
diff --git a/util/cbfstool/fit.c b/util/cbfstool/fit.c
index aeb1755..2fee9e3 100644
--- a/util/cbfstool/fit.c
+++ b/util/cbfstool/fit.c
@@ -238,7 +238,7 @@
static int parse_microcode_blob(struct cbfs_image *image,
struct cbfs_file *mcode_file,
struct microcode_entry *mcus,
- int total_entries, int *mcus_found)
+ int *mcus_found)
{
int num_mcus;
uint32_t current_offset;
@@ -272,9 +272,6 @@
file_length -= mcus[num_mcus].size;
num_mcus++;
- /* Reached limit of FIT entries. */
- if (num_mcus == total_entries)
- break;
if (file_length < sizeof(struct microcode_header))
break;
}
@@ -319,13 +316,18 @@
return 1;
}
- if (parse_microcode_blob(image, mcode_file, mcus, empty_entries,
- &mcus_found)) {
+ if (parse_microcode_blob(image, mcode_file, mcus, &mcus_found)) {
ERROR("Couldn't parse microcode blob.\n");
ret = 1;
goto out;
}
+ if (mcus_found > empty_entries) {
+ ERROR("Not enough empty FIT entries for all microcode update entries.\n");
+ ret = 1;
+ goto out;
+ }
+
add_microcodde_entries(fit, image, mcus_found, mcus, offset_fn, 0);
update_fit_checksum(fit);
--
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Gerrit-Branch: master
Gerrit-Change-Id: If86678a1eaaa0c5ff571f25bd6bfdb26ac93a946
Gerrit-Change-Number: 33555
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Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-MessageType: newchange
Erin Lo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34382 )
Change subject: WIP: mediatek/mt8183: Add SCP work support
......................................................................
WIP: mediatek/mt8183: Add SCP work support
Load SCP firmware to SCP's sram since buffer size is limited so load splitted binaries.
After SCP works done, disable it
Test=Build pass
Change-Id: I0801eac078aa9d6237142dcd92a3c3e9237a86ee
Signed-off-by: Erin Lo <erin.lo(a)mediatek.com>
---
M src/mainboard/google/kukui/Makefile.inc
M src/mainboard/google/kukui/romstage.c
M src/soc/mediatek/mt8183/Makefile.inc
M src/soc/mediatek/mt8183/include/soc/addressmap.h
A src/soc/mediatek/mt8183/include/soc/scp.h
A src/soc/mediatek/mt8183/scp.c
6 files changed, 123 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/34382/1
diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc
index a0556c1..f8a5bab 100644
--- a/src/mainboard/google/kukui/Makefile.inc
+++ b/src/mainboard/google/kukui/Makefile.inc
@@ -25,3 +25,18 @@
ramstage-y += mainboard.c
ramstage-y += memlayout.ld
ramstage-y += reset.c
+
+cbfs-files-y += scp_0.bin
+scp_0.bin-file := 3rdparty/blobs/mainboard/google/kukui/scp_0.bin
+scp_0.bin-type := raw
+scp_0.bin-compression := none
+
+cbfs-files-y += scp_1.bin
+scp_1.bin-file := 3rdparty/blobs/mainboard/google/kukui/scp_1.bin
+scp_1.bin-type := raw
+scp_1.bin-compression := none
+
+cbfs-files-y += scp_2.bin
+scp_2.bin-file := 3rdparty/blobs/mainboard/google/kukui/scp_2.bin
+scp_2.bin-type := raw
+scp_2.bin-compression := none
diff --git a/src/mainboard/google/kukui/romstage.c b/src/mainboard/google/kukui/romstage.c
index 1465243..cf3572d 100644
--- a/src/mainboard/google/kukui/romstage.c
+++ b/src/mainboard/google/kukui/romstage.c
@@ -19,7 +19,7 @@
#include <soc/mt6358.h>
#include <soc/pll.h>
#include <soc/rtc.h>
-
+#include <soc/scp.h>
#include "early_init.h"
void platform_romstage_main(void)
@@ -33,6 +33,7 @@
pmic_set_vsim2_cali(2700);
mt_pll_raise_ca53_freq(1989 * MHz);
rtc_boot();
+ scp_work();
mt_mem_init(get_sdram_config());
mtk_mmu_after_dram();
}
diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc
index d35a07e..0543552 100644
--- a/src/soc/mediatek/mt8183/Makefile.inc
+++ b/src/soc/mediatek/mt8183/Makefile.inc
@@ -35,6 +35,7 @@
romstage-y += ../common/pll.c pll.c
romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6358.c
romstage-y += ../common/rtc.c rtc.c
+romstage-y += scp.c
romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
romstage-y += ../common/timer.c
romstage-y += ../common/uart.c
diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h
index e9f80d1..affc776 100644
--- a/src/soc/mediatek/mt8183/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h
@@ -34,6 +34,9 @@
EMI_BASE = IO_PHYS + 0x00219000,
EMI_MPU_BASE = IO_PHYS + 0x00226000,
DRAMC_CH_BASE = IO_PHYS + 0x00228000,
+ SCP_SRAM_BASE = IO_PHYS + 0x00500000,
+ SCP_CFG_BASE = IO_PHYS + 0x005C0000,
+ SCP_CLK_CTRL_BASE = IO_PHYS + 0x005C4000,
AUXADC_BASE = IO_PHYS + 0x01001000,
UART0_BASE = IO_PHYS + 0x01002000,
SPI0_BASE = IO_PHYS + 0x0100A000,
diff --git a/src/soc/mediatek/mt8183/include/soc/scp.h b/src/soc/mediatek/mt8183/include/soc/scp.h
new file mode 100644
index 0000000..a3003bd
--- /dev/null
+++ b/src/soc/mediatek/mt8183/include/soc/scp.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_MEDIATEK_MT8183_SCP_H
+#define SOC_MEDIATEK_MT8183_SCP_H
+
+#include <soc/addressmap.h>
+#include <types.h>
+
+struct mt8183_scp_regs {
+ u32 sw_rstn;
+ u32 reserved[19];
+ u32 gpr0;
+};
+
+struct mt8183_scp_clk_ctrl_regs {
+ u32 reserved[11];
+ u32 sram_pdn;
+};
+
+static struct mt8183_scp_regs *const mt8183_scp = (void *)SCP_CFG_BASE;
+static struct mt8183_scp_clk_ctrl_regs *const mt8183_scp_clk_ctrl = (void *)SCP_CLK_CTRL_BASE;
+void scp_work(void);
+#endif /* SOC_MEDIATEK_MT8183_SCP_H */
diff --git a/src/soc/mediatek/mt8183/scp.c b/src/soc/mediatek/mt8183/scp.c
new file mode 100644
index 0000000..150eeba
--- /dev/null
+++ b/src/soc/mediatek/mt8183/scp.c
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/barrier.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <arch/mmio.h>
+#include <soc/scp.h>
+#include <string.h>
+
+#define BUF_SIZE (40 * KiB)
+static uint8_t scp_bin[BUF_SIZE] __aligned(8);
+
+void scp_work(void)
+{
+ size_t fw_size;
+
+ write32(&mt8183_scp_clk_ctrl->sram_pdn, 0x0);
+ mb();
+
+ fw_size = cbfs_boot_load_file("scp_0.bin",
+ scp_bin,
+ sizeof(scp_bin),
+ CBFS_TYPE_RAW);
+ if (fw_size == 0)
+ die("SCP file :scp_0.bin not found.");
+ memcpy((void *)SCP_SRAM_BASE + 0x0, scp_bin, fw_size);
+
+ fw_size = cbfs_boot_load_file("scp_1.bin",
+ scp_bin,
+ sizeof(scp_bin),
+ CBFS_TYPE_RAW);
+ memcpy((void *)SCP_SRAM_BASE + BUF_SIZE, scp_bin, fw_size);
+ if (fw_size == 0)
+ die("SCP file :scp_1.bin not found.");
+
+ fw_size = cbfs_boot_load_file("scp_2.bin",
+ scp_bin,
+ sizeof(scp_bin),
+ CBFS_TYPE_RAW);
+ if (fw_size == 0)
+ die("SCP file :scp_2.bin not found.");
+ memcpy((void *)SCP_SRAM_BASE + BUF_SIZE*2, scp_bin, fw_size);
+
+
+ /* Memory barrier to ensure that all fw code is loaded
+ before we release the reset pin. */
+ mb();
+ write32(&mt8183_scp->sw_rstn, 0x1);
+ while (read32(&mt8183_scp->gpr0) != 0xaaaa){}
+ mb();
+ write32(&mt8183_scp->sw_rstn, 0x0);
+ printk(BIOS_DEBUG, "scp finished \n");
+}
--
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Gerrit-Change-Id: I0801eac078aa9d6237142dcd92a3c3e9237a86ee
Gerrit-Change-Number: 34382
Gerrit-PatchSet: 1
Gerrit-Owner: Erin Lo <erin.lo(a)mediatek.com>
Gerrit-MessageType: newchange
Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31356
Change subject: WIP: libpayload: add initial support for RISC-V
......................................................................
WIP: libpayload: add initial support for RISC-V
Parse fdt provided by a2 and extract coreboot tables from it.
Change-Id: I91df02069a0f8fd8771f73de0e866e9cea05cded
Signed-off-by: Philipp Hug <philipp(a)hug.cx>
---
M payloads/libpayload/Kconfig
M payloads/libpayload/Makefile
M payloads/libpayload/Makefile.inc
A payloads/libpayload/arch/riscv/Kconfig
A payloads/libpayload/arch/riscv/Makefile.inc
A payloads/libpayload/arch/riscv/coreboot.c
A payloads/libpayload/arch/riscv/head.S
A payloads/libpayload/arch/riscv/libpayload.ldscript
A payloads/libpayload/arch/riscv/main.c
A payloads/libpayload/arch/riscv/sysinfo.c
A payloads/libpayload/arch/riscv/timer.c
A payloads/libpayload/arch/riscv/util.S
A payloads/libpayload/arch/riscv/virtual.c
M payloads/libpayload/bin/lpgcc
A payloads/libpayload/configs/config.riscv
A payloads/libpayload/configs/defconfig-riscv
A payloads/libpayload/include/riscv/arch/asm.h
A payloads/libpayload/include/riscv/arch/barrier.h
A payloads/libpayload/include/riscv/arch/cache.h
A payloads/libpayload/include/riscv/arch/io.h
A payloads/libpayload/include/riscv/arch/types.h
A payloads/libpayload/include/riscv/arch/virtual.h
22 files changed, 1,094 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/31356/1
diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig
index 5bfbd54..846280d 100644
--- a/payloads/libpayload/Kconfig
+++ b/payloads/libpayload/Kconfig
@@ -119,6 +119,11 @@
help
Support the MIPS architecture
+config ARCH_RISCV
+ bool "RISCV"
+ help
+ Support the RISCV architecture
+
endchoice
config MULTIBOOT
@@ -148,12 +153,13 @@
default 0x04000000 if ARCH_ARM
default 0x80100000 if ARCH_ARM64
default 0x00000000 if ARCH_MIPS
+ default 0x81000000 if ARCH_RISCV
default 0x00100000 if ARCH_X86
help
This is the base address for the payload.
If unsure, set to 0x00100000 on x86, 0x00000000 on MIPS,
- 0x04000000 on ARM or 0x80100000 on ARM64.
+ 0x04000000 on ARM or 0x80100000 on ARM64 or 0x81000000 on RISCV.
endmenu
@@ -451,4 +457,5 @@
source "arch/arm/Kconfig"
source "arch/arm64/Kconfig"
source "arch/mips/Kconfig"
+source "arch/riscv/Kconfig"
source "arch/x86/Kconfig"
diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile
index 1a0acf1..e01115e 100644
--- a/payloads/libpayload/Makefile
+++ b/payloads/libpayload/Makefile
@@ -96,6 +96,7 @@
ARCHDIR-$(CONFIG_LP_ARCH_ARM) := arm
ARCHDIR-$(CONFIG_LP_ARCH_ARM64) := arm64
ARCHDIR-$(CONFIG_LP_ARCH_MIPS) := mips
+ARCHDIR-$(CONFIG_LP_ARCH_RISCV) := riscv
ARCHDIR-$(CONFIG_LP_ARCH_X86) := x86
ARCH-y := $(ARCHDIR-y)
@@ -105,6 +106,7 @@
ARCH-$(CONFIG_LP_ARCH_ARM) := arm
ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64
ARCH-$(CONFIG_LP_ARCH_X86) := x86_32
+ARCH-$(CONFIG_LP_ARCH_RISCV) := riscv
ARCH-$(CONFIG_LP_ARCH_MIPS) := mips
# Three cases where we don't need fully populated $(obj) lists:
diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc
index 052a3f0..8ea0810 100644
--- a/payloads/libpayload/Makefile.inc
+++ b/payloads/libpayload/Makefile.inc
@@ -34,6 +34,7 @@
ARCHDIR-$(CONFIG_LP_ARCH_ARM) := arm
ARCHDIR-$(CONFIG_LP_ARCH_ARM64) := arm64
ARCHDIR-$(CONFIG_LP_ARCH_MIPS) := mips
+ARCHDIR-$(CONFIG_LP_ARCH_RISCV) := riscv
ARCHDIR-$(CONFIG_LP_ARCH_X86) := x86
DESTDIR ?= install
@@ -61,12 +62,15 @@
INCLUDES := -Iinclude -Iinclude/$(ARCHDIR-y) -I$(obj) -include include/kconfig.h
+ARCHCFLAGS-$(CONFIG_LP_ARCH_RISCV) := -mcmodel=medany
+
CFLAGS += $(EXTRA_CFLAGS) $(INCLUDES) -Os -pipe -nostdinc -ggdb3
CFLAGS += -nostdlib -fno-builtin -ffreestanding -fomit-frame-pointer
CFLAGS += -ffunction-sections -fdata-sections
CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes
CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs
CFLAGS += -Wstrict-aliasing -Wshadow -Werror
+CFLAGS += $(ARCHCFLAGS-y)
$(obj)/libpayload-config.h: $(KCONFIG_AUTOHEADER)
cmp $@ $< 2>/dev/null || cp $< $@
diff --git a/payloads/libpayload/arch/riscv/Kconfig b/payloads/libpayload/arch/riscv/Kconfig
new file mode 100644
index 0000000..6352ff0
--- /dev/null
+++ b/payloads/libpayload/arch/riscv/Kconfig
@@ -0,0 +1,37 @@
+##
+## This file is part of the libpayload project.
+##
+## Copyright (c) 2012 Google Inc.
+##
+## Redistribution and use in source and binary forms, with or without
+## modification, are permitted provided that the following conditions
+## are met:
+## 1. Redistributions of source code must retain the above copyright
+## notice, this list of conditions and the following disclaimer.
+## 2. Redistributions in binary form must reproduce the above copyright
+## notice, this list of conditions and the following disclaimer in the
+## documentation and/or other materials provided with the distribution.
+## 3. The name of the author may not be used to endorse or promote products
+## derived from this software without specific prior written permission.
+##
+## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+## SUCH DAMAGE.
+##
+
+if ARCH_RISCV
+
+config ARCH_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select LITTLE_ENDIAN
+ select FDT
+
+endif
diff --git a/payloads/libpayload/arch/riscv/Makefile.inc b/payloads/libpayload/arch/riscv/Makefile.inc
new file mode 100644
index 0000000..01d6bd8
--- /dev/null
+++ b/payloads/libpayload/arch/riscv/Makefile.inc
@@ -0,0 +1,34 @@
+##
+## This file is part of the libpayload project.
+##
+## Copyright (C) 2008 Advanced Micro Devices, Inc.
+##
+## Redistribution and use in source and binary forms, with or without
+## modification, are permitted provided that the following conditions
+## are met:
+## 1. Redistributions of source code must retain the above copyright
+## notice, this list of conditions and the following disclaimer.
+## 2. Redistributions in binary form must reproduce the above copyright
+## notice, this list of conditions and the following disclaimer in the
+## documentation and/or other materials provided with the distribution.
+## 3. The name of the author may not be used to endorse or promote products
+## derived from this software without specific prior written permission.
+##
+## THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+## ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+## ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+## OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+## HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+## LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+## OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+## SUCH DAMAGE.
+##
+
+head.o-y += head.S
+
+libc-y += main.c sysinfo.c
+libc-y += timer.c coreboot.c util.S
+libc-y += virtual.c
diff --git a/payloads/libpayload/arch/riscv/coreboot.c b/payloads/libpayload/arch/riscv/coreboot.c
new file mode 100644
index 0000000..ea21c51
--- /dev/null
+++ b/payloads/libpayload/arch/riscv/coreboot.c
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2019 Philipp Hug <philipp(a)hug.cx>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <libpayload-config.h>
+#include <libpayload.h>
+#include <coreboot_tables.h>
+#include <libfdt.h>
+
+/* This pointer gets set in head.S and is passed in from coreboot. */
+void *fdt_ptr;
+int hart_id;
+
+/* == Architecture specific == */
+
+int cb_parse_arch_specific(struct cb_record *rec, struct sysinfo_t *info)
+{
+ switch (rec->tag) {
+ default:
+ return 0;
+ }
+ return 1;
+}
+
+int get_coreboot_info(struct sysinfo_t *info)
+{
+ void *cb_header_ptr = get_cb_header_ptr();
+ if (cb_header_ptr == NULL)
+ return 1;
+ return cb_parse_header(cb_header_ptr, 1, info);
+}
+
+void *get_cb_header_ptr(void)
+{
+ int offset;
+ int len;
+ const struct fdt_property *prop;
+
+ /*
+ * coreboot tables are provides within the fdt which was passes as
+ * a2 to the entry point
+ */
+
+ if (fdt_check_header(fdt_ptr) != 0) {
+ printf("fdt: invalid header\n");
+ return NULL;
+ }
+
+ // search for coreboot node
+ offset = fdt_node_offset_by_compatible(fdt_ptr, -1, "coreboot");
+ if (offset < 0) {
+ printf("fdt: coreboot node not found\n");
+ return NULL;
+ }
+
+ /*
+ * get reg property and extract the pointer to the coreboot tables
+ * TODO: parse cell info and fix for RV32
+ */
+ prop = fdt_get_property(fdt_ptr, offset, "reg", &len);
+ if (len != 32) {
+ printf("fdt: invalid reg property\n");
+ return NULL;
+ }
+
+ return (void *)fdt64_ld((fdt64_t *)prop->data);
+}
diff --git a/payloads/libpayload/arch/riscv/head.S b/payloads/libpayload/arch/riscv/head.S
new file mode 100644
index 0000000..c46b20b
--- /dev/null
+++ b/payloads/libpayload/arch/riscv/head.S
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2019 Philipp Hug <philipp(a)hug.cx>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <arch/asm.h>
+
+/*
+ * Our entry point
+ */
+ENTRY(_entry)
+
+ /* Save off hart id in a0 */
+ la t0, hart_id
+ sd a0, 0(t0)
+
+ /* Save off device tree pointer in a1 */
+ la t0, fdt_ptr
+ sd a1, 0(t0)
+
+ /*
+ * busy-loop for harts != 0
+ * TODO: add support hart > 0
+ */
+ li a3, 0
+ beq a0, a3, _hart_zero
+_hart_loop:
+ j _hart_loop
+_hart_zero:
+
+ /*
+ * Setup new stack
+ * TODO, use stack per hart
+ */
+ la t0, _stack
+ li t1, 0xDEADBEEF
+ sd t1, 0(t0)
+ add sp, t0, 0
+
+ /* Let's rock. */
+ tail start_main
+
+ENDPROC(_entry)
+
+.align 4
+1:
+.quad fdt_ptr
+2:
+.quad _stack
diff --git a/payloads/libpayload/arch/riscv/libpayload.ldscript b/payloads/libpayload/arch/riscv/libpayload.ldscript
new file mode 100644
index 0000000..1929549
--- /dev/null
+++ b/payloads/libpayload/arch/riscv/libpayload.ldscript
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+OUTPUT_FORMAT("elf64-littleriscv", "elf64-littleriscv","elf64-littleriscv")
+OUTPUT_ARCH(riscv)
+
+ENTRY(_entry)
+
+SECTIONS
+{
+ . = CONFIG_LP_BASE_ADDRESS;
+
+ . = ALIGN(16);
+ _start = .;
+
+ .text : {
+ *(.text._entry)
+ *(.text)
+ *(.text.*)
+ }
+
+ .rodata : {
+ *(.rodata)
+ *(.rodata.*)
+ }
+
+ .data : {
+ *(.data)
+ *(.data.*)
+ }
+
+ _edata = .;
+
+ .bss : {
+ *(.sbss)
+ *(.sbss.*)
+ *(.bss)
+ *(.bss.*)
+ *(COMMON)
+
+ /* Stack and heap */
+
+ . = ALIGN(16);
+ _heap = .;
+ . += CONFIG_LP_HEAP_SIZE;
+ . = ALIGN(16);
+ _eheap = .;
+
+ _estack = .;
+ . += CONFIG_LP_STACK_SIZE;
+ . = ALIGN(16);
+ _stack = .;
+ }
+ .debug : {
+ *(.debug)
+ }
+
+ _end = .;
+
+ /DISCARD/ : {
+ *(.comment)
+ *(.note*)
+ }
+}
diff --git a/payloads/libpayload/arch/riscv/main.c b/payloads/libpayload/arch/riscv/main.c
new file mode 100644
index 0000000..83fb841
--- /dev/null
+++ b/payloads/libpayload/arch/riscv/main.c
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <libpayload.h>
+
+unsigned int main_argc; /**< The argc value to pass to main() */
+
+/** The argv value to pass to main() */
+char *main_argv[MAX_ARGC_COUNT];
+
+/**
+ * This is our C entry function - set up the system
+ * and jump into the payload entry point.
+ */
+void start_main(void);
+void start_main(void)
+{
+ extern int main(int argc, char **argv);
+
+ /* Gather system information. */
+ lib_get_sysinfo();
+
+#if !IS_ENABLED(CONFIG_LP_SKIP_CONSOLE_INIT)
+ console_init();
+#endif
+
+ // TODO: implement exceptions
+ // exception_init();
+
+ /*
+ * Any other system init that has to happen before the
+ * user gets control goes here.
+ */
+
+ /*
+ * Go to the entry point.
+ * In the future we may care about the return value.
+ */
+
+ (void)main(main_argc, (main_argc != 0) ? main_argv : NULL);
+
+ /*
+ * Returning here will go to the _leave function to return
+ * us to the original context.
+ */
+}
diff --git a/payloads/libpayload/arch/riscv/sysinfo.c b/payloads/libpayload/arch/riscv/sysinfo.c
new file mode 100644
index 0000000..575b7da
--- /dev/null
+++ b/payloads/libpayload/arch/riscv/sysinfo.c
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <libpayload-config.h>
+#include <libpayload.h>
+#include <coreboot_tables.h>
+
+/**
+ * This is a global structure that is used through the library - we set it
+ * up initially with some dummy values - hopefully they will be overridden.
+ * Also set some defaults for the console in case the fdt is messed up.
+ */
+struct cb_serial serial_info = {
+ .baseaddr = 0x10000000,
+ .type = CB_SERIAL_TYPE_MEMORY_MAPPED,
+ .regwidth = 1,
+};
+
+struct sysinfo_t lib_sysinfo = {
+ .cpu_khz = 1000,
+ .serial = &serial_info,
+};
+
+int lib_get_sysinfo(void)
+{
+ int ret;
+
+ /* Get the CPU speed (for delays). */
+ lib_sysinfo.cpu_khz = get_cpu_speed();
+
+ /* Get information from the coreboot tables,
+ * if they exist */
+
+ ret = get_coreboot_info(&lib_sysinfo);
+
+ if (!lib_sysinfo.n_memranges) {
+ /* If we can't get a good memory range, use the default. */
+ lib_sysinfo.n_memranges = 1;
+
+ lib_sysinfo.memrange[0].base = 0x80000000u;
+ lib_sysinfo.memrange[0].size = 1024 * 1024;
+ lib_sysinfo.memrange[0].type = CB_MEM_RAM;
+ }
+
+ return ret;
+}
+
+void lib_sysinfo_get_memranges(struct memrange **ranges,
+ uint64_t *nranges)
+{
+ *ranges = &lib_sysinfo.memrange[0];
+ *nranges = lib_sysinfo.n_memranges;
+}
diff --git a/payloads/libpayload/arch/riscv/timer.c b/payloads/libpayload/arch/riscv/timer.c
new file mode 100644
index 0000000..d233ddc
--- /dev/null
+++ b/payloads/libpayload/arch/riscv/timer.c
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/**
+ * @file riscv/timer.c
+ * RISC-V specific timer routines
+ */
+
+#include <libpayload.h>
+
+/**
+ * @ingroup arch
+ * Global variable containing the speed of the processor in KHz.
+ */
+u32 cpu_khz;
+
+/**
+ * Calculate the speed of the processor for use in delays.
+ *
+ * @return The CPU speed in kHz.
+ */
+unsigned int get_cpu_speed(void)
+{
+ /* FIXME */
+ cpu_khz = 1000000U;
+
+ return cpu_khz;
+}
diff --git a/payloads/libpayload/arch/riscv/util.S b/payloads/libpayload/arch/riscv/util.S
new file mode 100644
index 0000000..dde2099
--- /dev/null
+++ b/payloads/libpayload/arch/riscv/util.S
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2012 Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <arch/asm.h>
+
+/* This function puts the system into a halt. */
+ENTRY(halt)
+ j halt
+ENDPROC(halt)
diff --git a/payloads/libpayload/arch/riscv/virtual.c b/payloads/libpayload/arch/riscv/virtual.c
new file mode 100644
index 0000000..c3f4aa7
--- /dev/null
+++ b/payloads/libpayload/arch/riscv/virtual.c
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <libpayload.h>
+#include <assert.h>
+#include <die.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <arch/cache.h>
+#include <arch/virtual.h>
+#include <arch/io.h>
+
+unsigned long virtual_offset = 0;
+extern char _end[];
diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc
index b3ef342..2faf113 100755
--- a/payloads/libpayload/bin/lpgcc
+++ b/payloads/libpayload/bin/lpgcc
@@ -86,6 +86,12 @@
_ARCHEXTRA=""
_ARCH=mips
fi
+if [ "$CONFIG_LP_ARCH_RISCV" = "y" ]; then
+ _ARCHINCDIR=$_INCDIR/riscv
+ _ARCHLIBDIR=$_LIBDIR/riscv
+ _ARCHEXTRA=""
+ _ARCH=riscv
+fi
if [ "$CONFIG_LP_ARCH_X86" = "y" ]; then
_ARCHINCDIR=$_INCDIR/x86
_ARCHLIBDIR=$_LIBDIR/x86
diff --git a/payloads/libpayload/configs/config.riscv b/payloads/libpayload/configs/config.riscv
new file mode 100644
index 0000000..7982b4a
--- /dev/null
+++ b/payloads/libpayload/configs/config.riscv
@@ -0,0 +1,81 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Libpayload Configuration
+#
+
+#
+# Generic Options
+#
+# CONFIG_LP_GPL is not set
+# CONFIG_LP_EXPERIMENTAL is not set
+# CONFIG_LP_DEVELOPER is not set
+# CONFIG_LP_CHROMEOS is not set
+CONFIG_LP_COMPILER_GCC=y
+# CONFIG_LP_COMPILER_LLVM_CLANG is not set
+# CONFIG_LP_MEMMAP_RAM_ONLY is not set
+
+#
+# Architecture Options
+#
+# CONFIG_LP_ARCH_ARM is not set
+# CONFIG_LP_ARCH_X86 is not set
+# CONFIG_LP_ARCH_ARM64 is not set
+# CONFIG_LP_ARCH_MIPS is not set
+CONFIG_LP_ARCH_RISCV=y
+CONFIG_LP_HEAP_SIZE=131072
+CONFIG_LP_STACK_SIZE=16384
+CONFIG_LP_BASE_ADDRESS=0x80100000
+
+#
+# Standard Libraries
+#
+CONFIG_LP_LIBC=y
+# CONFIG_LP_CURSES is not set
+CONFIG_LP_CBFS=y
+CONFIG_LP_LZMA=y
+CONFIG_LP_LZ4=y
+
+#
+# Console Options
+#
+# CONFIG_LP_SKIP_CONSOLE_INIT is not set
+CONFIG_LP_CBMEM_CONSOLE=y
+# CONFIG_LP_SERIAL_CONSOLE is not set
+CONFIG_LP_VIDEO_CONSOLE=y
+# CONFIG_LP_COREBOOT_VIDEO_CONSOLE is not set
+# CONFIG_LP_PC_I8042 is not set
+# CONFIG_LP_PC_MOUSE is not set
+# CONFIG_LP_PC_KEYBOARD is not set
+
+#
+# Drivers
+#
+# CONFIG_LP_MOUSE_CURSOR is not set
+# CONFIG_LP_RTC_PORT_EXTENDED_VIA is not set
+CONFIG_LP_TIMER_NONE=y
+# CONFIG_LP_TIMER_MCT is not set
+# CONFIG_LP_TIMER_TEGRA_1US is not set
+# CONFIG_LP_TIMER_IPQ806X is not set
+# CONFIG_LP_TIMER_ARMADA38X is not set
+# CONFIG_LP_TIMER_IPQ40XX is not set
+# CONFIG_LP_TIMER_ARM64_ARCH is not set
+# CONFIG_LP_TIMER_RK3288 is not set
+# CONFIG_LP_TIMER_RK3399 is not set
+# CONFIG_LP_TIMER_CYGNUS is not set
+# CONFIG_LP_TIMER_IMG_PISTACHIO is not set
+# CONFIG_LP_TIMER_MTK is not set
+# CONFIG_LP_TIMER_MVMAP2315 is not set
+CONFIG_LP_TIMER_GENERIC_HZ=100000
+CONFIG_LP_TIMER_GENERIC_REG=0x0
+CONFIG_LP_TIMER_GENERIC_HIGH_REG=0x0
+CONFIG_LP_STORAGE=y
+# CONFIG_LP_STORAGE_64BIT_LBA is not set
+CONFIG_LP_STORAGE_ATA=y
+CONFIG_LP_STORAGE_ATAPI=y
+# CONFIG_LP_USB is not set
+# CONFIG_LP_USB_GEN_HUB is not set
+# CONFIG_LP_UDC is not set
+# CONFIG_LP_BIG_ENDIAN is not set
+CONFIG_LP_LITTLE_ENDIAN=y
+# CONFIG_LP_IO_ADDRESS_SPACE is not set
+CONFIG_LP_ARCH_SPECIFIC_OPTIONS=y
diff --git a/payloads/libpayload/configs/defconfig-riscv b/payloads/libpayload/configs/defconfig-riscv
new file mode 100644
index 0000000..2ce2bc5
--- /dev/null
+++ b/payloads/libpayload/configs/defconfig-riscv
@@ -0,0 +1,3 @@
+CONFIG_LP_ARCH_RISCV=y
+CONFIG_LP_TINYCURSES=n
+CONFIG_LP_USB=n
diff --git a/payloads/libpayload/include/riscv/arch/asm.h b/payloads/libpayload/include/riscv/arch/asm.h
new file mode 100644
index 0000000..842fb0d
--- /dev/null
+++ b/payloads/libpayload/include/riscv/arch/asm.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ */
+
+#ifndef __RISCV_ASM_H
+#define __RISCV_ASM_H
+
+# define RISCV(x...) x
+# define W(instr) instr
+
+#define ALIGN .align 2
+
+#define ENDPROC(name) \
+ .type name, %function; \
+ END(name)
+
+#define ENTRY(name) \
+ .section .text.name, "ax", %progbits; \
+ .global name; \
+ ALIGN; \
+ name:
+
+#define END(name) \
+ .size name, .-name
+
+#endif /* __RISCV_ASM_H */
diff --git a/payloads/libpayload/include/riscv/arch/barrier.h b/payloads/libpayload/include/riscv/arch/barrier.h
new file mode 100644
index 0000000..0b55df6
--- /dev/null
+++ b/payloads/libpayload/include/riscv/arch/barrier.h
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2014 Google Inc.
+ * Copyright (C) 2003-2004 Olivier Houchard
+ * Copyright (C) 1994-1997 Mark Brinicombe
+ * Copyright (C) 1994 Brini
+ * All rights reserved.
+ *
+ * This code is derived from software written for Brini by Mark Brinicombe
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#ifndef __ARCH_BARRIER_H_
+#define __ARCH_BARRIER_H__
+
+#include <arch/cache.h>
+
+/*
+ * Description of different memory barriers introduced:
+ *
+ * Memory barrier(mb) - Guarantees that all memory accesses specified before the
+ * barrier will happen before all memory accesses specified after the barrier
+ *
+ * Read memory barrier (rmb) - Guarantees that all read memory accesses
+ * specified before the barrier will happen before all read memory accesses
+ * specified after the barrier
+ *
+ * Write memory barrier (wmb) - Guarantees that all write memory accesses
+ * specified before the barrier will happen before all write memory accesses
+ * specified after the barrier
+ */
+
+#define mb()
+#define rmb()
+#define wmb()
+
+#endif /* __ARCH_BARRIER_H__ */
diff --git a/payloads/libpayload/include/riscv/arch/cache.h b/payloads/libpayload/include/riscv/arch/cache.h
new file mode 100644
index 0000000..820bee9
--- /dev/null
+++ b/payloads/libpayload/include/riscv/arch/cache.h
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * cache.h: Cache maintenance API for RISCV
+ */
+
+#ifndef RISCV_CACHE_H
+#define RISCV_CACHE_H
+
+#include <stddef.h>
+#include <stdint.h>
+
+/*
+ * Cache maintenance API
+ */
+
+/* dcache clean and invalidate all (on current level given by CCSELR) */
+void dcache_clean_invalidate_all(void);
+
+/* dcache clean by virtual address to PoC */
+void dcache_clean_by_mva(void const *addr, size_t len);
+
+/* dcache clean and invalidate by virtual address to PoC */
+void dcache_clean_invalidate_by_mva(void const *addr, size_t len);
+
+/* dcache invalidate by virtual address to PoC */
+void dcache_invalidate_by_mva(void const *addr, size_t len);
+
+void dcache_clean_all(void);
+
+/* dcache invalidate all (on current level given by CCSELR) */
+void dcache_invalidate_all(void);
+
+/* returns number of bytes per cache line */
+unsigned int dcache_line_bytes(void);
+
+/* dcache and MMU disable */
+void dcache_mmu_disable(void);
+
+/* dcache and MMU enable */
+void dcache_mmu_enable(void);
+
+/* perform all icache/dcache maintenance needed after loading new code */
+void cache_sync_instructions(void);
+
+/* Ensure that loaded program segment is synced back from cache to PoC */
+void arch_program_segment_loaded(void const *addr, size_t len);
+
+/* tlb invalidate all */
+void tlb_invalidate_all(void);
+
+/* Invalidate all of the instruction cache for PE to PoU. */
+static inline void icache_invalidate_all(void)
+{
+ return;
+}
+
+#endif /* RISCV_CACHE_H */
diff --git a/payloads/libpayload/include/riscv/arch/io.h b/payloads/libpayload/include/riscv/arch/io.h
new file mode 100644
index 0000000..8413b61
--- /dev/null
+++ b/payloads/libpayload/include/riscv/arch/io.h
@@ -0,0 +1,106 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _ARCH_IO_H
+#define _ARCH_IO_H
+
+#include <stdint.h>
+#include <arch/cache.h>
+//#include <arch/lib_helpers.h>
+
+/*
+ * readb/w/l writeb/w/l are deprecated. use read8/16/32 and write8/16/32
+ * instead for future development.
+ *
+ * TODO: make the existing code use read8/16/32 and write8/16/32 then remove
+ * readb/w/l and writeb/w/l.
+ */
+
+static inline uint8_t readb(volatile const void *_a)
+{
+ return *(volatile const uint8_t *)_a;
+}
+
+static inline uint16_t readw(volatile const void *_a)
+{
+ return *(volatile const uint16_t *)_a;
+}
+
+static inline uint32_t readl(volatile const void *_a)
+{
+ return *(volatile const uint32_t *)_a;
+}
+
+static inline void writeb(uint8_t _v, volatile void *_a)
+{
+ *(volatile uint8_t *)_a = _v;
+}
+
+static inline void writew(uint16_t _v, volatile void *_a)
+{
+ *(volatile uint16_t *)_a = _v;
+}
+
+static inline void writel(uint32_t _v, volatile void *_a)
+{
+ *(volatile uint32_t *)_a = _v;
+}
+
+static inline uint8_t read8(const void *addr)
+{
+ return *(volatile uint8_t *)addr;
+}
+
+static inline uint16_t read16(const void *addr)
+{
+ return *(volatile uint16_t *)addr;
+}
+
+static inline uint32_t read32(const void *addr)
+{
+ return *(volatile uint32_t *)addr;
+}
+
+static inline void write8(void *addr, uint8_t val)
+{
+ *(volatile uint8_t *)addr = val;
+}
+
+static inline void write16(void *addr, uint16_t val)
+{
+ *(volatile uint16_t *)addr = val;
+}
+
+static inline void write32(void *addr, uint32_t val)
+{
+ *(volatile uint32_t *)addr = val;
+}
+
+#endif
diff --git a/payloads/libpayload/include/riscv/arch/types.h b/payloads/libpayload/include/riscv/arch/types.h
new file mode 100644
index 0000000..1bd815b
--- /dev/null
+++ b/payloads/libpayload/include/riscv/arch/types.h
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2007 Uwe Hermann <uwe(a)hermann-uwe.de>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _ARCH_TYPES_H
+#define _ARCH_TYPES_H
+
+typedef unsigned char uint8_t;
+typedef unsigned char u8;
+typedef signed char int8_t;
+typedef signed char s8;
+
+typedef unsigned short uint16_t;
+typedef unsigned short u16;
+typedef signed short int16_t;
+typedef signed short s16;
+
+typedef unsigned int uint32_t;
+typedef unsigned int u32;
+typedef signed int int32_t;
+typedef signed int s32;
+
+typedef unsigned long long uint64_t;
+typedef unsigned long long u64;
+typedef signed long long int64_t;
+typedef signed long long s64;
+
+typedef long time_t;
+typedef long suseconds_t;
+
+#ifndef NULL
+#define NULL ((void *)0)
+#endif
+
+#endif
diff --git a/payloads/libpayload/include/riscv/arch/virtual.h b/payloads/libpayload/include/riscv/arch/virtual.h
new file mode 100644
index 0000000..dac3480
--- /dev/null
+++ b/payloads/libpayload/include/riscv/arch/virtual.h
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#ifndef _ARCH_VIRTUAL_H
+#define _ARCH_VIRTUAL_H
+
+extern unsigned long virtual_offset;
+
+#define virt_to_phys(virt) ((unsigned long)(virt) + virtual_offset)
+#define phys_to_virt(phys) ((void *)((unsigned long)(phys)-virtual_offset))
+
+#define virt_to_bus(addr) virt_to_phys(addr)
+#define bus_to_virt(addr) phys_to_virt(addr)
+
+#endif
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I91df02069a0f8fd8771f73de0e866e9cea05cded
Gerrit-Change-Number: 31356
Gerrit-PatchSet: 1
Gerrit-Owner: Philipp Hug <philipp(a)hug.cx>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx>
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Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32253
Change subject: Documentation: Document PMH known registers
......................................................................
Documentation: Document PMH known registers
Document what is known of Lenovo's PMH.
Change-Id: I1891a6370123d9ee29d9e37e4b7b78b677343aed
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M Documentation/mainboard/index.md
A Documentation/mainboard/lenovo/pmh.md
2 files changed, 70 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/32253/1
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index d94c23e..adfe877 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -54,6 +54,7 @@
- [Hardware Maintenance Manual of ThinkPads](lenovo/thinkpad_hmm.md)
- [T4xx common](lenovo/t4xx_series.md)
- [X2xx common](lenovo/x2xx_series.md)
+- [PMH](lenovo/pmh.md)
### Sandy Bridge series
diff --git a/Documentation/mainboard/lenovo/pmh.md b/Documentation/mainboard/lenovo/pmh.md
new file mode 100644
index 0000000..06c595d
--- /dev/null
+++ b/Documentation/mainboard/lenovo/pmh.md
@@ -0,0 +1,69 @@
+# Lenovo's Power Management Hub
+
+The *Power Management Hub* or *PMH* originally was a CPLD connected to the EC
+to controll power rails and reset lines on the lenovo mainboard.
+Starting with Ivy Bridge series, the CPLD was removed and an EC with higher
+pincount does the same job. The IO space to configure the PMH is still
+the same.
+
+## PMH access
+
+The PMH register can be accessed using the IO region:
+
+ IO region address: 0x15e0
+ IO region size: 16
+
+The IO region has the following layout:
+
+```eval_rst
++-------------------+---------------------------------------+
+| Offset | Register function |
++-------------------+---------------------------------------+
+| 0xc | ADDR_L: Low address into PMH space |
++-------------------+---------------------------------------+
+| 0xd | ADDR_H: High address into PMH space |
++-------------------+---------------------------------------+
+| 0xe | DATA: The data to read/write in PMH |
++-------------------+---------------------------------------+
+```
+
+The PMH register space allows to access 512bytes.
+The following registers are known:
+
+```eval_rst
++-------------------+---------------------------------------+
+| Offset | Register function |
++-------------------+---------------------------------------+
+| 0x50 | BIT3: dGPU power enable |
+| +---------------------------------------+
+| | BIT5: Backlight enable |
+| +---------------------------------------+
+| | BIT7: dGPU !reset |
++-------------------+---------------------------------------+
+| 0x51 | BIT0: Trackpoint enable |
+| +---------------------------------------+
+| | BIT2: Touchpad enable |
++-------------------+---------------------------------------+
+| 0x60 | BIT3: Dock event enable |
++-------------------+---------------------------------------+
+| 0x62 | BIT0: Ultrabay power enable |
++-------------------+---------------------------------------+
+| 0xc2 | ID: ID of PMH |
++-------------------+---------------------------------------+
+| 0xc3 | REV: Revision of PMH |
++-------------------+---------------------------------------+
+```
+
+The revision at 0xc3 seems to increment over time:
+
+```eval_rst
++-------------------+---------------------------------------+
+| Revision | Mainboard generation |
++-------------------+---------------------------------------+
+| 4 | T520 and T420s |
++-------------------+---------------------------------------+
+| 5 | W530 |
++-------------------+---------------------------------------+
+| 6 | T470p |
++-------------------+---------------------------------------+
+```
--
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