coreboot-gerrit July 2019

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/icelake: Refer to soc/soc_chip.h rather than chip.h
by Subrata Banik (Code Review) 08 Jul '19

08 Jul '19

Hello Patrick Rudolph, Angel Pons, Lean Sheng Tan, Aamir Bohra, Wonkyu Kim, Maulik V Vaghela, Paul Menzel, build bot (Jenkins), Martin Roth, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/34085 to look at the new patch set (#3). Change subject: soc/intel/icelake: Refer to soc/soc_chip.h rather than chip.h ...................................................................... soc/intel/icelake: Refer to soc/soc_chip.h rather than chip.h Change-Id: I9e3b5126173e7cec8f2809a38b92c82c9ed5327d Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/icelake/acpi.c M src/soc/intel/icelake/chip.c M src/soc/intel/icelake/cpu.c M src/soc/intel/icelake/espi.c M src/soc/intel/icelake/finalize.c M src/soc/intel/icelake/fsp_params.c M src/soc/intel/icelake/include/soc/ramstage.h M src/soc/intel/icelake/memmap.c M src/soc/intel/icelake/pmc.c M src/soc/intel/icelake/pmutil.c M src/soc/intel/icelake/romstage/fsp_params.c M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/icelake/sd.c M src/soc/intel/icelake/smihandler.c M src/soc/intel/icelake/smmrelocate.c 15 files changed, 15 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/34085/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/34085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e3b5126173e7cec8f2809a38b92c82c9ed5327d Gerrit-Change-Number: 34085 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/picasso: Add ability to begin romstage in DRAM
by Edward O'Callaghan (Code Review) 08 Jul '19

08 Jul '19

Edward O'Callaghan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/33759 ) Change subject: soc/amd/picasso: Add ability to begin romstage in DRAM ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/33759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id8c6175de34a0728ad41085e9c7cd310bd280976 Gerrit-Change-Number: 33759 Gerrit-PatchSet: 3 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Edward O'Callaghan <quasisec(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 08 Jul 2019 05:06:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/icelake: Refer to soc/soc_chip.h rather chip.h
by Lean Sheng Tan (Code Review) 08 Jul '19

08 Jul '19

Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34085 ) Change subject: soc/intel/icelake: Refer to soc/soc_chip.h rather chip.h ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/34085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e3b5126173e7cec8f2809a38b92c82c9ed5327d Gerrit-Change-Number: 34085 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 08 Jul 2019 04:02:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/hatch: Set GPP_D9 as enable pin for Goodix Touch Screen
by Frank Wu (Code Review) 08 Jul '19

08 Jul '19

Frank Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33808 Change subject: mb/google/hatch: Set GPP_D9 as enable pin for Goodix Touch Screen ...................................................................... mb/google/hatch: Set GPP_D9 as enable pin for Goodix Touch Screen Goodix touchscreen cannot work in normal mode because PP3300_TOUCHSCREEN_DX dropped. Configure GPP_D9 as enable pin in the devicetree.cb to fix the power sequence. BUG=b:135287161 BRANCH=None TEST=local build and measure sequence with Goodix touch screen Change-Id: I33140869990aa4715c780b0fa322921e450530ef Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/hatch/overridetree.cb M src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb 3 files changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/33808/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index e309175..e92d93b 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -195,8 +195,8 @@ PAD_NC(GPP_D7, NONE), /* D8 : WWAN_CONFIG_3 */ PAD_NC(GPP_D8, NONE), - /* D9 : GPP_D9 ==> NC */ - PAD_NC(GPP_D9, NONE), + /* D9 : GPP_D9 ==> EN_PP3300_DX_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_D9, 0, DEEP), /* D10 : GPP_D10 ==> NC */ PAD_NC(GPP_D10, NONE), /* D11 : GPP_D11 ==> NC */ diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index d676843..fd2d061 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -91,6 +91,8 @@ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "10" register "generic.reset_off_delay_ms" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "10" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end diff --git a/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb b/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb index 373438c..c3a1b2e 100644 --- a/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb @@ -82,6 +82,8 @@ "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "generic.reset_delay_ms" = "10" register "generic.reset_off_delay_ms" = "1" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D9)" + register "generic.enable_delay_ms" = "10" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" device i2c 5d on end -- To view, visit https://review.coreboot.org/c/coreboot/+/33808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33140869990aa4715c780b0fa322921e450530ef Gerrit-Change-Number: 33808 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Update GPIO settings
by Krishna P Bhat D (Code Review) 07 Jul '19

07 Jul '19

Krishna P Bhat D has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32176 Change subject: mb/google/hatch: Update GPIO settings ...................................................................... mb/google/hatch: Update GPIO settings This patch updates the following GPIO settings. 1. Set Native termination for GPP_G0 - G4 SD card pins. 2. Disable I2C #2 in devicetree. 3. Set GPP_B19, GPP_G7 to NF1. BUG=b:123907904 Change-Id: I4549ac7377d7f58f51cda0eb96a62604fd31d2f2 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/hatch/overridetree.cb M src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb 3 files changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/32176/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 4d1c87e..10f851b 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -106,8 +106,8 @@ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), /* B18 : H1_SLAVE_SPI_MOSI_R */ PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1), - /* B19 : GPP_B19 ==> NC */ - PAD_NC(GPP_B19, NONE), + /* B19 : Set to NF1 */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), /* B20 : PCH_SPI_FPMCU_CLK_R */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), /* B21 : PCH_SPI_FPMCU_MISO */ @@ -329,21 +329,21 @@ PAD_NC(GPP_F23, NONE), /* G0 : SD_CMD */ - PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G0, NATIVE, DEEP, NF1), /* G1 : SD_DATA0 */ - PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G1, NATIVE, DEEP, NF1), /* G2 : SD_DATA1 */ - PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G2, NATIVE, DEEP, NF1), /* G3 : SD_DATA2 */ - PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G3, NATIVE, DEEP, NF1), /* G4 : SD_DATA3 */ - PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_G4, NATIVE, DEEP, NF1), /* G5 : SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), /* G6 : SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), - /* G7 : SD_WP => NC */ - PAD_NC(GPP_G7, DN_20K), + /* G7 : Set to NF1 */ + PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), /* * H0 : HP_INT_L diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index 28644d1..57daba2 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -69,7 +69,7 @@ device i2c 49 on end end end # I2C #1 - device pci 15.2 on + device pci 15.2 off chip drivers/generic/gpio_keys register "name" = ""PENH"" register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_HIGH(GPP_A8)" diff --git a/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb b/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb index 9b772c2..098bca6 100644 --- a/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb @@ -54,7 +54,7 @@ device i2c 49 on end end end # I2C #1 - device pci 15.2 on + device pci 15.2 off chip drivers/generic/gpio_keys register "name" = ""PENH"" register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_HIGH(GPP_A8)" -- To view, visit https://review.coreboot.org/c/coreboot/+/32176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4549ac7377d7f58f51cda0eb96a62604fd31d2f2 Gerrit-Change-Number: 32176 Gerrit-PatchSet: 1 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: lib/romstage_stack.c: Remove file
by Kyösti Mälkki (Code Review) 07 Jul '19

07 Jul '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33957 Change subject: lib/romstage_stack.c: Remove file ...................................................................... lib/romstage_stack.c: Remove file After platforms have moved to POSTCAR_STAGE=y the only remaining user is binaryPI now. Make it simpler. Change-Id: Ia70c5c85e06c42f965fb7204b633db9b619e2e84 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/amd/pi/romstage.c M src/include/program_loading.h M src/lib/Makefile.inc D src/lib/romstage_stack.c 4 files changed, 1 insertion(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/33957/1 diff --git a/src/cpu/amd/pi/romstage.c b/src/cpu/amd/pi/romstage.c index aa14826..cfd4164 100644 --- a/src/cpu/amd/pi/romstage.c +++ b/src/cpu/amd/pi/romstage.c @@ -40,8 +40,7 @@ romstage_handoff_init(s3resume); - uintptr_t stack_top = romstage_ram_stack_base(HIGH_ROMSTAGE_STACK_SIZE, - ROMSTAGE_STACK_CBMEM); + char *stack_top = cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, HIGH_ROMSTAGE_STACK_SIZE); stack_top += HIGH_ROMSTAGE_STACK_SIZE; printk(BIOS_DEBUG, "Move CAR stack.\n"); diff --git a/src/include/program_loading.h b/src/include/program_loading.h index 223fc0b..5ac74bf 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -173,10 +173,6 @@ /* Run ramstage from romstage. */ void run_ramstage(void); -/* Determine where stack for ramstage loader is located. */ -enum { ROMSTAGE_STACK_CBMEM, ROMSTAGE_STACK_LOW_MEM }; -uintptr_t romstage_ram_stack_base(size_t size, int src); - /* Backup OS memory to CBMEM_ID_RESUME on ACPI S3 resume path, * if ramstage overwrites low memory. */ void backup_ramstage_section(uintptr_t base, size_t size); diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 16d5c64..f6d3f6d 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -89,9 +89,7 @@ romstage-y += region_file.c ramstage-y += romstage_handoff.c romstage-y += romstage_handoff.c -romstage-y += romstage_stack.c romstage-y += selfboot.c -ramstage-y += romstage_stack.c romstage-y += stack.c ramstage-y += rtc.c diff --git a/src/lib/romstage_stack.c b/src/lib/romstage_stack.c deleted file mode 100644 index 50ea6a5..0000000 --- a/src/lib/romstage_stack.c +++ /dev/null @@ -1,35 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <program_loading.h> -#include <cbmem.h> - -/* - * Romstage needs quite a bit of stack for decompressing images since the lzma - * lib keeps its state on the stack during romstage. - */ -#define ROMSTAGE_RAM_STACK_SIZE 0x5000 - -uintptr_t romstage_ram_stack_base(size_t size, int src) -{ - /* cbmem_add() does a find() before add(). */ - if (src == ROMSTAGE_STACK_CBMEM) - return (uintptr_t)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, size); - if (src == ROMSTAGE_STACK_LOW_MEM) - return CONFIG_RAMTOP - size; - return 0; -} - -- To view, visit https://review.coreboot.org/c/coreboot/+/33957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia70c5c85e06c42f965fb7204b633db9b619e2e84 Gerrit-Change-Number: 33957 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/ppc64: Make PPC64 specific options depend on ARCH_PPC64
by Kyösti Mälkki (Code Review) 07 Jul '19

07 Jul '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31314 ) Change subject: arch/ppc64: Make PPC64 specific options depend on ARCH_PPC64 ...................................................................... Patch Set 4: Code-Review-1 For consistency with everything else, I'd rather keep the cpu Kconfig file. CB:34115 -- To view, visit https://review.coreboot.org/c/coreboot/+/31314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70b64e49e1ce07b8f30d9bbc493272bdfb3bb0bf Gerrit-Change-Number: 31314 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 07 Jul 2019 21:05:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: arch/non-x86: Flip HAVE_MONOTONIC_TIMER default
by Nico Huber (Code Review) 07 Jul '19

07 Jul '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34112 ) Change subject: arch/non-x86: Flip HAVE_MONOTONIC_TIMER default ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/34112 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9dfa9b92dc63375465e3bb87b73eeefad601c810 Gerrit-Change-Number: 34112 Gerrit-PatchSet: 5 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Sun, 07 Jul 2019 21:04:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: WIP: mediatek/mt8183: update dcxo setting
by Weiyi Lu (Code Review) 07 Jul '19

07 Jul '19

Hello Weiyi Lu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32323 to review the following change. Change subject: WIP: mediatek/mt8183: update dcxo setting ...................................................................... WIP: mediatek/mt8183: update dcxo setting Disable unused DCXO and power mode. BRANCH=none TEST=Boots correctly on Kukui. Change-Id: I2e5ce181ad327ccf852979da53baca4f249912fe Signed-off-by: Weiyi Lu <weiyi.lu(a)mediatek.com> --- M src/soc/mediatek/mt8183/include/soc/rtc.h M src/soc/mediatek/mt8183/rtc.c 2 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/32323/1 diff --git a/src/soc/mediatek/mt8183/include/soc/rtc.h b/src/soc/mediatek/mt8183/include/soc/rtc.h index 3d115fe..a721ff8 100644 --- a/src/soc/mediatek/mt8183/include/soc/rtc.h +++ b/src/soc/mediatek/mt8183/include/soc/rtc.h @@ -140,6 +140,7 @@ PMIC_RG_DCXO_CW15 = 0x07AE, PMIC_RG_DCXO_CW16 = 0x07B0, PMIC_RG_DCXO_CW21 = 0x07BA, + PMIC_RG_DCXO_CW23 = 0x07BE, PMIC_RG_DCXO_ELR0 = 0x07C4 }; diff --git a/src/soc/mediatek/mt8183/rtc.c b/src/soc/mediatek/mt8183/rtc.c index 62256eb..57f26e8 100644 --- a/src/soc/mediatek/mt8183/rtc.c +++ b/src/soc/mediatek/mt8183/rtc.c @@ -281,9 +281,10 @@ rtc_write(PMIC_RG_DCXO_CW16, 0x9855); /* 26M enable control */ - /* Enable clock buffer XO_SOC, XO_CEL */ - rtc_write(PMIC_RG_DCXO_CW00, 0x4805); + /* Enable clock buffer XO_SOC */ + rtc_write(PMIC_RG_DCXO_CW00, 0x4005); rtc_write(PMIC_RG_DCXO_CW11, 0x8000); + rtc_write(PMIC_RG_DCXO_CW23, 0x0053); /* Load thermal coefficient */ rtc_write(PMIC_RG_TOP_TMA_KEY, 0x9CA7); -- To view, visit https://review.coreboot.org/c/coreboot/+/32323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e5ce181ad327ccf852979da53baca4f249912fe Gerrit-Change-Number: 32323 Gerrit-PatchSet: 1 Gerrit-Owner: Weiyi Lu <weiyi.lu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Weiyi Lu <weiyi.lu(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/ppc64: Make PPC64 specific options depend on ARCH_PPC64
by Martin Roth (Code Review) 07 Jul '19

07 Jul '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31314 ) Change subject: arch/ppc64: Make PPC64 specific options depend on ARCH_PPC64 ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70b64e49e1ce07b8f30d9bbc493272bdfb3bb0bf Gerrit-Change-Number: 31314 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 07 Jul 2019 21:01:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit July 2019