Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33036
Change subject: sb/intel/common: Add a common interface to set final OPs settings
......................................................................
sb/intel/common: Add a common interface to set final OPs settings
This adds a common place to set the final opprefix, optype and opmenu,
with a hook to override the opmenu.
Change-Id: I162ae6bad7da3ea02b96854ee28e70594e210947
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/southbridge/intel/common/spi.c
A src/southbridge/intel/common/spi.h
2 files changed, 79 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/33036/1
diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index bf2a44c..0794bb7 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -31,6 +31,8 @@
#include <spi-generic.h>
+#include "spi.h"
+
#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */
#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF)
#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */
@@ -1041,6 +1043,45 @@
return 0;
}
+void spi_finalize_ops(void)
+{
+ ich_spi_controller *cntlr = &g_cntlr;
+ u16 spi_opprefix;;
+ u16 optype = 0;
+ struct intel_spi_config spi_config = {
+ {0x06, 0x50}, /* OPPREFIXES: EWSR and WREN */
+ { /* OPTYPE and OPCODE */
+ {0x01, WRITE_NO_ADDR}, /* WRSR: Write Status Register */
+ {0x02, WRITE_WITH_ADDR}, /* BYPR: Byte Program */
+ {0x03, READ_WITH_ADDR}, /* READ: Read Data */
+ {0x05, READ_NO_ADDR}, /* RDSR: Read Status Register */
+ {0x20, WRITE_WITH_ADDR}, /* SE20: Sector Erase 0x20 */
+ {0x9f, READ_NO_ADDR}, /* RDID: Read ID */
+ {0xd8, WRITE_WITH_ADDR}, /* BED8: Block Erase 0xd8 */
+ {0x0b, READ_WITH_ADDR}, /* FAST: Fast Read */
+ }
+ };
+ int i;
+
+ if (g_ichspi_lock)
+ return;
+
+ intel_southbridge_override_spi(&spi_config);
+
+ spi_opprefix = spi_config.opprefixes[0]
+ | (spi_config.opprefixes[1] << 8);
+ writew_(spi_opprefix, cntlr->preop);
+ for (i = 0; i < ARRAY_SIZE(spi_config.ops); i++) {
+ optype |= (spi_config.ops[i].type & 3) << (i * 2);
+ writeb_(spi_config.ops[i].op, &cntlr->opmenu[i]);
+ }
+ writew_(optype, &cntlr->optype);
+}
+
+__weak void intel_southbridge_override_spi(struct intel_spi_config *spi_config)
+{
+}
+
static const struct spi_ctrlr spi_ctrlr = {
.xfer_vector = xfer_vectors,
.max_xfer_size = member_size(ich9_spi_regs, fdata),
diff --git a/src/southbridge/intel/common/spi.h b/src/southbridge/intel/common/spi.h
new file mode 100644
index 0000000..fcc5cd8
--- /dev/null
+++ b/src/southbridge/intel/common/spi.h
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOUTHBRIDGE_INTEL_SPI_H
+#define SOUTHBRIDGE_INTEL_SPI_H
+
+enum optype {
+ READ_NO_ADDR = 0,
+ WRITE_NO_ADDR = 1,
+ READ_WITH_ADDR = 2,
+ WRITE_WITH_ADDR = 3
+};
+
+struct intel_spi_op {
+ u8 op;
+ enum optype type;
+};
+
+struct intel_spi_config {
+ u8 opprefixes[2];
+ struct intel_spi_op ops[8];
+};
+
+void spi_finalize_ops(void);
+void intel_southbridge_override_spi(struct intel_spi_config *spi_config);
+
+#endif
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I162ae6bad7da3ea02b96854ee28e70594e210947
Gerrit-Change-Number: 33036
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-MessageType: newchange
Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31425
Change subject: qemu-q35: die if started on wrong machine
......................................................................
qemu-q35: die if started on wrong machine
The QEMU machine "PC" doesn't support MCFG.
Die in bootblock if the user selected the wrong qemu machine and
print a message to use the correct machine type.
Without this patch ramstage dies with non-helpful message:
"get_pbus: dev is NULL!"
Change-Id: I9d1b24176de971c5f827091bc5bc1bac8426f3f6
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
M src/mainboard/emulation/qemu-q35/bootblock.c
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/31425/1
diff --git a/src/mainboard/emulation/qemu-q35/bootblock.c b/src/mainboard/emulation/qemu-q35/bootblock.c
index 18a083d..96d3457 100644
--- a/src/mainboard/emulation/qemu-q35/bootblock.c
+++ b/src/mainboard/emulation/qemu-q35/bootblock.c
@@ -14,6 +14,7 @@
#include <arch/io.h>
#include <bootblock_common.h>
#include <southbridge/intel/i82801ix/i82801ix.h>
+#include <console/console.h>
/* Just define these here, there is no gm35.h file to include. */
#define D0F0_PCIEXBAR_LO 0x60
@@ -39,6 +40,11 @@
pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_HI, reg);
reg = CONFIG_MMCONF_BASE_ADDRESS | 1; /* 256MiB - 0-255 buses. */
pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg);
+
+ /* MCFG is now active. If it's not qemu was started for machine PC */
+ if (pci_read_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO) !=
+ (CONFIG_MMCONF_BASE_ADDRESS | 1))
+ die("You must run qemu for machine Q35");
}
static void enable_spi_prefetch(void)
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9d1b24176de971c5f827091bc5bc1bac8426f3f6
Gerrit-Change-Number: 31425
Gerrit-PatchSet: 1
Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: newchange
Hello Patrick Rudolph, Angel Pons, Lean Sheng Tan, Aamir Bohra, Wonkyu Kim, Maulik V Vaghela, Paul Menzel, build bot (Jenkins), Martin Roth, Furquan Shaikh,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/34085
to look at the new patch set (#4).
Change subject: soc/intel/icelake: Refer to soc/soc_chip.h rather than chip.h
......................................................................
soc/intel/icelake: Refer to soc/soc_chip.h rather than chip.h
Change-Id: I9e3b5126173e7cec8f2809a38b92c82c9ed5327d
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
M src/soc/intel/icelake/acpi.c
M src/soc/intel/icelake/chip.c
M src/soc/intel/icelake/cpu.c
M src/soc/intel/icelake/espi.c
M src/soc/intel/icelake/finalize.c
M src/soc/intel/icelake/fsp_params.c
M src/soc/intel/icelake/include/soc/ramstage.h
M src/soc/intel/icelake/memmap.c
M src/soc/intel/icelake/pmc.c
M src/soc/intel/icelake/pmutil.c
M src/soc/intel/icelake/romstage/fsp_params.c
M src/soc/intel/icelake/romstage/romstage.c
M src/soc/intel/icelake/sd.c
M src/soc/intel/icelake/smihandler.c
M src/soc/intel/icelake/smmrelocate.c
15 files changed, 15 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/34085/4
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9e3b5126173e7cec8f2809a38b92c82c9ed5327d
Gerrit-Change-Number: 34085
Gerrit-PatchSet: 4
Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: newpatchset