coreboot-gerrit July 2019

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Change in coreboot[master]: intel/socket_mPGA604: Enable TSC_MONOTONIC_TIMER
by Kyösti Mälkki (Code Review) 08 Jul '19

08 Jul '19

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34111 ) Change subject: intel/socket_mPGA604: Enable TSC_MONOTONIC_TIMER ...................................................................... intel/socket_mPGA604: Enable TSC_MONOTONIC_TIMER Change-Id: I3ca2b7752905209e8db6b1dc74b930445676792e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34111 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/cpu/intel/socket_mPGA604/Kconfig M src/mainboard/aopen/dxplplusu/Kconfig 2 files changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index ca2f7b3..1453f99 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -9,6 +9,7 @@ select MMX select SSE select UDELAY_TSC + select TSC_MONOTONIC_TIMER select SIPI_VECTOR_IN_ROM select C_ENVIRONMENT_BOOTBLOCK diff --git a/src/mainboard/aopen/dxplplusu/Kconfig b/src/mainboard/aopen/dxplplusu/Kconfig index 7dc0eab..738a2ea 100644 --- a/src/mainboard/aopen/dxplplusu/Kconfig +++ b/src/mainboard/aopen/dxplplusu/Kconfig @@ -7,7 +7,6 @@ select SOUTHBRIDGE_INTEL_I82870 select SOUTHBRIDGE_INTEL_I82801DX select SUPERIO_SMSC_LPC47M10X - select UDELAY_TSC select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 -- To view, visit https://review.coreboot.org/c/coreboot/+/34111 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ca2b7752905209e8db6b1dc74b930445676792e Gerrit-Change-Number: 34111 Gerrit-PatchSet: 2 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: intel/nehalem: Move TSC_MONOTONIC_TIMER
by Kyösti Mälkki (Code Review) 08 Jul '19

08 Jul '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34110 ) Change subject: intel/nehalem: Move TSC_MONOTONIC_TIMER ...................................................................... intel/nehalem: Move TSC_MONOTONIC_TIMER Change-Id: Ib7f2f7773d0eef5ac4e277b44ee9114aa6729527 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/intel/model_2065x/Kconfig M src/northbridge/intel/nehalem/Kconfig 2 files changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/34110/1 diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index d8c0168..0af0d35 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -13,6 +13,7 @@ select SSE2 select UDELAY_TSC select TSC_CONSTANT_RATE + select TSC_MONOTONIC_TIMER select SMM_TSEG select SUPPORT_CPU_UCODE_IN_CBFS select PARALLEL_CPU_INIT diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 1e50459..02b6e80 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -18,7 +18,6 @@ select CPU_INTEL_MODEL_2065X select VGA select INTEL_EDID - select TSC_MONOTONIC_TIMER select INTEL_GMA_ACPI select CACHE_MRC_SETTINGS select POSTCAR_STAGE -- To view, visit https://review.coreboot.org/c/coreboot/+/34110 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7f2f7773d0eef5ac4e277b44ee9114aa6729527 Gerrit-Change-Number: 34110 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/fsp_broadwell_de: Remove redundant TSC_MONOTONIC_TIMER
by Kyösti Mälkki (Code Review) 08 Jul '19

08 Jul '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34109 ) Change subject: intel/fsp_broadwell_de: Remove redundant TSC_MONOTONIC_TIMER ...................................................................... intel/fsp_broadwell_de: Remove redundant TSC_MONOTONIC_TIMER Change-Id: I240e9e767c9b38b3b06d3978fd20ddb37a96e470 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/intel/camelbackmountain_fsp/Kconfig M src/mainboard/ocp/monolake/Kconfig M src/mainboard/ocp/wedge100s/Kconfig M src/mainboard/siemens/mc_bdx1/Kconfig 4 files changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/34109/1 diff --git a/src/mainboard/intel/camelbackmountain_fsp/Kconfig b/src/mainboard/intel/camelbackmountain_fsp/Kconfig index 2829b84..696fbf4 100644 --- a/src/mainboard/intel/camelbackmountain_fsp/Kconfig +++ b/src/mainboard/intel/camelbackmountain_fsp/Kconfig @@ -6,7 +6,6 @@ select BOARD_ROMSIZE_KB_2048 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select TSC_MONOTONIC_TIMER select INTEGRATED_UART if FSP_PACKAGE_DEFAULT select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/ocp/monolake/Kconfig b/src/mainboard/ocp/monolake/Kconfig index 037c322..13d7876 100644 --- a/src/mainboard/ocp/monolake/Kconfig +++ b/src/mainboard/ocp/monolake/Kconfig @@ -6,7 +6,6 @@ select BOARD_ROMSIZE_KB_16384 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select TSC_MONOTONIC_TIMER select INTEGRATED_UART if FSP_PACKAGE_DEFAULT select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/ocp/wedge100s/Kconfig b/src/mainboard/ocp/wedge100s/Kconfig index 491829a..ef0fe88 100644 --- a/src/mainboard/ocp/wedge100s/Kconfig +++ b/src/mainboard/ocp/wedge100s/Kconfig @@ -6,7 +6,6 @@ select BOARD_ROMSIZE_KB_16384 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select TSC_MONOTONIC_TIMER select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select SERIRQ_CONTINUOUS_MODE select FSP_EHCI1_ENABLE diff --git a/src/mainboard/siemens/mc_bdx1/Kconfig b/src/mainboard/siemens/mc_bdx1/Kconfig index d99fea8..6feb1cf 100644 --- a/src/mainboard/siemens/mc_bdx1/Kconfig +++ b/src/mainboard/siemens/mc_bdx1/Kconfig @@ -6,7 +6,6 @@ select BOARD_ROMSIZE_KB_16384 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select TSC_MONOTONIC_TIMER select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select CBFS_AUTOGEN_ATTRIBUTES select USE_SIEMENS_HWILIB -- To view, visit https://review.coreboot.org/c/coreboot/+/34109 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I240e9e767c9b38b3b06d3978fd20ddb37a96e470 Gerrit-Change-Number: 34109 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: intel/fsp_baytrail: Move TSC_MONOTONIC_TIMER
by Kyösti Mälkki (Code Review) 08 Jul '19

08 Jul '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34108 ) Change subject: intel/fsp_baytrail: Move TSC_MONOTONIC_TIMER ...................................................................... intel/fsp_baytrail: Move TSC_MONOTONIC_TIMER Change-Id: Ib61ea29724401146eb6f008374cdf599f418e81f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/esd/atom15/Kconfig M src/mainboard/intel/bayleybay_fsp/Kconfig M src/mainboard/intel/minnowmax/Kconfig M src/mainboard/opencellular/rotundu/Kconfig M src/mainboard/siemens/mc_tcu3/Kconfig M src/soc/intel/fsp_baytrail/Kconfig 6 files changed, 1 insertion(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/34108/1 diff --git a/src/mainboard/esd/atom15/Kconfig b/src/mainboard/esd/atom15/Kconfig index 94dae08..5726461 100644 --- a/src/mainboard/esd/atom15/Kconfig +++ b/src/mainboard/esd/atom15/Kconfig @@ -22,7 +22,6 @@ select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select TSC_MONOTONIC_TIMER config MAINBOARD_DIR string diff --git a/src/mainboard/intel/bayleybay_fsp/Kconfig b/src/mainboard/intel/bayleybay_fsp/Kconfig index c849438..4a08fb1 100644 --- a/src/mainboard/intel/bayleybay_fsp/Kconfig +++ b/src/mainboard/intel/bayleybay_fsp/Kconfig @@ -23,7 +23,6 @@ select HAVE_OPTION_TABLE select ENABLE_BUILTIN_COM1 if FSP_PACKAGE_DEFAULT select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT - select TSC_MONOTONIC_TIMER config MAINBOARD_DIR string diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig index 59172e3..ca24c92 100644 --- a/src/mainboard/intel/minnowmax/Kconfig +++ b/src/mainboard/intel/minnowmax/Kconfig @@ -22,7 +22,6 @@ select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE - select TSC_MONOTONIC_TIMER config MAINBOARD_DIR string diff --git a/src/mainboard/opencellular/rotundu/Kconfig b/src/mainboard/opencellular/rotundu/Kconfig index f5d9340..fe1cbf9 100644 --- a/src/mainboard/opencellular/rotundu/Kconfig +++ b/src/mainboard/opencellular/rotundu/Kconfig @@ -22,7 +22,6 @@ select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select ENABLE_BUILTIN_COM1 - select TSC_MONOTONIC_TIMER select ENABLE_FSP_FAST_BOOT select HAVE_ACPI_RESUME select USE_BLOBS diff --git a/src/mainboard/siemens/mc_tcu3/Kconfig b/src/mainboard/siemens/mc_tcu3/Kconfig index db0fd24..508aaeb 100644 --- a/src/mainboard/siemens/mc_tcu3/Kconfig +++ b/src/mainboard/siemens/mc_tcu3/Kconfig @@ -24,7 +24,6 @@ select ENABLE_BUILTIN_COM1 select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT select ENABLE_FSP_FAST_BOOT - select TSC_MONOTONIC_TIMER select DRIVER_INTEL_I210 select SOC_INTEL_FSP_BAYTRAIL_MD select USE_BLOBS diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 5228bb7..26c9548 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -40,6 +40,7 @@ select TSC_CONSTANT_RATE select TSC_SYNC_MFENCE select UDELAY_TSC + select TSC_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS select MICROCODE_BLOB_NOT_HOOKED_UP select INTEL_DESCRIPTOR_MODE_CAPABLE -- To view, visit https://review.coreboot.org/c/coreboot/+/34108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib61ea29724401146eb6f008374cdf599f418e81f Gerrit-Change-Number: 34108 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: drivers/pc80: Move UDELAY_IO and UDELAY_TIMER2
by Kyösti Mälkki (Code Review) 08 Jul '19

08 Jul '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34107 ) Change subject: drivers/pc80: Move UDELAY_IO and UDELAY_TIMER2 ...................................................................... drivers/pc80: Move UDELAY_IO and UDELAY_TIMER2 No longer fallback to UDELAY_IO as default. Since these are not cpu properties or features, move the Kconfig location. Change-Id: I9809cdc285c7bf741aa391ddb5755390bbfc2909 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/cpu/x86/Kconfig M src/drivers/pc80/pc/Kconfig 2 files changed, 13 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/34107/1 diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 608afd7..99a7075 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -17,11 +17,6 @@ Allow APs to do other work after initialization instead of going to sleep. -config UDELAY_IO - bool - default y if !UDELAY_LAPIC && !UDELAY_TSC && !UDELAY_TIMER2 && !GENERIC_UDELAY - default n - config UDELAY_LAPIC bool default n @@ -54,11 +49,6 @@ help Expose monotonic time using the TSC. -# This option is used in code but never selected. -config UDELAY_TIMER2 - bool - default n - config TSC_SYNC_LFENCE bool default n diff --git a/src/drivers/pc80/pc/Kconfig b/src/drivers/pc80/pc/Kconfig index c44cf91..bba45f6 100644 --- a/src/drivers/pc80/pc/Kconfig +++ b/src/drivers/pc80/pc/Kconfig @@ -1,10 +1,11 @@ +if PC80_SYSTEM + # Might be removed (alongside with the PS/2 init code) once payloads # reliably support PS/2 init themselves. config DRIVERS_PS2_KEYBOARD bool "PS/2 keyboard init" default n - depends on PC80_SYSTEM help Enable this option to initialize PS/2 keyboards found connected to the PS/2 port. @@ -16,3 +17,14 @@ If you know you will only use a payload which does not require this option, then you can say N here to speed up boot time. Otherwise say Y. + +config UDELAY_IO + bool + default n + +# This option is used in code but never selected. +config UDELAY_TIMER2 + bool + default n + +endif -- To view, visit https://review.coreboot.org/c/coreboot/+/34107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9809cdc285c7bf741aa391ddb5755390bbfc2909 Gerrit-Change-Number: 34107 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: device/oprom: Fix coding standard problem from // to /* */
by Subrata Banik (Code Review) 08 Jul '19

08 Jul '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33783 Change subject: device/oprom: Fix coding standard problem from // to /* */ ...................................................................... device/oprom: Fix coding standard problem from // to /* */ Change-Id: I321d9e54fee42cd9f0cff5f962246934209577f7 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/device/oprom/realmode/x86.c 1 file changed, 17 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/33783/1 diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index a7631a1..80455a5 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -104,9 +104,9 @@ printk(BIOS_INFO, "Oops, exception %d while executing option rom\n", regs->vector); - x86_exception(regs); // Call coreboot exception handler + x86_exception(regs); /* Call coreboot exception handler */ - return 0; // Never really returns + return 0; /* Never really returns */ } static int intXX_unknown_handler(void) @@ -238,9 +238,9 @@ static u8 vbe_set_mode(vbe_mode_info_t * mi) { printk(BIOS_DEBUG, "VBE: Setting VESA mode %04x\n", mi->video_mode); - // request linear framebuffer mode + /* request linear framebuffer mode */ mi->video_mode |= (1 << 14); - // request clearing of framebuffer + /* request clearing of framebuffer */ mi->video_mode &= ~(1 << 15); realmode_interrupt(0x10, VESA_SET_MODE, mi->video_mode, 0x0000, 0x0000, 0x0000, 0x0000); @@ -393,8 +393,9 @@ ip, cs, flags); #endif - // Fetch arguments from the stack and put them to a place - // suitable for the interrupt handlers + /* Fetch arguments from the stack and put them to a place + * suitable for the interrupt handlers + */ X86_EAX = eax; X86_ECX = ecx; X86_EDX = edx; @@ -409,15 +410,16 @@ X86_CS = cs; X86_EFLAGS = flags; - // Call the interrupt handler for this int# + /* Call the interrupt handler for this int# */ ret = intXX_handler[intnumber](); - // Put registers back on the stack. The assembler code - // will later pop them. - // What happens here is that we force (volatile!) changing - // the values of the parameters of this function. We do this - // because we know that they stay alive on the stack after - // we leave this function. Don't say this is bollocks. + /* Put registers back on the stack. The assembler code + * will later pop them. + * What happens here is that we force (volatile!) changing + * the values of the parameters of this function. We do this + * because we know that they stay alive on the stack after + * we leave this function. Don't say this is bollocks. + */ *(volatile u32 *)&eax = X86_EAX; *(volatile u32 *)&ecx = X86_ECX; *(volatile u32 *)&edx = X86_EDX; @@ -428,10 +430,10 @@ /* Pass success or error back to our caller via the CARRY flag */ if (ret) { - flags &= ~1; // no error: clear carry + flags &= ~1; /* no error: clear carry */ }else{ printk(BIOS_DEBUG,"int%02x call returned error.\n", intnumber); - flags |= 1; // error: set carry + flags |= 1; /* error: set carry */ } *(volatile u16 *)&stackflags = flags; -- To view, visit https://review.coreboot.org/c/coreboot/+/33783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I321d9e54fee42cd9f0cff5f962246934209577f7 Gerrit-Change-Number: 33783 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: device/oprom: Update vbe_info_t as per vbe specification 3.0
by Subrata Banik (Code Review) 08 Jul '19

08 Jul '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33806 Change subject: device/oprom: Update vbe_info_t as per vbe specification 3.0 ...................................................................... device/oprom: Update vbe_info_t as per vbe specification 3.0 This patch fixes unable to get correct value from TotalMemory variable using existing vbe_info_t structure. New vbe_info_t structure follows vbe spec 3.0. http://www.vesa.org/public/VBE/vbe3.pdf Change-Id: I12db01280aec480f1f42332ebe97d92539dfdc1c Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/device/oprom/yabel/vbe.c M src/include/vbe.h 2 files changed, 16 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/33806/1 diff --git a/src/device/oprom/yabel/vbe.c b/src/device/oprom/yabel/vbe.c index 682bf00..104b4c2 100644 --- a/src/device/oprom/yabel/vbe.c +++ b/src/device/oprom/yabel/vbe.c @@ -66,6 +66,9 @@ u8 *biosmem; u32 biosmem_size; +/* Let's hope we never have more than 256 video modes. */ +#define MAX_VBE_FRAMEBUFFER_MODE 256 + #if CONFIG(FRAMEBUFFER_SET_VESA_MODE) static inline u8 vbe_prepare(void) @@ -133,20 +136,9 @@ info->capabilities = in32le(vbe_info_buffer + 10); // offset 14: 32 bit le containing segment:offset of supported video mode table - u16 *video_mode_ptr; - video_mode_ptr = - (u16 *) (biosmem + - ((in16le(vbe_info_buffer + 16) << 4) + - in16le(vbe_info_buffer + 14))); - u32 i = 0; - do { - info->video_mode_list[i] = in16le(video_mode_ptr + i); - i++; - } - while ((i < - (sizeof(info->video_mode_list) / - sizeof(info->video_mode_list[0]))) - && (info->video_mode_list[i - 1] != 0xFFFF)); + info->video_mode_ptr = + (u32 *)(biosmem + ((in16le(vbe_info_buffer + 16) << 4) + + in16le(vbe_info_buffer + 14))); //offset 18: 16bit le total memory in 64KB blocks info->total_memory = in16le(vbe_info_buffer + 18); @@ -441,7 +433,7 @@ vbe_get_info(void) { u8 rval; - int i; + int i = 0; // XXX FIXME these need to be filled with sane values @@ -536,12 +528,17 @@ DEBUG_PRINTF_VBE("DDC: found display type %d\n", output->display_type); memcpy(output->edid_block_zero, ddc_info.edid_block_zero, sizeof(ddc_info.edid_block_zero)); - i = 0; vbe_mode_info_t mode_info; vbe_mode_info_t best_mode_info; + u16 video_mode_list[MAX_VBE_FRAMEBUFFER_MODE]; // initialize best_mode to 0 memset(&best_mode_info, 0, sizeof(best_mode_info)); - while ((mode_info.video_mode = info.video_mode_list[i]) != 0xFFFF) { + do { + video_mode_list[i] = in16le(info.video_mode_ptr + i); + i++; + } while (video_mode_list[i - 1] != 0xFFFF); + i = 0; + while ((mode_info.video_mode = video_mode_list[i]) != 0xFFFF) { //DEBUG_PRINTF_VBE("%x: Mode: %04x\n", i, mode_info.video_mode); vbe_get_mode_info(&mode_info); diff --git a/src/include/vbe.h b/src/include/vbe.h index 2aa45a8..af7bfa1 100644 --- a/src/include/vbe.h +++ b/src/include/vbe.h @@ -41,9 +41,9 @@ u16 version; u8 *oem_string_ptr; u32 capabilities; - u16 video_mode_list[256]; // lets hope we never have more than - // 256 video modes... + u32 *video_mode_ptr; u16 total_memory; + char reserved[236]; } __packed vbe_info_t; typedef struct { -- To view, visit https://review.coreboot.org/c/coreboot/+/33806 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I12db01280aec480f1f42332ebe97d92539dfdc1c Gerrit-Change-Number: 33806 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: vbe.h: Convert hardcode vega mode into macro
by Subrata Banik (Code Review) 08 Jul '19

08 Jul '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33782 Change subject: vbe.h: Convert hardcode vega mode into macro ...................................................................... vbe.h: Convert hardcode vega mode into macro This patch replaces vega framebuffer mode hard coded value into macro (MAX_VBE_FRAMEBUFFER_MODE). Also make use of __packed to align data access. Change-Id: I5e79b21acf44f6ca184a09d42acdf69c31dd4841 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/include/vbe.h 1 file changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/33782/1 diff --git a/src/include/vbe.h b/src/include/vbe.h index 2c40d05..88888e8 100644 --- a/src/include/vbe.h +++ b/src/include/vbe.h @@ -14,6 +14,10 @@ #define VBE_H #include <boot/coreboot_tables.h> + +/* Let's hope we never have more than 256 video modes. */ +#define MAX_VBE_FRAMEBUFFER_MODE 256 + // these structs are for input from and output to OF typedef struct { u8 display_type; // 0 = NONE, 1 = analog, 2 = digital @@ -41,10 +45,9 @@ u16 version; u8 *oem_string_ptr; u32 capabilities; - u16 video_mode_list[256]; // lets hope we never have more than - // 256 video modes... + u16 video_mode_list[MAX_VBE_FRAMEBUFFER_MODE]; u16 total_memory; -} vbe_info_t; +} __packed vbe_info_t; typedef struct { u16 mode_attributes; // 00 -- To view, visit https://review.coreboot.org/c/coreboot/+/33782 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e79b21acf44f6ca184a09d42acdf69c31dd4841 Gerrit-Change-Number: 33782 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

4 17

Change in ...coreboot[master]: payloads/external/Memtest86Plus: update to version 002 stable
by Martin Kepplinger (Code Review) 08 Jul '19

08 Jul '19

Martin Kepplinger has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32613 Change subject: payloads/external/Memtest86Plus: update to version 002 stable ...................................................................... payloads/external/Memtest86Plus: update to version 002 stable The memtest86plus project has been tagged as stable. Update the coreboot build accordingly. Change-Id: I078ac5d91e60a424efb5e14f39ae59e7ae9cbfe2 Signed-off-by: Martin Kepplinger <martink(a)posteo.de> --- M payloads/external/Memtest86Plus/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/32613/1 diff --git a/payloads/external/Memtest86Plus/Makefile b/payloads/external/Memtest86Plus/Makefile index 4b3132d..b799f9e 100644 --- a/payloads/external/Memtest86Plus/Makefile +++ b/payloads/external/Memtest86Plus/Makefile @@ -15,7 +15,7 @@ TAG-$(CONFIG_MEMTEST_MASTER)=origin/master NAME-$(CONFIG_MEMTEST_MASTER)=Master -TAG-$(CONFIG_MEMTEST_STABLE)=3754fd440f4009b62244e0f95c56bbb12c2fffcb +TAG-$(CONFIG_MEMTEST_STABLE)=0bd34c22604660e4283316331f3e7bf8a3863753 NAME-$(CONFIG_MEMTEST_STABLE)=Stable TAG-$(CONFIG_MEMTEST_REVISION)=$(CONFIG_MEMTEST_REVISION_ID) -- To view, visit https://review.coreboot.org/c/coreboot/+/32613 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I078ac5d91e60a424efb5e14f39ae59e7ae9cbfe2 Gerrit-Change-Number: 32613 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Kepplinger <martink(a)posteo.de> Gerrit-MessageType: newchange

5 6

Change in coreboot[master]: soc/intel/icelake: Refer to soc/soc_chip.h rather than chip.h
by Subrata Banik (Code Review) 08 Jul '19

08 Jul '19

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34085 ) Change subject: soc/intel/icelake: Refer to soc/soc_chip.h rather than chip.h ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/c/coreboot/+/34085/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/34085/2//COMMIT_MSG@7 PS2, Line 7: rather > rather *than* Done https://review.coreboot.org/c/coreboot/+/34085/2/src/soc/intel/icelake/acpi… File src/soc/intel/icelake/acpi.c: https://review.coreboot.org/c/coreboot/+/34085/2/src/soc/intel/icelake/acpi… PS2, Line 33: #include <soc/soc_chip.h> > Please move these includes so that they are alphabetically ordered Done -- To view, visit https://review.coreboot.org/c/coreboot/+/34085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9e3b5126173e7cec8f2809a38b92c82c9ed5327d Gerrit-Change-Number: 34085 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 08 Jul 2019 06:32:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit July 2019