coreboot-gerrit May 2019

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Change in ...coreboot[master]: arch/x86: Drop Kconfig SIPI_VECTOR_IN_ROM
by Kyösti Mälkki (Code Review) 21 Dec '19

21 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30856 Change subject: arch/x86: Drop Kconfig SIPI_VECTOR_IN_ROM ...................................................................... arch/x86: Drop Kconfig SIPI_VECTOR_IN_ROM This was used to enforce 4kiB alignment of _start16bit in romcc bootblock. Platforms requiring this moved away to C_ENVIRONMENT_BOOTBLOCK that globally forces the alignment. Change-Id: I8ca453bbc56ab2aeb127f3e081c69e1b38bb8396 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/arch/x86/Kconfig M src/arch/x86/failover.ld M src/cpu/intel/car/p4-netburst/cache_as_ram.S M src/cpu/intel/model_106cx/Kconfig M src/cpu/intel/socket_LGA775/Kconfig M src/cpu/intel/socket_mPGA604/Kconfig M src/cpu/x86/16bit/entry16.inc 7 files changed, 5 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/30856/1 diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 242a7cf..c2fc914 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -81,13 +81,6 @@ default n depends on ARCH_X86 && SMP -# Aligns 16bit entry code in bootblock so that hyper-threading CPUs -# can boot AP CPUs to enable their shared caches. -config SIPI_VECTOR_IN_ROM - bool - default n - depends on ARCH_X86 - # Set the rambase for systems that still need it, only 5 chipsets as of # Sep 2018. This value was 0x100000, chosen to match the entry point # of Linux 2.2 in 1999. The new value, 14 MiB, makes a lot more sense diff --git a/src/arch/x86/failover.ld b/src/arch/x86/failover.ld index b32aa29..eabc9f7 100644 --- a/src/arch/x86/failover.ld +++ b/src/arch/x86/failover.ld @@ -23,12 +23,11 @@ TARGET(binary) SECTIONS { - /* Symbol ap_sipi_vector must be aligned to 4kB to start AP CPUs - * with Startup IPI message without RAM. Align .rom to next 4 byte - * boundary anyway, so no pad byte appears between _rom and _start. + /* Align .rom to 4 byte boundary so no pad byte appears + * between _rom and _start. */ .bogus ROMLOC_MIN : { - . = CONFIG_SIPI_VECTOR_IN_ROM ? ALIGN(4096) : ALIGN(4); + . = ALIGN(4); ROMLOC = .; } >rom = 0xff @@ -49,12 +48,7 @@ * may cause the total size of a section to change when the start * address gets applied. */ - ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16) - - (CONFIG_SIPI_VECTOR_IN_ROM ? 4096 : 0); - - /* Post-check proper SIPI vector. */ - _bogus = ASSERT(!CONFIG_SIPI_VECTOR_IN_ROM || (ap_sipi_vector_in_rom == 0xff), - "Address mismatch on AP_SIPI_VECTOR"); + ROMLOC_MIN = 0xffffff00 - (_erom - _rom + 16); /DISCARD/ : { *(.comment) diff --git a/src/cpu/intel/car/p4-netburst/cache_as_ram.S b/src/cpu/intel/car/p4-netburst/cache_as_ram.S index fda572d..5c579a1 100644 --- a/src/cpu/intel/car/p4-netburst/cache_as_ram.S +++ b/src/cpu/intel/car/p4-netburst/cache_as_ram.S @@ -23,10 +23,6 @@ /* Macro to access Local APIC registers at default base. */ #define LAPIC(x) $(LAPIC_DEFAULT_BASE | LAPIC_ ## x) -#if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) -/* Fixed location, ASSERTED in failover.ld if it changes. */ -.set ap_sipi_vector_in_rom, 0xff -#endif #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig index f365cf1..2a324fb 100644 --- a/src/cpu/intel/model_106cx/Kconfig +++ b/src/cpu/intel/model_106cx/Kconfig @@ -7,7 +7,6 @@ select SMP select SSE2 select UDELAY_LAPIC - select SIPI_VECTOR_IN_ROM select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 8b227bd..6c3d837 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -13,7 +13,6 @@ select CPU_INTEL_MODEL_1067X select MMX select SSE - select SIPI_VECTOR_IN_ROM config DCACHE_RAM_SIZE hex diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index ca2f7b3..e860ded 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -9,7 +9,6 @@ select MMX select SSE select UDELAY_TSC - select SIPI_VECTOR_IN_ROM select C_ENVIRONMENT_BOOTBLOCK # mPGA604 are usually Intel Netburst CPUs which should have SSE2 diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 2a9f8c5..f110980 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -29,8 +29,7 @@ #include <arch/rom_segs.h> -#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) || \ - IS_ENABLED(CONFIG_SIPI_VECTOR_IN_ROM) +#if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) /* Symbol _start16bit must be aligned to 4kB to start AP CPUs with * Startup IPI message without RAM. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ca453bbc56ab2aeb127f3e081c69e1b38bb8396 Gerrit-Change-Number: 30856 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP] Move AGESA and apufw higher in CBFS
by Kyösti Mälkki (Code Review) 19 Dec '19

19 Dec '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31076 Change subject: [WIP] Move AGESA and apufw higher in CBFS ...................................................................... [WIP] Move AGESA and apufw higher in CBFS Increases continuous free space in CBFS from 5.8 MiB to 7.1 MiB. Will not work with released binaryPI build from 3rdparty/blobs. Change-Id: I3c166102b8774499a0b21f212b5e8a66fe6c52eb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/southbridge/amd/pi/hudson/Makefile.inc M src/vendorcode/amd/pi/Kconfig 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/31076/1 diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 81fe7ff..57bad38 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -75,7 +75,7 @@ ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) HUDSON_FWM_POSITION=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 0x20000 1) else -HUDSON_FWM_POSITION=0xfff20000 +HUDSON_FWM_POSITION=0xfffa0000 endif ifeq ($(CONFIG_HUDSON_PSP), y) diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig index f463b7d..3dc7052 100644 --- a/src/vendorcode/amd/pi/Kconfig +++ b/src/vendorcode/amd/pi/Kconfig @@ -96,7 +96,7 @@ config AGESA_BINARY_PI_LOCATION hex "AGESA PI binary address in ROM" - default 0xFFE00000 + default 0xFFF00000 depends on !AGESA_BINARY_PI_AS_STAGE help Specify the ROM address at which to store the binary Platform -- To view, visit https://review.coreboot.org/c/coreboot/+/31076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3c166102b8774499a0b21f212b5e8a66fe6c52eb Gerrit-Change-Number: 31076 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: src/arch: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32820 Change subject: src/arch: Use 'include <stdlib.h>' when appropriate ...................................................................... src/arch: Use 'include <stdlib.h>' when appropriate Change-Id: I79f065703b5249ca9630b06de7142bc52675076e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm/armv7/mmu.c M src/arch/arm/cpu.c M src/arch/mips/mmu.c M src/arch/x86/acpigen_dsm.c M src/arch/x86/cbmem.c M src/arch/x86/mmap_boot.c 6 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/32820/1 diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index ce9d3fd..f0a5fa6 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -29,12 +29,9 @@ */ #include <assert.h> -#include <stdlib.h> #include <stdint.h> #include <symbols.h> - #include <console/console.h> - #include <arch/cache.h> #if CONFIG(ARM_LPAE) diff --git a/src/arch/arm/cpu.c b/src/arch/arm/cpu.c index fae1a37..0637bf6 100644 --- a/src/arch/arm/cpu.c +++ b/src/arch/arm/cpu.c @@ -27,7 +27,6 @@ * SUCH DAMAGE. * */ -#include <stdlib.h> #include <arch/cpu.h> /* Return the CPU struct which is at the high memory address of the stack. diff --git a/src/arch/mips/mmu.c b/src/arch/mips/mmu.c index b144fd3..2ceb2a7 100644 --- a/src/arch/mips/mmu.c +++ b/src/arch/mips/mmu.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <stddef.h> #include <stdint.h> -#include <stdlib.h> #define MIN_PAGE_SIZE (4 * KiB) diff --git a/src/arch/x86/acpigen_dsm.c b/src/arch/x86/acpigen_dsm.c index 1aab90b..8c9cd350 100644 --- a/src/arch/x86/acpigen_dsm.c +++ b/src/arch/x86/acpigen_dsm.c @@ -15,7 +15,6 @@ #include <arch/acpigen.h> #include <arch/acpigen_dsm.h> -#include <stdlib.h> /* ------------------- I2C HID DSM ---------------------------- */ diff --git a/src/arch/x86/cbmem.c b/src/arch/x86/cbmem.c index 648633f..abd163d 100644 --- a/src/arch/x86/cbmem.c +++ b/src/arch/x86/cbmem.c @@ -11,7 +11,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <cbmem.h> #include <arch/acpi.h> diff --git a/src/arch/x86/mmap_boot.c b/src/arch/x86/mmap_boot.c index abfa024..98b5643 100644 --- a/src/arch/x86/mmap_boot.c +++ b/src/arch/x86/mmap_boot.c @@ -15,7 +15,6 @@ #include <boot_device.h> #include <endian.h> -#include <stdlib.h> /* The ROM is memory mapped just below 4GiB. Form a pointer for the base. */ #define rom_base ((void *)(uintptr_t)(0x100000000ULL-CONFIG_ROM_SIZE)) -- To view, visit https://review.coreboot.org/c/coreboot/+/32820 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I79f065703b5249ca9630b06de7142bc52675076e Gerrit-Change-Number: 32820 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

2 6

Change in ...coreboot[master]: southbridge: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 19 Dec '19

19 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32829 Change subject: southbridge: Use 'include <stdlib.h>' when appropriate ...................................................................... southbridge: Use 'include <stdlib.h>' when appropriate Change-Id: I5728b44fdd680b21e951397a2390e24f9171ac34 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/amd/agesa/hudson/spi.c M src/southbridge/amd/amd8111/lpc.c M src/southbridge/intel/bd82x6x/me_status.c M src/southbridge/intel/common/smbus.c M src/southbridge/intel/fsp_rangeley/early_init.c M src/southbridge/intel/i82801ix/i82801ix.c M src/southbridge/intel/i82801jx/i82801jx.c M src/southbridge/intel/lynxpoint/me_status.c M src/southbridge/intel/lynxpoint/serialio.c M src/southbridge/nvidia/ck804/lpc.c M src/southbridge/nvidia/mcp55/lpc.c 11 files changed, 10 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/32829/1 diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index 9c546c5..fb9f7a1 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -12,8 +12,9 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ + +#include <stddef.h> #include <stdint.h> -#include <stdlib.h> #include <device/mmio.h> #include <console/console.h> #include <spi_flash.h> @@ -21,7 +22,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> - #include <Proc/Fch/FchPlatform.h> #define SPI_REG_OPCODE 0x0 diff --git a/src/southbridge/amd/amd8111/lpc.c b/src/southbridge/amd/amd8111/lpc.c index c4a7896..11e852a 100644 --- a/src/southbridge/amd/amd8111/lpc.c +++ b/src/southbridge/amd/amd8111/lpc.c @@ -28,7 +28,6 @@ #include <arch/acpigen.h> #include <cpu/amd/powernow.h> #endif -#include <stdlib.h> #include "amd8111.h" diff --git a/src/southbridge/intel/bd82x6x/me_status.c b/src/southbridge/intel/bd82x6x/me_status.c index b202376..1225cb1 100644 --- a/src/southbridge/intel/bd82x6x/me_status.c +++ b/src/southbridge/intel/bd82x6x/me_status.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <console/console.h> + #include "me.h" #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) diff --git a/src/southbridge/intel/common/smbus.c b/src/southbridge/intel/common/smbus.c index af1eb60..6d901d6 100644 --- a/src/southbridge/intel/common/smbus.c +++ b/src/southbridge/intel/common/smbus.c @@ -18,12 +18,10 @@ #include <arch/io.h> #include <console/console.h> #include <device/smbus_def.h> -#include <stdlib.h> #include <types.h> #include "smbus.h" - #if CONFIG(DEBUG_SMBUS) #define dprintk(args...) printk(BIOS_DEBUG, ##args) #else diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c index 32e3bb5..aade4db 100644 --- a/src/southbridge/intel/fsp_rangeley/early_init.c +++ b/src/southbridge/intel/fsp_rangeley/early_init.c @@ -16,7 +16,6 @@ */ #include <stdint.h> -#include <stdlib.h> #include <console/console.h> #include <arch/io.h> #include <device/mmio.h> @@ -24,6 +23,7 @@ #include <device/pci_def.h> #include <pc80/mc146818rtc.h> #include <version.h> + #include "pci_devs.h" #include "soc.h" diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index 99078dc..aa81984 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -16,12 +16,12 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <arch/io.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> #include <console/console.h> + #include "i82801ix.h" typedef struct southbridge_intel_i82801ix_config config_t; diff --git a/src/southbridge/intel/i82801jx/i82801jx.c b/src/southbridge/intel/i82801jx/i82801jx.c index ec5576d..bf85f98 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.c +++ b/src/southbridge/intel/i82801jx/i82801jx.c @@ -16,12 +16,12 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <arch/io.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> #include <console/console.h> + #include "i82801jx.h" typedef struct southbridge_intel_i82801jx_config config_t; diff --git a/src/southbridge/intel/lynxpoint/me_status.c b/src/southbridge/intel/lynxpoint/me_status.c index 9ca5552..d1ece5a 100644 --- a/src/southbridge/intel/lynxpoint/me_status.c +++ b/src/southbridge/intel/lynxpoint/me_status.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <console/console.h> + #include "me.h" #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index 23d8125..1557c8d 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -21,7 +21,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <stdlib.h> + #include "pch.h" #include "nvs.h" diff --git a/src/southbridge/nvidia/ck804/lpc.c b/src/southbridge/nvidia/ck804/lpc.c index 2123554..cbf5320 100644 --- a/src/southbridge/nvidia/ck804/lpc.c +++ b/src/southbridge/nvidia/ck804/lpc.c @@ -29,9 +29,9 @@ #include <arch/ioapic.h> #include <arch/acpi.h> #include <cpu/x86/lapic.h> -#include <stdlib.h> #include <assert.h> #include <cpu/amd/powernow.h> + #include "chip.h" #define NMI_OFF 0 diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index 1aef631..b80a524 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -31,8 +31,8 @@ #include <arch/ioapic.h> #include <cpu/x86/lapic.h> #include <arch/acpi.h> -#include <stdlib.h> #include <cpu/amd/powernow.h> + #include "mcp55.h" #define NMI_OFF 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/32829 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5728b44fdd680b21e951397a2390e24f9171ac34 Gerrit-Change-Number: 32829 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 7

Change in ...coreboot[master]: nb/sandybridge/raminit_common.c: Remove variable set but not used
by HAOUAS Elyes (Code Review) 13 Dec '19

13 Dec '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33005 Change subject: nb/sandybridge/raminit_common.c: Remove variable set but not used ...................................................................... nb/sandybridge/raminit_common.c: Remove variable set but not used Change-Id: I109353775fe4ecce6a05ef88781939243f398d17 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 9 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/33005/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 5347c5c..b8ad3c0 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1824,7 +1824,7 @@ static void adjust_high_timB(ramctr_timing * ctrl) { - int channel, slotrank, lane, old; + int channel, slotrank, lane; MCHBAR32(0x3400) = 0x200; FOR_ALL_POPULATED_CHANNELS { fill_pattern1(ctrl, channel); @@ -1898,15 +1898,18 @@ 0x100 * channel + 4); res |= ((u64) MCHBAR32(lane_registers[lane] + 0x100 * channel + 8)) << 32; - old = ctrl->timings[channel][slotrank].lanes[lane].timB; - ctrl->timings[channel][slotrank].lanes[lane].timB += - get_timB_high_adjust(res) * 64; printram("High adjust %d:%016llx\n", lane, res); - printram("Bval+: %d, %d, %d, %x -> %x\n", channel, - slotrank, lane, old, + printram("Bval+: %d, %d, %d, %x", channel, + slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane]. timB); + ctrl->timings[channel][slotrank].lanes[lane].timB += + get_timB_high_adjust(res) * 64; + printram(" -> %x\n", + ctrl->timings[channel][slotrank].lanes[lane]. + timB); + } } MCHBAR32(0x3400) = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/33005 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I109353775fe4ecce6a05ef88781939243f398d17 Gerrit-Change-Number: 33005 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [RFC] Initial commit to support SKL SP and OCP Tiogapass platform
by Name of user not set (Code Review) 03 Dec '19

03 Dec '19

Name of user not set #1002246 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31205 Change subject: [RFC] Initial commit to support SKL SP and OCP Tiogapass platform ...................................................................... [RFC] Initial commit to support SKL SP and OCP Tiogapass platform Summary: This commit adds support for SK SP and OCP Tiogapass platform: * Added microcode files. * Added FSP header files. * Updated skylake soc code to accomodate FSP 2.0. * Added tiogapass platform code to accomodate FSP 2.0. With this commit, it is able to build coreboot.rom image. The 3 FSP binaries are added to the coreboot image. It looks okay by examining the coreboot.rom file through ifdtool command. However, when booting with this image, no postcode is observed on port 80, no UART message shows up. Debugging is on-going. This commit is submitted as draft to enable early review feedback. Change-Id: I389355162eb9515b533a8d7f77cc8f03b8beb019 Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> test Change-Id: I033a52bc3f0b86f0ec1db8325b7435d20d194fda --- M src/Kconfig M src/drivers/intel/fsp2_0/include/fsp/api.h A src/mainboard/ocp/tiogapass/Kconfig A src/mainboard/ocp/tiogapass/Kconfig.name A src/mainboard/ocp/tiogapass/Makefile.inc A src/mainboard/ocp/tiogapass/acpi/mainboard.asl A src/mainboard/ocp/tiogapass/board_id.c A src/mainboard/ocp/tiogapass/board_id.h A src/mainboard/ocp/tiogapass/board_info.txt A src/mainboard/ocp/tiogapass/bootblock.c A src/mainboard/ocp/tiogapass/cmos.default A src/mainboard/ocp/tiogapass/cmos.layout A src/mainboard/ocp/tiogapass/devicetree.cb A src/mainboard/ocp/tiogapass/dsdt.asl A src/mainboard/ocp/tiogapass/gpio.h A src/mainboard/ocp/tiogapass/pei_data.c A src/mainboard/ocp/tiogapass/ramstage.c A src/mainboard/ocp/tiogapass/romstage.c A src/mainboard/ocp/tiogapass/spd/Makefile.inc A src/mainboard/ocp/tiogapass/spd/spd.h A src/mainboard/ocp/tiogapass/spd/spd_util.c M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/include/fsp20/soc/ramstage.h M src/soc/intel/skylake/irq.c M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/intel/skylake/vr_config.c M src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DebugSupport.h A src/vendorcode/intel/fsp/fsp2_0/skykabylake/FirmwareVersionInfoHob.h A src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h A src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h A src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h A src/vendorcode/intel/fsp/fsp2_0/skykabylake/FsptUpd.h 34 files changed, 1,968 insertions(+), 162 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/31205/1 diff --git a/src/Kconfig b/src/Kconfig index a069f63..7de3335 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -360,6 +360,7 @@ source "src/ec/*/*/Kconfig" # FIXME move to vendorcode source "src/drivers/intel/fsp1_0/Kconfig" +source "src/drivers/intel/fsp2_0/Kconfig" source "src/southbridge/intel/common/firmware/Kconfig" source "src/vendorcode/*/Kconfig" diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 5ed3801..666020a 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -66,9 +66,9 @@ void platform_fsp_notify_status(enum fsp_notify_phase phase); /* Initialize memory margin analysis settings. */ -void setup_mma(FSP_M_CONFIG *memory_cfg); +void setup_mma(FSPM_CONFIG *memory_cfg); /* Update the SOC specific memory config param for mma. */ -void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, +void soc_update_memory_params_for_mma(FSPM_CONFIG *memory_cfg, struct mma_config_param *mma_cfg); /* diff --git a/src/mainboard/ocp/tiogapass/Kconfig b/src/mainboard/ocp/tiogapass/Kconfig new file mode 100644 index 0000000..c411b15 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/Kconfig @@ -0,0 +1,58 @@ +if BOARD_OCP_TIOGAPASS + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_32768 + select CONSOLE_SERIAL + select DRIVERS_UART + select GENERIC_SPD_BIN + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select EC_ACPI + select HAVE_OPTION_TABLE + select HAVE_SMI_HANDLER + select SERIRQ_CONTINUOUS_MODE + select SKYLAKE_SOC_PCH_H + select SOC_INTEL_SKYLAKE + select SUPERIO_NUVOTON_NCT6776 + select SUPERIO_NUVOTON_NCT6776_COM_A + select MAINBOARD_USES_FSP2_0 + select HAVE_CMOS_DEFAULT + + +config PLATFORM_USES_FSP2_0 + bool "FSP driver 2.0" + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_DIR + string + default "ocp/tiogapass" + +config MAINBOARD_PART_NUMBER + string + default "Tioga Pass" + +config MAINBOARD_FAMILY + string + default "OCP_TiogaPass" + +config CBFS_SIZE + hex + default 0x1000000 + +config VIRTUAL_ROM_SIZE + hex + default 0x2000000 + +config MAX_CPUS + int + default 8 + +config TPM_PIRQ + hex + default 0x18 # GPP_E0_IRQ + +endif # BOARD_OCP_TIOGAPASS diff --git a/src/mainboard/ocp/tiogapass/Kconfig.name b/src/mainboard/ocp/tiogapass/Kconfig.name new file mode 100644 index 0000000..0c57fd3 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_OCP_TIOGAPASS + bool "Tioga Pass" diff --git a/src/mainboard/ocp/tiogapass/Makefile.inc b/src/mainboard/ocp/tiogapass/Makefile.inc new file mode 100644 index 0000000..77cdb16 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/Makefile.inc @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +subdirs-y += spd + +bootblock-y += bootblock.c +romstage-y += pei_data.c +romstage-y += board_id.c + +ramstage-y += ramstage.c diff --git a/src/mainboard/ocp/tiogapass/acpi/mainboard.asl b/src/mainboard/ocp/tiogapass/acpi/mainboard.asl new file mode 100644 index 0000000..5174eeb --- /dev/null +++ b/src/mainboard/ocp/tiogapass/acpi/mainboard.asl @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/gpio.h> diff --git a/src/mainboard/ocp/tiogapass/board_id.c b/src/mainboard/ocp/tiogapass/board_id.c new file mode 100644 index 0000000..a362b08 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/board_id.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include "board_id.h" +#include <ec/acpi/ec.h> +#include <stdint.h> + +/* + * Get Board ID via EC I/O port write/read + */ +int get_board_id(void) +{ + uint8_t buffer[2]; + uint8_t index; + if (send_ec_command(EC_FAB_ID_CMD) == 0) { + for (index = 0; index < sizeof(buffer); index++) + buffer[index] = recv_ec_data(); + return (buffer[1] << 8) | buffer[0]; + } + return -1; +} diff --git a/src/mainboard/ocp/tiogapass/board_id.h b/src/mainboard/ocp/tiogapass/board_id.h new file mode 100644 index 0000000..881866f --- /dev/null +++ b/src/mainboard/ocp/tiogapass/board_id.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MAINBOARD_BOARD_ID_H_ +#define _MAINBOARD_BOARD_ID_H_ + +/* Mobile Board Id 0x00 - 0xFF */ +#define BOARD_ID_SKL_A0_RVP3 0x04 +#define BOARD_ID_SKL_RVP7 0x0B + +/* 60-6F reserved for KBL RVPs */ +#define BOARD_ID_KBL_LPDDR3_RVP3 0x60 +#define BOARD_ID_KBL_LPDDR3_RVP7 0x64 + +/* Board/FAB ID Command */ +#define EC_FAB_ID_CMD 0x0D + +/* + * Returns board information (board id[15:8] and + * Fab info[7:0]) on success and < 0 on error + */ +int get_board_id(void); + +#endif /* _MAINBOARD_BOARD_ID_H_ */ diff --git a/src/mainboard/ocp/tiogapass/board_info.txt b/src/mainboard/ocp/tiogapass/board_info.txt new file mode 100644 index 0000000..25dac38 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/board_info.txt @@ -0,0 +1,5 @@ +Board name: Tioga Pass +Category: server +ROM protocol: SPI +ROM socketed: yes +Release year: 2017 diff --git a/src/mainboard/ocp/tiogapass/bootblock.c b/src/mainboard/ocp/tiogapass/bootblock.c new file mode 100644 index 0000000..cf9740d --- /dev/null +++ b/src/mainboard/ocp/tiogapass/bootblock.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/gpio.h> +#include "gpio.h" + +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> + +#define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) + +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't do. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + +void bootblock_mainboard_init(void) +{ + early_config_gpio(); +} + +void bootblock_mainboard_early_init(void) +{ + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/ocp/tiogapass/cmos.default b/src/mainboard/ocp/tiogapass/cmos.default new file mode 100644 index 0000000..cd8bd47 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/cmos.default @@ -0,0 +1,4 @@ +boot_option=Fallback +debug_level=Spew +power_on_after_fail=Disable +nmi=Enable diff --git a/src/mainboard/ocp/tiogapass/cmos.layout b/src/mainboard/ocp/tiogapass/cmos.layout new file mode 100644 index 0000000..83a2e05 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/cmos.layout @@ -0,0 +1,117 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +#401 7 r 0 unused + +# coreboot config options: southbridge +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#544 440 r 0 unused + + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/ocp/tiogapass/devicetree.cb b/src/mainboard/ocp/tiogapass/devicetree.cb new file mode 100644 index 0000000..9b23a0e --- /dev/null +++ b/src/mainboard/ocp/tiogapass/devicetree.cb @@ -0,0 +1,293 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2017 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_B" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # FSP Configuration + register "EnableAzalia" = "1" + register "DspEnable" = "1" + register "IoBufferOwnership" = "3" + register "SmbusEnable" = "1" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "InternalGfx" = "1" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "0" + register "Heci3Enabled" = "0" + + register "SaGv" = "3" + register "PmTimerDisabled" = "0" + + # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch + # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s + register "PmConfigSlpS3MinAssert" = "0x02" + + # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s + register "PmConfigSlpS4MinAssert" = "0x04" + + # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s + register "PmConfigSlpSusMinAssert" = "0x03" + + # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s + register "PmConfigSlpAMinAssert" = "0x03" + + # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled + register "SerialIrqConfigSirqEnable" = "0x01" + register "SerialIrqConfigSirqMode" = "0x01" + + # VR Settings Configuration for 5 Domains + #+----------------+-------+-------+-------------+-------------+-------+ + #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | + #+----------------+-------+-------+-------------+-------------+-------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | 0 | + #| IccMax | 7A | 34A | 34A | 35A | 35A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-------+-------+-------------+-------------+-------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x10, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x1C, \ + .voltage_limit = 0x5F0 \ + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x88, \ + .voltage_limit = 0x5F0 \ + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x8C ,\ + .voltage_limit = 0x5F0 \ + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, \ + .psi1threshold = 0x50, \ + .psi2threshold = 0x14, \ + .psi3threshold = 0x4, \ + .psi3enable = 1, \ + .psi4enable = 1, \ + .imon_slope = 0x0, \ + .imon_offset = 0x0, \ + .icc_max = 0x8C, \ + .voltage_limit = 0x5F0 \ + }" + + # Skip coreboot MP Init + register "common_soc_config" = "{ + .use_fsp_mp_init = 1, + }" + + # Enable x1 slot + register "PcieRpEnable[7]" = "1" + register "PcieRpClkReqSupport[7]" = "1" + register "PcieRpClkReqNumber[7]" = "3" #uses SRCCLKREQ3 + + # Enable x4 slot + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "4" #uses SRCCLKREQ4 + + # Enable Root port 6 and 13. + register "PcieRpEnable[5]" = "1" + register "PcieRpEnable[12]" = "1" + + # Enable CLKREQ# + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqSupport[12]" = "1" + + # RP 6 uses SRCCLKREQ1# while RP `3 uses SRCCLKREQ2# + register "PcieRpClkReqNumber[5]" = "0" + register "PcieRpClkReqNumber[12]" = "1" + + register "EnableLan" = "1" + + # USB related + register "SsicPortEnable" = "1" + + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # OTG + register "usb2_ports[1]" = "USB2_PORT_MID(OC3)" # Touch Pad + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 BT + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Touch Panel + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Front Panel + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # Front Panel + register "usb2_ports[7]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb) + register "usb2_ports[8]" = "USB2_PORT_MID(OC2)" # Stacked conn (lan + usb) + register "usb2_ports[9]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK + register "usb2_ports[10]" = "USB2_PORT_MID(OC1)" # LAN MAGJACK + register "usb2_ports[11]" = "USB2_PORT_MID(OC_SKIP)" # Finger print sensor + register "usb2_ports[12]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn + register "usb2_ports[13]" = "USB2_PORT_MID(OC4)" # USB 2 stack conn + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC5)" # OTG + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # Flex + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # IVCAM + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC0)" # Front Panel + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC2)" # Stack Conn + register "usb3_ports[9]" = "USB3_PORT_DEFAULT(OC1)" # LAN MAGJACK + + register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V + + # Must leave UART0 enabled or SD/eMMC will not work as PCI + + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0a" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x0b" + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0b" + register "pirqh_routing" = "0x0b" + + register "PmTimerDisabled" = "0" + + register "EnableSata" = "1" + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ \ + [0] = 1, \ + [1] = 1, \ + [2] = 1, \ + [3] = 1, \ + [4] = 1, \ + [5] = 1, \ + [6] = 1, \ + [7] = 1, \ + }" + register "SerialIoDevMode" = "{ \ + [PchSerialIoIndexI2C0] = PchSerialIoPci, \ + [PchSerialIoIndexI2C1] = PchSerialIoPci, \ + [PchSerialIoIndexI2C2] = PchSerialIoPci, \ + [PchSerialIoIndexI2C3] = PchSerialIoPci, \ + [PchSerialIoIndexI2C4] = PchSerialIoPci, \ + [PchSerialIoIndexI2C5] = PchSerialIoPci, \ + [PchSerialIoIndexSpi0] = PchSerialIoPci, \ + [PchSerialIoIndexSpi1] = PchSerialIoPci, \ + [PchSerialIoIndexUart0] = PchSerialIoPci, \ + [PchSerialIoIndexUart1] = PchSerialIoPci, \ + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ + }" + + # PL2 override 25W + register "tdp_pl2_override" = "25" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Enable/Disable VMX feature + register "VmxEnable" = "0" + # Use default SD card detect GPIO configuration + #register "sdcard_cd_gpio_default" = "GPP_A7" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 19.0 on end # UART #2 + device pci 19.1 on end # I2C #5 + device pci 19.2 on end # I2C #4 + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 on end # UART #0 + device pci 1e.1 on end # UART #1 + device pci 1e.2 on end # GSPI #0 + device pci 1e.3 on end # GSPI #1 + device pci 1e.4 off end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 off end # SDCard + device pci 1f.0 on + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/ocp/tiogapass/dsdt.asl b/src/mainboard/ocp/tiogapass/dsdt.asl new file mode 100644 index 0000000..45d9a85 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/dsdt.asl @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <soc/intel/skylake/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/ocp/tiogapass/gpio.h b/src/mainboard/ocp/tiogapass/gpio.h new file mode 100644 index 0000000..f8db6cd --- /dev/null +++ b/src/mainboard/ocp/tiogapass/gpio.h @@ -0,0 +1,183 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef _GPIORVP8_H +#define _GPIORVP8_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +/* TCA6424A I/O Expander */ +#define IO_EXPANDER_BUS 4 +#define IO_EXPANDER_0_ADDR 0x22 +#define IO_EXPANDER_P0CONF 0x0C /* Port 0 conf offset */ +#define IO_EXPANDER_P0DOUT 0x04 /* Port 0 data offset */ +#define IO_EXPANDER_P1CONF 0x0D +#define IO_EXPANDER_P1DOUT 0x05 +#define IO_EXPANDER_P2CONF 0x0E +#define IO_EXPANDER_P2DOUT 0x06 +#define IO_EXPANDER_1_ADDR 0x23 + +/* GPE_EC_WAKE */ +#define GPE_EC_WAKE GPE0_LAN_WAK +#define EC_SMI_GPI GPP_I3 + +/* + * Gpio based irq for touchpad, 18th index in North Bank + * MAX_DIRECT_IRQ + GPSW_SIZE + 19 + */ +#define KBLRVP_TOUCHPAD_IRQ 33 + +#define KBLRVP_TOUCH_IRQ 31 + +#define BOARD_TOUCHPAD_NAME "touchpad" +#define BOARD_TOUCHPAD_IRQ KBLRVP_TOUCHPAD_IRQ +#define BOARD_TOUCHPAD_I2C_BUS 0 +#define BOARD_TOUCHPAD_I2C_ADDR 0x20 + +#define BOARD_TOUCHSCREEN_NAME "touchscreen" +#define BOARD_TOUCHSCREEN_IRQ KBLRVP_TOUCH_IRQ +#define BOARD_TOUCHSCREEN_I2C_BUS 0 +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4c + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +/* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF3), +/* EC_LPC_IO0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF3), +/* EC_LPC_IO1*/ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF3), +/* EC_LPC_IO2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF3), +/* EC_LPC_IO3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF3), +/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF3), +/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF3), +/* PIRQAB */ PAD_CFG_GPI(GPP_A7, NONE, DEEP), +/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), +/* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF3), +/* PCH_LPC_CLK */ PAD_CFG_NF(GPP_A10, 20K_PD, DEEP, NF1), +/* PMEB */ PAD_CFG_GPI(GPP_A11, NONE, DEEP), +/* SUS_PWR_ACK_R */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), +/* PM_SUS_ESPI_RST */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF3), +/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, 20K_PU, DEEP, NF1), +/* BT_RF_KILL */ PAD_CFG_GPO(GPP_B3, 1, DEEP), +/* EXTTS_SNI_DRV1 */ PAD_CFG_NF(GPP_B4, NONE, DEEP, NF1), +/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), +/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* GPP_B_14_SPKR */ PAD_CFG_NF(GPP_B14, 20K_PD, DEEP, NF1), +/* GSPI0_MISO */ PAD_CFG_GPO(GPP_B17, 1, DEEP), +/* PCHHOTB */ PAD_CFG_NF(GPP_B23, 20K_PD, DEEP, NF2), +/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), +/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), +/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 1, DEEP), +/* SML0_CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), +/* SML0_DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), +/* SML1_CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), +/* SML1_DATA */ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +/* UART0_RTS_N */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), +/* UART0_CTS_N */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), +/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* UART2_RTS_N */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), +/* UART2_CTS_N */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), +/* SSP0_SFRM */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), +/* SSP0_TXD */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), +/* SSP0_RXD */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), +/* SSP0_SCLK */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), +/* SATAE_IFDET */ PAD_CFG_NF(GPP_E0, 20K_PU, DEEP, NF1), +/* SATAE_IFDET */ PAD_CFG_NF(GPP_E1, 20K_PU, DEEP, NF1), +/* CPU_GP0 */ PAD_CFG_NF(GPP_E3, NONE, DEEP, NF1), +/* SSD_SATA_DEVSLP */ PAD_CFG_NF(GPP_E4, NONE, DEEP, NF1), +/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), +/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), +/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), +/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), +/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), +/* SATAXPCIE_4 */ PAD_CFG_NF(GPP_F1, 20K_PU, DEEP,NF1), +/* SATA_DEVSLP_3 */ PAD_CFG_GPI_ACPI_SCI(GPP_F5, NONE, DEEP, YES), +/* SATA_DEVSLP_4 */ PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), +/* SATA_SCLOCK */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), +/* SATA_SLOAD */ PAD_CFG_GPI(GPP_F11, NONE, DEEP), +/* SATA_SDATAOUT1 */ PAD_CFG_GPI_APIC(GPP_F12, NONE, DEEP), +/* SATA_SDATAOUT0 */ PAD_CFG_GPI_APIC(GPP_F13, NONE, DEEP), +/* H_SKTOCC_N */ PAD_CFG_GPI_APIC(GPP_F14, NONE, DEEP), +/* USB_OC4_R_N */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), +/* USB_OC5_R_N */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), +/* USB_OC6_R_N */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), +/* USB_OC7_R_N */ PAD_CFG_GPO(GPP_F18, 1, DEEP), +/* GPIO_PEG_RESET */ PAD_CFG_GPO(GPP_F22, 1, DEEP), +/* VCORE_VBOOST_CTRL */ PAD_CFG_GPO(GPP_F23, 0, DEEP), +/* FAN_TACH_0 */ PAD_CFG_GPO(GPP_G0, 1, DEEP), +/* FAN_TACH_1 */ PAD_CFG_GPO(GPP_G1, 1, DEEP), +/* FAN_TACH_2 */ PAD_CFG_GPI_ACPI_SCI(GPP_G2, NONE, DEEP, YES), +/* FAN_TACH_3 */ PAD_CFG_GPI_ACPI_SCI(GPP_G3, NONE, DEEP, YES), +/* FAN_TACH_4 */ PAD_CFG_GPO(GPP_G4, 1, DEEP), +/* FAN_TACH_5 */ PAD_CFG_GPI_APIC(GPP_G5, NONE, DEEP), +/* FAN_TACH_6 */ PAD_CFG_GPI_ACPI_SCI(GPP_G6, NONE, DEEP, YES), +/* FAN_TACH_7 */ PAD_CFG_GPO(GPP_G7, 1, DEEP), +/* GSXDOUT */ PAD_CFG_GPI_ACPI_SCI(GPP_G12, 20K_PD, DEEP, YES), +/* GSXSLOAD */ PAD_CFG_GPO(GPP_G13, 1, DEEP), +/* GSXDIN */ PAD_CFG_GPI_ACPI_SCI(GPP_G14, NONE, DEEP, YES), +/* GSXSRESETB */ PAD_CFG_GPO(GPP_G15, 0, DEEP), +/* GSXCLK */ PAD_CFG_GPO(GPP_G16, 0, DEEP), +/* NMIB */ PAD_CFG_GPI_APIC(GPP_G18, NONE, DEEP), +/* SMIB */ PAD_CFG_NF(GPP_G19, NONE, DEEP, NF1), +/* TEST_SETUP_MENU */ PAD_CFG_GPI_APIC(GPP_G20, NONE, DEEP), +/* P_INTF_N */ PAD_CFG_GPI_ACPI_SCI(GPP_G21, NONE, DEEP, YES), +/* PCH_PEGSLOT1 */ PAD_CFG_GPO(GPP_G22, 1, DEEP), +/* IVCAM_DFU_R */ PAD_CFG_GPO(GPP_G23, 1, DEEP), +/* SRCCLKREQB_8 */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF1), +/* SML2CLK */ PAD_CFG_GPI(GPP_H10, NONE, DEEP), +/* SML2DATA */ PAD_CFG_GPI(GPP_H11, NONE, DEEP), +/* SML3CLK */ PAD_CFG_GPI_APIC(GPP_H13, NONE, DEEP), +/* SML3DATA */ PAD_CFG_GPI_APIC(GPP_H14, NONE, DEEP), +/* SML3ALERTB */ PAD_CFG_GPI_APIC(GPP_H15, NONE, DEEP), +/* SML4DATA */ PAD_CFG_GPO(GPP_H17, 1, DEEP), +/* LED_DRIVE */ PAD_CFG_GPO(GPP_H23, 0, DEEP), +/* DDSP_HPD_0 */ PAD_CFG_NF(GPP_I0, NONE, DEEP, NF1), +/* DDSP_HPD_1 */ PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), +/* DDSP_HPD_2 */ PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), +/* DDSP_HPD_1 */ PAD_CFG_GPI_ACPI_SMI(GPP_I3, NONE, DEEP, YES), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_I5, NONE, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_I6, 20K_PD, DEEP, NF1), +/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_I8, 20K_PD, DEEP, NF1), +/* DDPD_CTRLCLK */ PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), +/* DDPD_CTRLDATA */ PAD_CFG_NF(GPP_I10, 20K_PD, DEEP, NF1), +/* EC_PCH_ACPRESENT */ PAD_CFG_GPO(GPD1, 0, DEEP), +/* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), +/* PM_PWRBTN_R_N */ PAD_CFG_NF(GPD3, 20K_PU, DEEP, NF1), +/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), +/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), +/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), +/* USB_WAKEOUT_N */ PAD_CFG_NF(GPD7, NONE, DEEP, NF1), +/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), +/* PCH_SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), +/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), + +}; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +}; + + +#endif +#endif diff --git a/src/mainboard/ocp/tiogapass/pei_data.c b/src/mainboard/ocp/tiogapass/pei_data.c new file mode 100644 index 0000000..ac4ce95 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/pei_data.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> +#include "spd/spd.h" + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + mainboard_fill_dq_map_data(&pei_data->dq_map); + mainboard_fill_dqs_map_data(&pei_data->dqs_map); + mainboard_fill_rcomp_res_data(&pei_data->RcompResistor); + mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget); +} diff --git a/src/mainboard/ocp/tiogapass/ramstage.c b/src/mainboard/ocp/tiogapass/ramstage.c new file mode 100644 index 0000000..6fef017 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/ramstage.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <console/console.h> +#include <device/i2c_simple.h> +#include <soc/ramstage.h> +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +// params->CdClock = 3; + + /* Enable Virtual Channel 1 */ +// params->PchHdaVcType = 0x1; +} + +static void ioexpander_init(void *unused) +{ + printk(BIOS_DEBUG, "Programming TCA6424A I/O expander\n"); + + /* I/O Expander 1, Port 0 Data */ + i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_0_ADDR, IO_EXPANDER_P0DOUT, + 0xF7); + /* Port 0 Configuration */ + i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_0_ADDR, IO_EXPANDER_P0CONF, + 0xE0); + + /* Port 1 Data */ + i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_0_ADDR, IO_EXPANDER_P1DOUT, + 0x9E); + /* Port 1 Configuration */ + i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_0_ADDR, IO_EXPANDER_P1CONF, + 0x8C); + + /* Port 2 Data */ + i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_0_ADDR, IO_EXPANDER_P2DOUT, + 0xDA); + /* Port 2 Configuration */ + i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_0_ADDR, IO_EXPANDER_P2CONF, + 0x08); + + /* I/O Expander 2, Port 0 Data */ + i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_1_ADDR, IO_EXPANDER_P0DOUT, + 0xFF); + /* Port 0 Configuration */ + i2c_writeb(IO_EXPANDER_BUS, IO_EXPANDER_1_ADDR, IO_EXPANDER_P0CONF, + 0x00); + +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, ioexpander_init, NULL); diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c new file mode 100644 index 0000000..230cc50 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/romstage.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/byteorder.h> +#include <cbfs.h> +#include <console/console.h> +#include <fsp/api.h> +#include <gpio.h> +#include "gpio.h" +#include <soc/romstage.h> +#include <soc/gpio.h> +#include "spd/spd.h" +#include <string.h> +#include <spd_bin.h> +#include "board_id.h" + + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + FSPM_CONFIG *mem_cfg; + mem_cfg = &mupd->FspmConfig; + u8 spd_index = (get_board_id() >> 5) & 0x7; + + printk(BIOS_INFO, "SPD index %d\n", spd_index); +/* + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); +*/ + if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP3)) { + struct region_device spd_rdev; + +// mem_cfg->DqPinsInterleaved = 0; + if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + die("spd.bin not found\n"); +// mem_cfg->MemorySpdDataLen = region_device_sz(&spd_rdev); + /* Memory leak is ok since we have memory mapped boot media */ +// mem_cfg->MemorySpdPtr00 = (uintptr_t)rdev_mmap_full(&spd_rdev); + } else { /* CONFIG_BOARD_INTEL_KBLRVP7 and CONFIG_BOARD_INTEL_KBLRVP8 */ + struct spd_block blk = { + .addr_map = { 0x50, 0x51, 0x52, 0x53, }, + }; + +// mem_cfg->DqPinsInterleaved = 1; + get_spd_smbus(&blk); +// mem_cfg->MemorySpdDataLen = blk.len; +// mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; +// mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[2]; + if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8)) { +// mem_cfg->MemorySpdPtr01 = (uintptr_t)blk.spd_array[1]; +// mem_cfg->MemorySpdPtr11 = (uintptr_t)blk.spd_array[3]; + } + + } +// mupd->FspmTestConfig.DmiVc1 = 1; +// if (IS_ENABLED(CONFIG_BOARD_INTEL_KBLRVP8)) +// mem_cfg->UserBd = BOARD_TYPE_DESKTOP; +} diff --git a/src/mainboard/ocp/tiogapass/spd/Makefile.inc b/src/mainboard/ocp/tiogapass/spd/Makefile.inc new file mode 100644 index 0000000..721736d --- /dev/null +++ b/src/mainboard/ocp/tiogapass/spd/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## Copyright (C) 2015 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += spd_util.c diff --git a/src/mainboard/ocp/tiogapass/spd/spd.h b/src/mainboard/ocp/tiogapass/spd/spd.h new file mode 100644 index 0000000..a5f1af3 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/spd/spd.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#define RCOMP_TARGET_PARAMS 0x5 + +void mainboard_fill_dq_map_data(void *dq_map_ptr); +void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(void *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); + +#endif diff --git a/src/mainboard/ocp/tiogapass/spd/spd_util.c b/src/mainboard/ocp/tiogapass/spd/spd_util.c new file mode 100644 index 0000000..2c26d78 --- /dev/null +++ b/src/mainboard/ocp/tiogapass/spd/spd_util.c @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> +#include "spd.h" + +void mainboard_fill_dq_map_data(void *dq_map_ptr) +{ + /* DQ byte map */ + const u8 dq_map[2][12] = { + { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 }, + { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dqs_map_data(void *dqs_map_ptr) +{ + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + { 0, 1, 3, 2, 4, 5, 6, 7 }, + { 1, 0, 4, 5, 2, 3, 6, 7 } }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +void mainboard_fill_rcomp_res_data(void *rcomp_ptr) +{ + /* Rcomp resistor */ + const u16 RcompResistor[3] = { 121, 81, 100 }; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) +{ + /* Rcomp target */ + static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { + 100, 40, 20, 20, 26 }; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 506a041..f1f03d7 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -20,6 +20,7 @@ select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 + select BOOTBLOCK_CONSOLE select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS @@ -28,43 +29,40 @@ select COMMON_FADT select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select C_ENVIRONMENT_BOOTBLOCK - select FSP_M_XIP if MAINBOARD_USES_FSP2_0 - select FSP_T_XIP if FSP_CAR select GENERIC_GPIO_LIB select HAVE_FSP_GOP - select INTEL_DESCRIPTOR_MODE_CAPABLE + select HAVE_INTEL_FIRMWARE select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER - select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI select IOAPIC select MRC_SETTINGS_PROTECT select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PARALLEL_MP_AP_WORK + select PCIEXP_ASPM + select PCIEXP_CLK_PM + select PCIEXP_COMMON_CLOCK + select PCIEXP_L1_SUB_STATE select PCIEX_LENGTH_64MB select REG_SCRIPT + select RTC select SA_ENABLE_DPR select SMM_TSEG select SMP - select PMC_GLOBAL_RESET_ENABLE_LOCK select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BLOCK - select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CPU select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT - select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GPIO_LEGACY_MACROS select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL select SOC_INTEL_COMMON_BLOCK_GSPI - select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SGX select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP - select SOC_INTEL_COMMON_BLOCK_UART select SOC_INTEL_COMMON_BLOCK_VMX select SOC_INTEL_COMMON_PCH_BASE select SOC_INTEL_COMMON_NHLT @@ -76,10 +74,6 @@ select TSC_SYNC_MFENCE select UDELAY_TSC -config CPU_INTEL_NUM_FIT_ENTRIES - int - default 10 - config MAINBOARD_USES_FSP2_0 bool default n @@ -88,7 +82,7 @@ def_bool y depends on MAINBOARD_USES_FSP2_0 select PLATFORM_USES_FSP2_0 - select UDK_2015_BINDING + select UDK_2017_BINDING select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select POSTCAR_CONSOLE select POSTCAR_STAGE @@ -98,7 +92,6 @@ depends on !MAINBOARD_USES_FSP2_0 select PLATFORM_USES_FSP1_1 select DISPLAY_FSP_ENTRY_POINTS - select SKIP_FSP_CAR config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC @@ -112,6 +105,10 @@ select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH +config BOOTBLOCK_RESETS + string + default "soc/intel/common/reset.c" + config CBFS_SIZE hex default 0x200000 @@ -124,6 +121,10 @@ hex default 0xfef00000 +config BOOTBLOCK_CPU_INIT + string + default "soc/intel/skylake/bootblock/bootblock.c" + config DCACHE_RAM_SIZE hex default 0x40000 @@ -162,6 +163,10 @@ help This option allows you to select MMIO Base Address of sideband bus. +config SERIAL_CPU_INIT + bool + default n + config SERIRQ_CONTINUOUS_MODE bool default n @@ -181,12 +186,31 @@ string default "8086,0406" +config UART_DEBUG + bool "Enable UART debug port." + default y + select CONSOLE_SERIAL + select DRIVERS_UART_8250MEM_32 + select NO_UART_ON_SUPERIO + +config UART_FOR_CONSOLE + int "Index for LPSS UART port to use for console" + default 2 if DRIVERS_UART_8250MEM + default 0 + help + Index for LPSS UART port to use for console: + 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2 + config SKYLAKE_SOC_PCH_H bool default n help Choose this option if you have a PCH-H chipset. +config CHIPSET_BOOTBLOCK_INCLUDE + string + default "soc/intel/skylake/bootblock/timestamp.inc" + config NHLT_DMIC_2CH bool default n @@ -247,19 +271,37 @@ help Include DSP firmware settings for DA7219 headset codec. -config FSP_HEADER_PATH - string "Location of FSP headers" - depends on MAINBOARD_USES_FSP2_0 - # Use KabylakeFsp for both Skylake and Kabylake as it supports both. - # SkylakeFsp is FSP 1.1 and therefore incompatible. - default "3rdparty/fsp/KabylakeFspBinPkg/Include/" if SOC_INTEL_SKYLAKE - default "3rdparty/fsp/KabylakeFspBinPkg/Include/" if SOC_INTEL_KABYLAKE +choice + prompt "Cache-as-ram implementation" + default USE_SKYLAKE_CAR_NEM_ENHANCED + help + This option allows you to select how cache-as-ram (CAR) is set up. -config FSP_FD_PATH - string - depends on FSP_USE_REPO - default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" if SOC_INTEL_SKYLAKE - default "3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd" if SOC_INTEL_KABYLAKE +config USE_SKYLAKE_CAR_NEM_ENHANCED + bool "Enhanced Non-evict mode" + select SOC_INTEL_COMMON_BLOCK_CAR + select INTEL_CAR_NEM_ENHANCED + help + A current limitation of NEM (Non-Evict mode) is that code and data + sizes are derived from the requirement to not write out any modified + cache line. With NEM, if there is no physical memory behind the + cached area, the modified data will be lost and NEM results will be + inconsistent. ENHANCED NEM guarantees that modified data is always + kept in cache while clean data is replaced. + +config USE_SKYLAKE_FSP_CAR + bool "Use FSP CAR" + select FSP_CAR + help + Use FSP APIs to initialize and tear down the Cache-As-Ram. + +endchoice + +config SKIP_FSP_CAR + bool "Skip cache as RAM setup in FSP" + default y + help + Skip Cache as RAM setup in FSP. config SPI_FLASH_INCLUDE_ALL_DRIVERS bool diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index ee2c928..c5451e6 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -2,7 +2,6 @@ subdirs-y += nhlt subdirs-y += romstage -subdirs-y += ../../../cpu/intel/common subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/x86/lapic @@ -11,7 +10,6 @@ subdirs-y += ../../../cpu/x86/tsc bootblock-y += bootblock/bootblock.c -bootblock-$(CONFIG_FSP_CAR) += fspcar.c bootblock-y += bootblock/cpu.c bootblock-y += i2c.c bootblock-y += bootblock/pch.c @@ -22,13 +20,13 @@ bootblock-y += pmutil.c bootblock-y += spi.c bootblock-y += lpc.c -bootblock-y += uart.c +bootblock-$(CONFIG_UART_DEBUG) += uart.c verstage-y += gspi.c verstage-y += pmutil.c verstage-y += i2c.c verstage-y += spi.c -verstage-y += uart.c +verstage-$(CONFIG_UART_DEBUG) += uart.c romstage-y += gpio.c romstage-y += gspi.c @@ -40,7 +38,7 @@ romstage-y += pmutil.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c romstage-y += spi.c -romstage-y += uart.c +romstage-$(CONFIG_UART_DEBUG) += uart.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += chip.c @@ -67,33 +65,22 @@ ramstage-y += spi.c ramstage-y += systemagent.c ramstage-y += thermal.c -ramstage-y += uart.c -ramstage-y += vr_config.c +ramstage-$(CONFIG_UART_DEBUG) += uart.c +//ramstage-y += vr_config.c smm-y += elog.c smm-y += gpio.c smm-y += p2sb.c smm-y += pmutil.c smm-y += smihandler.c -smm-y += uart.c +smm-$(CONFIG_UART_DEBUG) += uart.c postcar-y += memmap.c postcar-y += gspi.c postcar-y += spi.c -postcar-y += i2c.c -postcar-y += uart.c +postcar-$(CONFIG_UART_DEBUG) += uart.c - -# Skylake D0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_406ex/microcode.bin -# Skylake H Q0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_506ex/microcode.bin -# Kabylake H0, Y0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_806ex/microcode.bin -# Kabylake HB0 -cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_906ex/microcode.bin -# Missing for Skylake C0 (0x406e2), Kabylake G0 (0x406e8), Kabylake HA0 (0x506e8) -# since those are probably pre-release samples. +# cpu_microcode_bins += ??? CPPFLAGS_common += -I$(src)/soc/intel/skylake CPPFLAGS_common += -I$(src)/soc/intel/skylake/include @@ -103,6 +90,7 @@ CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/skylake else CPPFLAGS_common += -I$(src)/soc/intel/skylake/include/fsp20 +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/skykabylake endif # Currently used for microcode path. diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 3ade8d7..020dea3 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -20,12 +20,16 @@ #include <fsp/api.h> #include <arch/acpi.h> #include <arch/io.h> +#include <chip.h> +#include <compiler.h> +#include <bootstate.h> #include <console/console.h> #include <device/device.h> +#include <device/pci.h> #include <device/pci_ids.h> +#include <fsp/api.h> #include <fsp/util.h> #include <intelblocks/chip.h> -#include <intelblocks/itss.h> #include <intelblocks/xdci.h> #include <intelpch/lockdown.h> #include <romstage_handoff.h> @@ -34,7 +38,6 @@ #include <soc/interrupt.h> #include <soc/iomap.h> #include <soc/irq.h> -#include <soc/itss.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> #include <soc/systemagent.h> @@ -165,16 +168,8 @@ void soc_init_pre_device(void *chip_info) { - /* Snapshot the current GPIO IRQ polarities. FSP is setting a - * default policy that doesn't honor boards' requirements. */ - itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - /* Perform silicon specific init. */ fsp_silicon_init(romstage_handoff_is_resume()); - - /* Restore GPIO IRQ polarities back to previous settings. */ - itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - /* swap enabled PCI ports in device tree if needed */ pcie_override_devicetree_after_silicon_init(); } @@ -227,8 +222,9 @@ /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { - FSP_S_CONFIG *params = &supd->FspsConfig; - FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig; + FSPS_CONFIG *params = &supd->FspsConfig; +#if 0 +// FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig; static struct soc_intel_skylake_config *config; uintptr_t vbt_data = (uintptr_t)vbt_get(); int i; @@ -244,14 +240,14 @@ /* Set PsysPmax if it is available from DT */ if (config->psys_pmax) { /* PsysPmax is in unit of 1/8 Watt */ - tconfig->PsysPmax = config->psys_pmax * 8; - printk(BIOS_DEBUG, "psys_pmax = %d\n", tconfig->PsysPmax); +// tconfig->PsysPmax = config->psys_pmax * 8; +// printk(BIOS_DEBUG, "psys_pmax = %d\n", tconfig->PsysPmax); } - params->GraphicsConfigPtr = (u32) vbt_data; +// params->GraphicsConfigPtr = (u32) vbt_data; for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { - params->PortUsb20Enable[i] = +/* params->PortUsb20Enable[i] = config->usb2_ports[i].enable; params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; @@ -295,6 +291,7 @@ sizeof(params->PcieRpLtrEnable)); memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, sizeof(params->PcieRpHotPlug)); +*/ /* * PcieRpClkSrcNumber UPD is set to clock source number(0-6) for @@ -341,15 +338,6 @@ params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; params->ScsSdCardEnabled = config->ScsSdCardEnabled; - if (!!params->ScsEmmcHs400Enabled && !!config->EmmcHs400DllNeed) { - params->PchScsEmmcHs400DllDataValid = - !!config->EmmcHs400DllNeed; - params->PchScsEmmcHs400RxStrobeDll1 = - config->ScsEmmcHs400RxStrobeDll1; - params->PchScsEmmcHs400TxDataDll = - config->ScsEmmcHs400TxDataDll; - } - /* If ISH is enabled, enable ISH elements */ dev = dev_find_slot(0, PCH_DEVFN_ISH); if (dev) @@ -365,20 +353,18 @@ params->SataMode = config->SataMode; params->SataSpeedLimit = config->SataSpeedLimit; params->SataPwrOptEnable = config->SataPwrOptEnable; - params->EnableTcoTimer = !config->PmTimerDisabled; - tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; - tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; - tconfig->PowerLimit4 = config->PowerLimit4; +// tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; +// tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; /* * To disable HECI, the Psf needs to be left unlocked * by FSP till end of post sequence. Based on the devicetree * setting, we set the appropriate PsfUnlock policy in FSP, * do the changes and then lock it back in coreboot during finalize. */ - tconfig->PchSbAccessUnlock = (config->HeciEnabled == 0) ? 1 : 0; +// tconfig->PchSbAccessUnlock = (config->HeciEnabled == 0) ? 1 : 0; if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT) { - tconfig->PchLockDownBiosInterface = 0; +// tconfig->PchLockDownBiosInterface = 0; params->PchLockDownBiosLock = 0; params->PchLockDownSpiEiss = 0; /* @@ -390,17 +376,8 @@ */ params->SpiFlashCfgLockDown = 0; } - /* only replacing preexisting subsys ID defaults when non-zero */ - if (CONFIG_SUBSYSTEM_VENDOR_ID != 0) { - params->DefaultSvid = CONFIG_SUBSYSTEM_VENDOR_ID; - params->PchSubSystemVendorId = CONFIG_SUBSYSTEM_VENDOR_ID; - } - - if (CONFIG_SUBSYSTEM_DEVICE_ID != 0) { - params->DefaultSid = CONFIG_SUBSYSTEM_DEVICE_ID; - params->PchSubSystemId = CONFIG_SUBSYSTEM_DEVICE_ID; - } - + params->PchSubSystemVendorId = config->PchConfigSubSystemVendorId; + params->PchSubSystemId = config->PchConfigSubSystemId; params->PchPmWolEnableOverride = config->WakeConfigWolEnableOverride; params->PchPmPcieWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; params->PchPmDeepSxPol = config->PmConfigDeepSxPol; @@ -467,13 +444,13 @@ params->FastPkgCRampDisableSa = config->FastPkgCRampDisableSa; /* Enable PMC XRAM read */ - tconfig->PchPmPmcReadDisable = config->PchPmPmcReadDisable; +// tconfig->PchPmPmcReadDisable = config->PchPmPmcReadDisable; /* Enable/Disable EIST */ - tconfig->Eist = config->eist_enable; +// tconfig->Eist = config->eist_enable; /* Set TccActivationOffset */ - tconfig->TccActivationOffset = config->tcc_offset; +// tconfig->TccActivationOffset = config->tcc_offset; /* Enable VT-d and X2APIC */ if (!config->ignore_vtd && soc_is_vtd_capable()) { @@ -487,12 +464,13 @@ params->PchIoApicDeviceNumber = 31; params->PchIoApicFunctionNumber = 0; } +#endif soc_irq_settings(params); } /* Mainboard GPIO Configuration */ -__weak void mainboard_silicon_init_params(FSP_S_CONFIG *params) +__weak void mainboard_silicon_init_params(FSPS_CONFIG *params) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h index e75b350..820e517 100644 --- a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h +++ b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h @@ -22,10 +22,10 @@ #include <fsp/api.h> #include <fsp/util.h> -#define FSP_SIL_UPD FSP_S_CONFIG -#define FSP_MEM_UPD FSP_M_CONFIG +#define FSP_SIL_UPD FSPS_CONFIG +#define FSP_MEM_UPD FSPM_CONFIG -void mainboard_silicon_init_params(FSP_S_CONFIG *params); +void mainboard_silicon_init_params(FSPS_CONFIG *params); void soc_fsp_load(void); void soc_init_pre_device(void *chip_info); void soc_irq_settings(FSP_SIL_UPD *params); diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c index 7b3e1bd..d26bd84 100644 --- a/src/soc/intel/skylake/irq.c +++ b/src/soc/intel/skylake/irq.c @@ -22,6 +22,7 @@ #include <soc/irq.h> #include <string.h> +#if 0 static const SI_PCH_DEVICE_INTERRUPT_CONFIG devintconfig[] = { /* * cAVS(Audio, Voice, Speech), INTA is default, programmed in @@ -216,23 +217,26 @@ DEVICE_INT_CONFIG(PCH_DEV_SLOT_ISH, PCI_FUNC(PCH_DEVFN_ISH), int_A, ISH_IRQ) }; +#endif void soc_irq_settings(FSP_SIL_UPD *params) { - uint32_t i, intdeventry; + uint32_t i; +// uint32_t i, intdeventry; u8 irq_config[PCH_MAX_IRQ_CONFIG]; - const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); - const struct soc_intel_skylake_config *config = dev->chip_info; +// const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC); +// const struct soc_intel_skylake_config *config = dev->chip_info; /* Get Device Int Count */ - intdeventry = ARRAY_SIZE(devintconfig); +// intdeventry = ARRAY_SIZE(devintconfig); /* update irq table */ - memcpy((SI_PCH_DEVICE_INTERRUPT_CONFIG *) +/* memcpy((SI_PCH_DEVICE_INTERRUPT_CONFIG *) (params->DevIntConfigPtr), devintconfig, intdeventry * sizeof(SI_PCH_DEVICE_INTERRUPT_CONFIG)); params->NumOfDevIntConfig = intdeventry; +*/ /* PxRC to IRQ programming */ for (i = 0; i < PCH_MAX_IRQ_CONFIG; i++) { switch (i) { @@ -250,13 +254,15 @@ break; } } - memcpy(params->PxRcConfig, irq_config, PCH_MAX_IRQ_CONFIG); +// memcpy(params->PxRcConfig, irq_config, PCH_MAX_IRQ_CONFIG); /* GPIO IRQ Route The valid values is 14 or 15 */ - if (config->GpioIrqSelect == 0) +/* if (config->GpioIrqSelect == 0) params->GpioIrqRoute = GPIO_IRQ14; else params->GpioIrqRoute = config->GpioIrqSelect; +*/ /* SCI IRQ Select The valid values is 9, 10, 11 and 20 21, 22, 23 */ +#if 0 if (config->SciIrqSelect == 0) params->SciIrqSelect = SCI_IRQ9; else @@ -268,6 +274,7 @@ params->TcoIrqSelect = config->TcoIrqSelect; /* TCO Irq enable/disable */ params->TcoIrqEnable = config->TcoIrqEnable; +#endif } /* diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 2a60158..48f3429 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -18,6 +18,7 @@ #include <arch/io.h> #include <arch/symbols.h> #include <assert.h> +#include <compiler.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cbmem.h> @@ -37,6 +38,7 @@ #include <string.h> #include <timestamp.h> #include <security/vboot/vboot_common.h> +#include <MemInfoHob.h> #define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ @@ -101,18 +103,18 @@ if (src_dimm->Status != DIMM_PRESENT) continue; - switch (memory_info_hob->MemoryType) { + switch(memory_info_hob->MemoryType) { case MRC_DDR_TYPE_DDR4: - ddr_type = MEMORY_TYPE_DDR4; + ddr_type = MEMORY_DEVICE_DDR4; break; case MRC_DDR_TYPE_DDR3: - ddr_type = MEMORY_TYPE_DDR3; + ddr_type = MEMORY_DEVICE_DDR3; break; case MRC_DDR_TYPE_LPDDR3: - ddr_type = MEMORY_TYPE_LPDDR3; + ddr_type = MEMORY_DEVICE_LPDDR3; break; default: - ddr_type = MEMORY_TYPE_UNKNOWN; + ddr_type = MEMORY_DEVICE_UNKNOWN; break; } @@ -190,19 +192,19 @@ run_postcar_phase(&pcf); } -static void cpu_flex_override(FSP_M_CONFIG *m_cfg) +static void cpu_flex_override(FSPM_CONFIG *m_cfg) { msr_t flex_ratio; - m_cfg->CpuRatioOverride = 1; +// m_cfg->CpuRatioOverride = 1; /* * Set cpuratio to that value set in bootblock, This will ensure FSPM * knows the intended flex ratio. */ flex_ratio = rdmsr(MSR_FLEX_RATIO); - m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; +// m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff; } -static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, +static void soc_memory_init_params(FSPM_CONFIG *m_cfg, const struct soc_intel_skylake_config *config) { int i; @@ -215,31 +217,30 @@ * With the default stolen size of 32MB(-8MB) there is not enough space * for FBC to work with a high resolution panel. */ - m_cfg->IgdDvmt50PreAlloc = 2; - m_cfg->MmioSize = 0x800; /* 2GB in MB */ - m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; - m_cfg->IedSize = CONFIG_IED_REGION_SIZE; - m_cfg->ProbelessTrace = config->ProbelessTrace; - m_cfg->SaGv = config->SaGv; - m_cfg->UserBd = BOARD_TYPE_ULT_ULX; - m_cfg->RMT = config->Rmt; - m_cfg->CmdTriStateDis = config->CmdTriStateDis; - m_cfg->DdrFreqLimit = config->DdrFreqLimit; - m_cfg->VmxEnable = config->VmxEnable; - m_cfg->PrmrrSize = config->PrmrrSize; +// m_cfg->IgdDvmt50PreAlloc = 2; +// m_cfg->MmioSize = 0x800; /* 2GB in MB */ +// m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; +// m_cfg->IedSize = CONFIG_IED_REGION_SIZE; +// m_cfg->ProbelessTrace = config->ProbelessTrace; +// m_cfg->SaGv = config->SaGv; +// m_cfg->UserBd = BOARD_TYPE_ULT_ULX; +// m_cfg->RMT = config->Rmt; +// m_cfg->DdrFreqLimit = config->DdrFreqLimit; +// m_cfg->VmxEnable = config->VmxEnable; +// m_cfg->PrmrrSize = config->PrmrrSize; for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { if (config->PcieRpEnable[i]) mask |= (1<<i); } - m_cfg->PcieRpEnableMask = mask; +// m_cfg->PcieRpEnableMask = mask; cpu_flex_override(m_cfg); if (!config->ignore_vtd) { - m_cfg->PchHpetBdfValid = 1; - m_cfg->PchHpetBusNumber = 250; - m_cfg->PchHpetDeviceNumber = 15; - m_cfg->PchHpetFunctionNumber = 0; +// m_cfg->PchHpetBdfValid = 1; +// m_cfg->PchHpetBusNumber = 250; +// m_cfg->PchHpetDeviceNumber = 15; +// m_cfg->PchHpetFunctionNumber = 0; } } @@ -247,8 +248,8 @@ { const struct device *dev; const struct soc_intel_skylake_config *config; - FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig; + FSPM_CONFIG *m_cfg = &mupd->FspmConfig; +// FSPM_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig; dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); config = dev->chip_info; @@ -256,43 +257,43 @@ soc_memory_init_params(m_cfg, config); /* Skip creating Management Engine MBP HOB */ - m_t_cfg->SkipMbpHob = 0x01; +// m_t_cfg->SkipMbpHob = 0x01; /* Enable DMI Virtual Channel for ME */ - m_t_cfg->DmiVcm = 0x01; +// m_t_cfg->DmiVcm = 0x01; /* Enable Sending DID to ME */ - m_t_cfg->SendDidMsg = 0x01; - m_t_cfg->DidInitStat = 0x01; +// m_t_cfg->SendDidMsg = 0x01; +// m_t_cfg->DidInitStat = 0x01; /* DCI and TraceHub configs */ - m_t_cfg->PchDciEn = config->PchDciEn; - m_cfg->EnableTraceHub = config->EnableTraceHub; - m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size; - m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size; +// m_t_cfg->PchDciEn = config->PchDciEn; +// m_cfg->EnableTraceHub = config->EnableTraceHub; +// m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size; +// m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size; /* Enable SMBus controller based on config */ - m_cfg->SmbusEnable = config->SmbusEnable; +// m_cfg->SmbusEnable = config->SmbusEnable; mainboard_memory_init_params(mupd); } -void soc_update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, +void soc_update_memory_params_for_mma(FSPM_CONFIG *memory_cfg, struct mma_config_param *mma_cfg) { /* Boot media is memory mapped for Skylake and Kabylake (SPI). */ assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)); - memory_cfg->MmaTestContentPtr = - (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); - memory_cfg->MmaTestContentSize = - region_device_sz(&mma_cfg->test_content); - memory_cfg->MmaTestConfigPtr = - (uintptr_t) rdev_mmap_full(&mma_cfg->test_param); - memory_cfg->MmaTestConfigSize = - region_device_sz(&mma_cfg->test_param); - memory_cfg->MrcFastBoot = 0x00; - memory_cfg->SaGv = 0x02; +// memory_cfg->MmaTestContentPtr = +// (uintptr_t) rdev_mmap_full(&mma_cfg->test_content); +// memory_cfg->MmaTestContentSize = +// region_device_sz(&mma_cfg->test_content); +// memory_cfg->MmaTestConfigPtr = +// (uintptr_t) rdev_mmap_full(&mma_cfg->test_param); +// memory_cfg->MmaTestConfigSize = +// region_device_sz(&mma_cfg->test_param); +// memory_cfg->MrcFastBoot = 0x00; +// memory_cfg->SaGv = 0x02; } __weak void mainboard_memory_init_params(FSPM_UPD *mupd) diff --git a/src/soc/intel/skylake/vr_config.c b/src/soc/intel/skylake/vr_config.c index 4508fda..9266330 100644 --- a/src/soc/intel/skylake/vr_config.c +++ b/src/soc/intel/skylake/vr_config.c @@ -56,7 +56,7 @@ * | IccMax(AML-Y) | 4.1A | 28A | 24A | 24A | * +----------------+-------------+---------------+------+-----+ */ - +#if 0 static const struct { uint16_t icc_max[NUM_VR_DOMAINS]; }sku_icc_max_mapping[] = { @@ -167,12 +167,13 @@ .voltage_limit = 1520, }, }; +#endif static uint16_t get_dev_id(struct device *dev) { return pci_read_config16(dev, PCI_DEVICE_ID); } - +#if 0 static int get_kbl_sku(void) { static int sku = -1; @@ -201,7 +202,6 @@ sku = -2; return sku; } - static uint16_t get_sku_icc_max(int domain, uint16_t board_icc_max) { /* If board provided non-zero value, use it. */ @@ -229,7 +229,7 @@ cfg = chip_cfg; else cfg = &default_configs[domain]; - +/* vr_params->VrConfigEnable[domain] = cfg->vr_config_enable; vr_params->Psi1Threshold[domain] = cfg->psi1threshold; vr_params->Psi2Threshold[domain] = cfg->psi2threshold; @@ -240,9 +240,10 @@ vr_params->ImonOffset[domain] = cfg->imon_offset; vr_params->IccMax[domain] = get_sku_icc_max(domain, cfg->icc_max); vr_params->VrVoltageLimit[domain] = cfg->voltage_limit; - +*/ #if IS_ENABLED(CONFIG_PLATFORM_USES_FSP2_0) - vr_params->AcLoadline[domain] = cfg->ac_loadline; - vr_params->DcLoadline[domain] = cfg->dc_loadline; +// vr_params->AcLoadline[domain] = cfg->ac_loadline; +// vr_params->DcLoadline[domain] = cfg->dc_loadline; #endif } +#endif diff --git a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DebugSupport.h b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DebugSupport.h index 6983469..af0950f 100644 --- a/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DebugSupport.h +++ b/src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/DebugSupport.h @@ -605,7 +605,7 @@ UINT64 ELR; // Exception Link Register UINT64 SPSR; // Saved Processor Status Register UINT64 FPSR; // Floating Point Status Register - UINT64 ESR; // Exception syndrome register +// UINT64 ESR; // Exception syndrome register UINT64 FAR; // Fault Address Register } EFI_SYSTEM_CONTEXT_AARCH64; diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FirmwareVersionInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FirmwareVersionInfoHob.h new file mode 100644 index 0000000..fca01e9 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FirmwareVersionInfoHob.h @@ -0,0 +1,67 @@ +/** @file + Header file for Firmware Version Information + + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved. + + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License which accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _FIRMWARE_VERSION_INFO_HOB_H_ +#define _FIRMWARE_VERSION_INFO_HOB_H_ + +#include <Uefi/UefiMultiPhase.h> +#include <Pi/PiBootMode.h> +#include <Pi/PiHob.h> + +#pragma pack(1) +/// +/// Firmware Version Structure +/// +typedef struct { + UINT8 MajorVersion; + UINT8 MinorVersion; + UINT8 Revision; + UINT16 BuildNumber; +} FIRMWARE_VERSION; + +/// +/// Firmware Version Information Structure +/// +typedef struct { + UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name + UINT8 VersionStringIndex; ///< Offset 1 Index of Version String + FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version +} FIRMWARE_VERSION_INFO; + +#ifndef __SMBIOS_STANDARD_H__ +/// +/// The Smbios structure header. +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Handle; +} SMBIOS_STRUCTURE; +#endif + +/// +/// Firmware Version Information HOB Structure +/// +typedef struct { + EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB + SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB + UINT8 Count; ///< Offset 28 Number of FVI elements included. +/// +/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer +/// +} FIRMWARE_VERSION_INFO_HOB; +#pragma pack() + +#endif // _FIRMWARE_VERSION_INFO_HOB_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h new file mode 100644 index 0000000..cf543fe --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspUpd.h @@ -0,0 +1,48 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPD_H__ +#define __FSPUPD_H__ + +#include <FspEas.h> + +#pragma pack(1) + +#define FSPT_UPD_SIGNATURE 0x545F445055434F53 /* 'SOCUPD_T' */ + +#define FSPM_UPD_SIGNATURE 0x4D5F445055434F53 /* 'SOCUPD_M' */ + +#define FSPS_UPD_SIGNATURE 0x535F445055434F53 /* 'SOCUPD_S' */ + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h new file mode 100644 index 0000000..a66b3306 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspmUpd.h @@ -0,0 +1,248 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include <FspUpd.h> + +#pragma pack(1) + + +/** FSP-M Configuration +**/ +typedef struct { + +/** Offset 0x0040 - Tseg Size + Size of SMRAM memory reserved. + 2:2 MB, 4:4 MB, 8:8 MB, 16:16 MB +**/ + UINT8 PcdSmmTsegSize; + +/** Offset 0x0041 - FSP Debug Print Level + Select the FSP debug message print level. + 0:NO DEBUG, 1:MIN DEBUG, 2:MED DEBUG, 3:VERBOSE DEBUG +**/ + UINT8 PcdFspDebugPrintErrorLevel; + +/** Offset 0x0042 - Channel 0 DIMM 0 SPD SMBus Address + SPD SMBus Address of each DIMM slot. +**/ + UINT8 PcdSpdSmbusAddress_0_0; + +/** Offset 0x0043 - Channel 0 DIMM 1 SPD SMBus Address + SPD SMBus Address of each DIMM slot. +**/ + UINT8 PcdSpdSmbusAddress_0_1; + +/** Offset 0x0044 - Channel 1 DIMM 0 SPD SMBus Address + SPD SMBus Address of each DIMM slot. +**/ + UINT8 PcdSpdSmbusAddress_1_0; + +/** Offset 0x0045 - Channel 1 DIMM 1 SPD SMBus Address + SPD SMBus Address of each DIMM slot. +**/ + UINT8 PcdSpdSmbusAddress_1_1; + +/** Offset 0x0046 - Enable Rank Margin Tool + Enable/disable Rank Margin Tool. + $EN_DIS +**/ + UINT8 PcdMrcRmtSupport; + +/** Offset 0x0047 - RMT CPGC exp_loop_cnt + Set the CPGC exp_loop_cnt field for RMT execution 2^(exp_loop_cnt -1). + 1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 +**/ + UINT8 PcdMrcRmtCpgcExpLoopCntValue; + +/** Offset 0x0048 - RMT CPGC num_bursts + Set the CPGC num_bursts field for RMT execution 2^(num_bursts -1). + 1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, 14:14, 15:15 +**/ + UINT8 PcdMrcRmtCpgcNumBursts; + +/** Offset 0x0049 - Preserve Memory Across Reset + Enable/disable memory preservation across reset. + $EN_DIS +**/ + UINT8 PcdMemoryPreservation; + +/** Offset 0x004A - Fast Boot + Enable/disable Fast Boot function. Once enabled, all following boots will use the + presaved MRC data to improve the boot performance. + $EN_DIS +**/ + UINT8 PcdFastBoot; + +/** Offset 0x004B - ECC Support + Enable/disable ECC Support. + $EN_DIS +**/ + UINT8 PcdEccSupport; + +/** Offset 0x004C - HSUART Device + Select the PCI High Speed UART Device for Serial Port. + 0:HSUART0, 1:HSUART1, 2:HSUART2 +**/ + UINT8 PcdHsuartDevice; + +/** Offset 0x004D - Memory Down + Enable/disable Memory Down function. + $EN_DIS +**/ + UINT8 PcdMemoryDown; + +/** Offset 0x004E +**/ + UINT32 PcdMemoryDownConfigPtr; + +/** Offset 0x0052 - SATA Controller 0 + Enable/disable SATA Controller 0. + $EN_DIS +**/ + UINT8 PcdEnableSATA0; + +/** Offset 0x0053 - SATA Controller 1 + Enable/disable SATA Controller 1. + $EN_DIS +**/ + UINT8 PcdEnableSATA1; + +/** Offset 0x0054 - Intel Quick Assist Technology + Enable/disable Intel Quick Assist Technology. + $EN_DIS +**/ + UINT8 PcdEnableIQAT; + +/** Offset 0x0055 - SPD Write Disable + Select SMBus SPD Write Enable State (Default: 0 = [FORCE_ENABLE], 1 = [FORCE_DISABLE]) + 0:Force Enable, 1:Force Disable +**/ + UINT8 PcdSmbusSpdWriteDisable; + +/** Offset 0x0056 - ME_SHUTDOWN Message + Enable/Disable sending ME_SHUTDOWN message to ME, refer to FSP Integration Guide + for details. + $EN_DIS +**/ + UINT8 PcdEnableMeShutdown; + +/** Offset 0x0057 - XHCI Controller + Enable / Disable XHCI controller + $EN_DIS +**/ + UINT8 PcdEnableXhci; + +/** Offset 0x0058 - Memory Frequency + Set DDR Memory Frequency, refer to FSP Integration Guide for details.. + 15:Auto, 3:1600, 4:1866, 5:2133, 6:2400 +**/ + UINT8 PcdDdrFreq; + +/** Offset 0x0059 - MMIO Size + Set memory mapped IO space size + 0:2048M, 1:1024M, 2:3072M +**/ + UINT8 PcdMmioSize; + +/** Offset 0x005A +**/ + UINT8 UnusedUpdSpace0[6]; + +/** Offset 0x0060 - Customer Revision + The Customer can set this revision string for their own purpose. +**/ + UINT8 PcdCustomerRevision[32]; + +/** Offset 0x0080 - 32-Bit bus mode + Enable/Disable 32-Bit bus memory mode. + $EN_DIS +**/ + UINT8 PcdHalfWidthEnable; + +/** Offset 0x0081 - TCL Performance + Enable/Disable Tcl timing for performance. + $EN_DIS +**/ + UINT8 PcdTclIdle; + +/** Offset 0x0082 - Interleave Mode + Select Interleave Mode + 0:DISABLED, 1:MODE0, 2:MODE1, 3:MODE2 +**/ + UINT8 PcdInterleaveMode; + +/** Offset 0x0083 - Memory Thermal Throttling + Enable/disable Memory Thermal Throttling management mode + $EN_DIS +**/ + UINT8 PcdMemoryThermalThrottling; + +/** Offset 0x0084 +**/ + UINT8 UnusedUpdSpace1[348]; + +/** Offset 0x01E0 +**/ + UINT8 ReservedMemoryInitUpd[16]; +} FSPM_CONFIG; + +/** Fsp M UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPM_ARCH_UPD FspmArchUpd; + +/** Offset 0x0040 +**/ + FSPM_CONFIG FspmConfig; + +/** Offset 0x01F0 +**/ + UINT8 UnusedUpdSpace2[14]; + +/** Offset 0x01FE +**/ + UINT16 UpdTerminator; +} FSPM_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h new file mode 100644 index 0000000..5d0b793 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FspsUpd.h @@ -0,0 +1,192 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include <FspUpd.h> + +#pragma pack(1) + + +/** FSP-S Configuration +**/ +typedef struct { + +/** Offset 0x0020 - PCIe Controller 0 Bifurcation + Configure PCI Express controller 0 bifurcation. + 0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8 +**/ + UINT8 PcdBifurcationPcie0; + +/** Offset 0x0021 - PCIe Controller 1 Bifurcation + Configure PCI Express controller 1 bifurcation. + 0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8 +**/ + UINT8 PcdBifurcationPcie1; + +/** Offset 0x0022 - Active Core Count + Select # of Active Cores (Default: 0, 0:ALL, 1..15 = 1..15 Cores) + 0:ALL, 1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, + 14:14, 15:15 +**/ + UINT8 PcdActiveCoreCount; + +/** Offset 0x0023 +**/ + UINT32 PcdCpuMicrocodePatchBase; + +/** Offset 0x0027 +**/ + UINT32 PcdCpuMicrocodePatchSize; + +/** Offset 0x002B - PCIe Controller 0 + Enable / Disable PCI Express controller 0 + $EN_DIS +**/ + UINT8 PcdEnablePcie0; + +/** Offset 0x002C - PCIe Controller 1 + Enable / Disable PCI Express controller 1 + $EN_DIS +**/ + UINT8 PcdEnablePcie1; + +/** Offset 0x002D - Embedded Multi-Media Controller (eMMC) + Enable / Disable Embedded Multi-Media controller + $EN_DIS +**/ + UINT8 PcdEnableEmmc; + +/** Offset 0x002E - LAN Controllers + Enable / Disable LAN controllers, refer to FSP Integration Guide for details. + 0:Disable LAN 0 & LAN 1, 1:Enable LAN 0 & LAN 1, 2:Disable LAN 1 only +**/ + UINT8 PcdEnableGbE; + +/** Offset 0x002F +**/ + UINT32 PcdFiaMuxConfigRequestPtr; + +/** Offset 0x0033 +**/ + UINT8 UnusedUpdSpace0[4]; + +/** Offset 0x0037 - PCIe Root Port 0 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort0DeEmphasis; + +/** Offset 0x0038 - PCIe Root Port 1 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort1DeEmphasis; + +/** Offset 0x0039 - PCIe Root Port 2 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort2DeEmphasis; + +/** Offset 0x003A - PCIe Root Port 3 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort3DeEmphasis; + +/** Offset 0x003B - PCIe Root Port 4 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort4DeEmphasis; + +/** Offset 0x003C - PCIe Root Port 5 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort5DeEmphasis; + +/** Offset 0x003D - PCIe Root Port 6 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort6DeEmphasis; + +/** Offset 0x003E - PCIe Root Port 7 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcdPcieRootPort7DeEmphasis; + +/** Offset 0x003F +**/ + UINT8 UnusedUpdSpace1; + +/** Offset 0x0040 +**/ + UINT32 PcdEMMCDLLConfigPtr; + +/** Offset 0x0044 +**/ + UINT8 UnusedUpdSpace2[156]; + +/** Offset 0x00E0 +**/ + UINT8 ReservedSiliconInitUpd[16]; +} FSPS_CONFIG; + +/** Fsp S UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPS_CONFIG FspsConfig; + +/** Offset 0x00F0 +**/ + UINT8 UnusedUpdSpace3[14]; + +/** Offset 0x00FE +**/ + UINT16 UpdTerminator; +} FSPS_UPD; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FsptUpd.h new file mode 100644 index 0000000..340f144 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/skykabylake/FsptUpd.h @@ -0,0 +1,109 @@ +/** @file + +Copyright (c) 2018, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPTUPD_H__ +#define __FSPTUPD_H__ + +#include <FspUpd.h> + +#pragma pack(1) + + +/** FSP-T Core UPD +**/ +typedef struct { + +/** Offset 0x0020 +**/ + UINT32 MicrocodeRegionBase; + +/** Offset 0x0024 +**/ + UINT32 MicrocodeRegionLength; + +/** Offset 0x0028 +**/ + UINT32 CodeRegionBase; + +/** Offset 0x002C +**/ + UINT32 CodeRegionLength; + +/** Offset 0x0030 +**/ + UINT8 Reserved1[16]; +} FSPT_CORE_UPD; + +/** FSP-T Configuration +**/ +typedef struct { + +/** Offset 0x0040 - Disable Port80 output in FSP-T + Select Port80 Control in FSP-T (0:VPD-Style, 1:Enable Port80 Output, 2:Disable Port80 + Output, refer to FSP Integration Guide for details + 0:VPD-Style, 1:Enable Port80 Output[Default], 2:Disable Port80 Output +**/ + UINT8 PcdFsptPort80RouteDisable; + +/** Offset 0x0041 +**/ + UINT8 ReservedTempRamInitUpd[31]; +} FSPT_CONFIG; + +/** Fsp T UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPT_CORE_UPD FsptCoreUpd; + +/** Offset 0x0040 +**/ + FSPT_CONFIG FsptConfig; + +/** Offset 0x0060 +**/ + UINT8 UnusedUpdSpace0[30]; + +/** Offset 0x007E +**/ + UINT16 UpdTerminator; +} FSPT_UPD; + +#pragma pack() + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/31205 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I033a52bc3f0b86f0ec1db8325b7435d20d194fda Gerrit-Change-Number: 31205 Gerrit-PatchSet: 1 Gerrit-Owner: Name of user not set #1002246 Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: drivers/smmstore: Fix some issues
by Arthur Heymans (Code Review) 29 Nov '19

29 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30432 Change subject: drivers/smmstore: Fix some issues ...................................................................... drivers/smmstore: Fix some issues This fixes the following: - Make the API ARCH independent (no dependency on size_t) - clean up the code a little Change-Id: I629be25d2a9b65796ae8f7a700b6bdab57b91b22 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/smmstore/store.c M src/include/smmstore.h M src/soc/intel/common/block/smm/smihandler.c 3 files changed, 86 insertions(+), 67 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/30432/1 diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c index 409949a..0a62b3c 100644 --- a/src/drivers/smmstore/store.c +++ b/src/drivers/smmstore/store.c @@ -62,8 +62,8 @@ if (cbfs_locate_file_in_region(&file, CONFIG_SMMSTORE_REGION, CONFIG_SMMSTORE_FILENAME, NULL) < 0) { - printk(BIOS_WARNING, "smm store: " - "Unable to find SMM store file in region '%s'\n", + printk(BIOS_WARNING, + "smm store: Unable to find SMM store file in region '%s'\n", CONFIG_SMMSTORE_REGION); return -1; } @@ -87,14 +87,13 @@ * returns 0 on success, -1 on failure * writes up to `*bufsize` bytes into `buf` and updates `*bufsize` */ -int smmstore_read_region(void *buf, ssize_t *bufsize) +int smmstore_read_region(void *buf, uint32_t *bufsize) { struct region_device store; if (bufsize == NULL) return -1; - *bufsize = 0; if (lookup_store(&store) < 0) { printk(BIOS_WARNING, "reading region failed\n"); return -1; @@ -109,6 +108,66 @@ return 0; } +static enum cb_err scan_end(ssize_t *end) +{ + struct region_device store; + + if (lookup_store(&store) < 0) { + printk(BIOS_WARNING, "reading region failed\n"); + return CB_ERR; + } + ssize_t data_sz = region_device_sz(&store); + + /* scan for end */ + *end = 0; + uint32_t k_sz, v_sz; + while (*end < data_sz) { + /* make odd corner cases identifiable, eg. invalid v_sz */ + k_sz = 0; + + if (rdev_readat(&store, &k_sz, *end, sizeof(k_sz)) < 0) { + printk(BIOS_WARNING, "failed reading key size\n"); + return CB_ERR; + } + + /* found the end */ + if (k_sz == 0xffffffff) + break; + + /* something is fishy here: + * Avoid wrapping (since data_size < MAX_UINT32_T / 2) while + * other problems are covered by the loop condition + */ + if (k_sz > data_sz) { + printk(BIOS_WARNING, "key size out of bounds\n"); + return CB_ERR; + } + + if (rdev_readat(&store, &v_sz, *end + 4, sizeof(v_sz)) < 0) { + printk(BIOS_WARNING, "failed reading value size\n"); + return CB_ERR; + } + + if (v_sz > data_sz) { + printk(BIOS_WARNING, "value size out of bounds\n"); + return CB_ERR; + } + + *end += sizeof(k_sz) + sizeof(v_sz) + k_sz + v_sz + 1; + *end = ALIGN_UP(*end, sizeof(uint32_t)); + } + + printk(BIOS_WARNING, "used smm store size might be 0x%zx bytes\n", *end); + + if (k_sz != 0xffffffff) { + printk(BIOS_WARNING, + "eof of data marker looks invalid: 0x%x\n", k_sz); + return CB_ERR; + } + + return CB_SUCCESS; + +} /* * Append data to region * @@ -124,78 +183,38 @@ return -1; } - ssize_t data_sz = region_device_sz(&store); - - /* scan for end */ - ssize_t end = 0; - uint32_t k_sz, v_sz; - while (end < data_sz) { - /* make odd corner cases identifiable, eg. invalid v_sz */ - k_sz = 0; - - if (rdev_readat(&store, &k_sz, end, sizeof(k_sz)) < 0) { - printk(BIOS_WARNING, "failed reading key size\n"); - return -1; - } - - /* found the end */ - if (k_sz == 0xffffffff) - break; - - /* something is fishy here: - * Avoid wrapping (since data_size < MAX_UINT32_T / 2) while - * other problems are covered by the loop condition - */ - if (k_sz > data_sz) { - printk(BIOS_WARNING, "key size out of bounds\n"); - return -1; - } - - if (rdev_readat(&store, &v_sz, end + 4, sizeof(v_sz)) < 0) { - printk(BIOS_WARNING, "failed reading value size\n"); - return -1; - } - - if (v_sz > data_sz) { - printk(BIOS_WARNING, "value size out of bounds\n"); - return -1; - } - - end += 8 + k_sz + v_sz + 1; - end = ALIGN_UP(end, sizeof(uint32_t)); - } - - printk(BIOS_WARNING, "used smm store size might be 0x%zx bytes\n", end); - - if (k_sz != 0xffffffff) { - printk(BIOS_WARNING, - "eof of data marker looks invalid: 0x%x\n", k_sz); + ssize_t end; + if (scan_end(&end) == CB_ERR) return -1; - } printk(BIOS_WARNING, "used size looks legit\n"); printk(BIOS_WARNING, "open (%zx, %zx) for writing\n", region_device_offset(&store), region_device_sz(&store)); - if (boot_device_rw_subregion(&store.region, &store) < 0) { + if (boot_device_rw_subregion(region_device_region(&store), &store) < 0) { printk(BIOS_WARNING, "couldn't open store for writing\n"); return -1; } - uint32_t record_sz = 8 + key_sz + value_sz + 1; - if (end + record_sz >= data_sz) { + struct region subregion = + { + .offset = end, + .size = sizeof(key_sz) + sizeof(value_sz) + key_sz + value_sz + 1, + }; + + if (region_is_subregion(region_device_region(&store), &subregion)) { printk(BIOS_WARNING, "not enough space for new data\n"); return -1; } - if (rdev_writeat(&store, &key_sz, end, 4) != 4) { + if (rdev_writeat(&store, &key_sz, end, sizeof(key_sz) != sizeof(key_sz))) { printk(BIOS_WARNING, "failed writing key size\n"); } - end += 4; - if (rdev_writeat(&store, &value_sz, end, 4) != 4) { + end += sizeof(key_sz); + if (rdev_writeat(&store, &value_sz, end, sizeof(value_sz) != sizeof(key_sz))) { printk(BIOS_WARNING, "failed writing value size\n"); } - end += 4; + end += sizeof(value_sz); if (rdev_writeat(&store, key, end, key_sz) != key_sz) { printk(BIOS_WARNING, "failed writing key data\n"); } @@ -205,7 +224,7 @@ } end += value_sz; uint8_t nul = 0; - if (rdev_writeat(&store, &nul, end, 1) != 1) { + if (rdev_writeat(&store, &nul, end, sizeof(nul)) != sizeof(nul)) { printk(BIOS_WARNING, "failed writing termination\n"); } diff --git a/src/include/smmstore.h b/src/include/smmstore.h index a535c5b..30a8191 100644 --- a/src/include/smmstore.h +++ b/src/include/smmstore.h @@ -28,22 +28,22 @@ #define SMMSTORE_CMD_APPEND 3 struct smmstore_params_read { - void *buf; - ssize_t bufsize; + uint32_t *buf; + uint32_t bufsize; }; struct smmstore_params_append { - void *key; - size_t keysize; - void *val; - size_t valsize; + uint32_t *key; + uint32_t keysize; + uint32_t *val; + uint32_t valsize; }; /* SMM responder */ uint32_t smmstore_exec(uint8_t command, void *param); /* implementation */ -int smmstore_read_region(void *buf, ssize_t *bufsize); +int smmstore_read_region(void *buf, uint32_t *bufsize); int smmstore_append_data(void *key, uint32_t key_sz, void *value, uint32_t value_sz); int smmstore_clear_region(void); diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 2ffc00f..c125c0c 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -311,7 +311,7 @@ reg_ebx = save_state_ops->get_reg(io_smi, RBX); /* drivers/smmstore/smi.c */ - ret = smmstore_exec(sub_command, (void *)reg_ebx); + ret = smmstore_exec(sub_command, (uintptr_t *)reg_ebx); save_state_ops->set_reg(io_smi, RAX, ret); } -- To view, visit https://review.coreboot.org/c/coreboot/+/30432 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I629be25d2a9b65796ae8f7a700b6bdab57b91b22 Gerrit-Change-Number: 30432 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

6 35

Change in ...coreboot[master]: {include,lib}: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 28 Nov '19

28 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32824 Change subject: {include,lib}: Use 'include <stdlib.h>' when appropriate ...................................................................... {include,lib}: Use 'include <stdlib.h>' when appropriate Change-Id: I49762ffee79274c39c0fdd62d127e1d0d57cd686 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/bootstate.h M src/include/string.h M src/lib/coreboot_table.c M src/lib/hardwaremain.c M src/lib/thread.c 5 files changed, 1 insertion(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/32824/1 diff --git a/src/include/bootstate.h b/src/include/bootstate.h index 26038c6..c53884e 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -16,7 +16,6 @@ #define BOOTSTATE_H #include <string.h> -#include <stdlib.h> #include <stddef.h> #include <stdint.h> /* Only declare main() when in ramstage. */ diff --git a/src/include/string.h b/src/include/string.h index 4a2f5e9..81afcf0 100644 --- a/src/include/string.h +++ b/src/include/string.h @@ -2,7 +2,6 @@ #define STRING_H #include <stddef.h> -#include <stdlib.h> #if !defined(__ROMCC__) #include <console/vtxprintf.h> diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 6e44f5d..24e10f4 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -27,10 +27,10 @@ #include <boardid.h> #include <device/device.h> #include <fmap.h> -#include <stdlib.h> #include <cbfs.h> #include <cbmem.h> #include <bootmem.h> +#include <stddef.h> #include <spi_flash.h> #include <security/vboot/misc.h> #include <security/vboot/vbnv_layout.h> diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 2881162..608b683 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -28,7 +28,6 @@ #include <device/device.h> #include <device/pci.h> #include <delay.h> -#include <stdlib.h> #include <boot/tables.h> #include <program_loading.h> #if CONFIG(HAVE_ACPI_RESUME) diff --git a/src/lib/thread.c b/src/lib/thread.c index 281885f..a786b9f 100644 --- a/src/lib/thread.c +++ b/src/lib/thread.c @@ -15,7 +15,6 @@ #include <stddef.h> #include <stdint.h> -#include <stdlib.h> #include <arch/cpu.h> #include <bootstate.h> #include <console/console.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/32824 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49762ffee79274c39c0fdd62d127e1d0d57cd686 Gerrit-Change-Number: 32824 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/security: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 28 Nov '19

28 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32827 Change subject: src/security: Use 'include <stdlib.h>' when appropriate ...................................................................... src/security: Use 'include <stdlib.h>' when appropriate Change-Id: I7c3ae72b4388ee12ab957ca516ed0fe19188895a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/security/tpm/tspi/tspi.c M src/security/vboot/secdata_mock.c M src/security/vboot/secdata_tpm.c M src/security/vboot/vboot_handoff.c 4 files changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/32827/1 diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 4698a4d..7bb4362 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -19,12 +19,12 @@ #include <console/console.h> #include <security/tpm/tspi.h> #include <security/tpm/tss.h> -#include <stdlib.h> #if CONFIG(VBOOT) #include <vb2_api.h> #include <vb2_sha.h> #include <assert.h> #endif +#include <stddef.h> #if CONFIG(TPM1) static uint32_t tpm1_invoke_state_machine(void) diff --git a/src/security/vboot/secdata_mock.c b/src/security/vboot/secdata_mock.c index 3075d33..53265c1 100644 --- a/src/security/vboot/secdata_mock.c +++ b/src/security/vboot/secdata_mock.c @@ -32,7 +32,6 @@ * stored in the TPM NVRAM. */ -#include <stdlib.h> #include <security/tpm/tspi.h> #include <vb2_api.h> diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 39cd614..5aff0d6 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -33,7 +33,7 @@ */ #include <security/vboot/antirollback.h> -#include <stdlib.h> +#include <stddef.h> #include <string.h> #include <security/tpm/tspi.h> #include <vb2_api.h> diff --git a/src/security/vboot/vboot_handoff.c b/src/security/vboot/vboot_handoff.c index 8a6b3d6..7f0d528 100644 --- a/src/security/vboot/vboot_handoff.c +++ b/src/security/vboot/vboot_handoff.c @@ -27,7 +27,6 @@ #include <console/console.h> #include <console/vtxprintf.h> #include <fmap.h> -#include <stdlib.h> #include <vboot_struct.h> #include <security/vboot/vbnv.h> #include <security/vboot/misc.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/32827 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c3ae72b4388ee12ab957ca516ed0fe19188895a Gerrit-Change-Number: 32827 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: northbridge: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 28 Nov '19

28 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32826 Change subject: northbridge: Use 'include <stdlib.h>' when appropriate ...................................................................... northbridge: Use 'include <stdlib.h>' when appropriate Change-Id: I9ccbca68ac7a2c049d917968310a6346353f4548 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/agesa/family12/dimmSpd.c M src/northbridge/amd/agesa/family12/northbridge.c M src/northbridge/amd/agesa/family14/dimmSpd.c M src/northbridge/amd/agesa/family14/northbridge.c M src/northbridge/amd/agesa/family15tn/dimmSpd.c M src/northbridge/amd/agesa/family16kb/dimmSpd.c M src/northbridge/amd/amdht/comlib.h M src/northbridge/amd/amdmct/wrappers/mcti.h M src/northbridge/amd/pi/00660F01/dimmSpd.c M src/northbridge/intel/e7505/debug.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/e7505/raminit.c M src/northbridge/intel/fsp_rangeley/northbridge.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/haswell/gma.c M src/northbridge/intel/haswell/minihd.c M src/northbridge/intel/nehalem/early_init.c M src/northbridge/intel/nehalem/northbridge.c M src/northbridge/intel/pineview/early_init.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/sandybridge/finalize.c M src/northbridge/intel/x4x/northbridge.c M src/northbridge/via/vx900/chrome9hd.c 24 files changed, 7 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/32826/1 diff --git a/src/northbridge/amd/agesa/family12/dimmSpd.c b/src/northbridge/amd/agesa/family12/dimmSpd.c index 822c577..8e72773 100644 --- a/src/northbridge/amd/agesa/family12/dimmSpd.c +++ b/src/northbridge/amd/agesa/family12/dimmSpd.c @@ -27,10 +27,8 @@ * */ -#include <stdlib.h> #include <Porting.h> #include <AGESA.h> - #include <northbridge/amd/agesa/dimmSpd.h> typedef struct _DIMM_INFO_SMBUS { diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 290ab16..4f5fd9c 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -22,11 +22,9 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/hypertransport.h> -#include <stdlib.h> #include <string.h> #include <lib.h> #include <cpu/cpu.h> - #include <cpu/x86/lapic.h> #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> diff --git a/src/northbridge/amd/agesa/family14/dimmSpd.c b/src/northbridge/amd/agesa/family14/dimmSpd.c index 9877650..f95ff5e 100644 --- a/src/northbridge/amd/agesa/family14/dimmSpd.c +++ b/src/northbridge/amd/agesa/family14/dimmSpd.c @@ -15,9 +15,7 @@ #include <device/pci_def.h> #include <device/device.h> -#include <stdlib.h> #include <OEM.h> /* SMBUS0_BASE_ADDRESS */ - /* warning: Porting.h includes an open #pragma pack(1) */ #include <Porting.h> #include <AGESA.h> diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index a52f7ec..e4f26f6 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -22,7 +22,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/hypertransport.h> -#include <stdlib.h> #include <string.h> #include <lib.h> #include <cpu/cpu.h> diff --git a/src/northbridge/amd/agesa/family15tn/dimmSpd.c b/src/northbridge/amd/agesa/family15tn/dimmSpd.c index 7ca4709..30fd74b 100644 --- a/src/northbridge/amd/agesa/family15tn/dimmSpd.c +++ b/src/northbridge/amd/agesa/family15tn/dimmSpd.c @@ -15,7 +15,6 @@ #include <device/pci_def.h> #include <device/device.h> -#include <stdlib.h> /* warning: Porting.h includes an open #pragma pack(1) */ #include <Porting.h> diff --git a/src/northbridge/amd/agesa/family16kb/dimmSpd.c b/src/northbridge/amd/agesa/family16kb/dimmSpd.c index 8c453bb..78dc128 100644 --- a/src/northbridge/amd/agesa/family16kb/dimmSpd.c +++ b/src/northbridge/amd/agesa/family16kb/dimmSpd.c @@ -15,7 +15,6 @@ #include <device/pci_def.h> #include <device/device.h> -#include <stdlib.h> /* warning: Porting.h includes an open #pragma pack(1) */ #include <Porting.h> diff --git a/src/northbridge/amd/amdht/comlib.h b/src/northbridge/amd/amdht/comlib.h index d497fd2..d7b53c3 100644 --- a/src/northbridge/amd/amdht/comlib.h +++ b/src/northbridge/amd/amdht/comlib.h @@ -20,7 +20,6 @@ #define FILECODE 0xF001 #include <inttypes.h> -#include <stdlib.h> #include "porting.h" #ifdef AMD_DEBUG diff --git a/src/northbridge/amd/amdmct/wrappers/mcti.h b/src/northbridge/amd/amdmct/wrappers/mcti.h index 92dc0b8..baab526 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti.h +++ b/src/northbridge/amd/amdmct/wrappers/mcti.h @@ -19,7 +19,6 @@ #define MCTI_H #include <inttypes.h> -#include <stdlib.h> #include <pc80/mc146818rtc.h> struct DCTStatStruc; diff --git a/src/northbridge/amd/pi/00660F01/dimmSpd.c b/src/northbridge/amd/pi/00660F01/dimmSpd.c index 349dacf..d25a35f 100644 --- a/src/northbridge/amd/pi/00660F01/dimmSpd.c +++ b/src/northbridge/amd/pi/00660F01/dimmSpd.c @@ -15,7 +15,6 @@ #include <device/pci_def.h> #include <device/device.h> -#include <stdlib.h> /* warning: Porting.h includes an open #pragma pack(1) */ #include <Porting.h> diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c index 357a963..baa0bf1 100644 --- a/src/northbridge/intel/e7505/debug.c +++ b/src/northbridge/intel/e7505/debug.c @@ -13,7 +13,6 @@ #include <device/pci_def.h> #include <console/console.h> -#include <stdlib.h> #include <arch/io.h> #include <device/pci_ops.h> #include <spd.h> diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c index 7cb0b5b..074f63a 100644 --- a/src/northbridge/intel/e7505/northbridge.c +++ b/src/northbridge/intel/e7505/northbridge.c @@ -18,7 +18,6 @@ #include <device/device.h> #include <device/pci.h> #include <cpu/cpu.h> -#include <stdlib.h> #include "e7505.h" diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 3bb1f67..18d3abe 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -30,7 +30,6 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <lib.h> -#include <stdlib.h> #include <commonlib/helpers.h> #include <console/console.h> #include <cpu/x86/mtrr.h> diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index 63f2068..b89a8cf 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -23,7 +23,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <stdlib.h> #include <cpu/cpu.h> #include <drivers/intel/fsp1_0/fsp_util.h> #include <cpu/x86/lapic.h> diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index f011cce..261fef5 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -19,7 +19,6 @@ #include <stdint.h> #include <device/device.h> #include <device/pci.h> -#include <stdlib.h> #include <cpu/cpu.h> #include <boot/tables.h> #include <arch/acpi.h> diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index 607fab7..c4f6f76 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -29,7 +29,6 @@ #include <cpu/intel/haswell/haswell.h> #include <drivers/intel/gma/opregion.h> #include <southbridge/intel/lynxpoint/nvs.h> -#include <stdlib.h> #include <string.h> #include <types.h> diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index 61265dd..ff5b943 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -21,7 +21,6 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/mmio.h> -#include <stdlib.h> #include <southbridge/intel/lynxpoint/hda_verb.h> static const u32 minihd_verb_table[] = { diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c index a5cac7b..f12416e 100644 --- a/src/northbridge/intel/nehalem/early_init.c +++ b/src/northbridge/intel/nehalem/early_init.c @@ -16,7 +16,6 @@ */ #include <stdint.h> -#include <stdlib.h> #include <console/console.h> #include <arch/io.h> #include <device/pci_ops.h> diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index a9032ba..aee98cd 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -25,11 +25,11 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <stdlib.h> #include <cpu/cpu.h> +#include <cpu/intel/smm/gen1/smi.h> + #include "chip.h" #include "nehalem.h" -#include <cpu/intel/smm/gen1/smi.h> static int bridge_revision_id = -1; diff --git a/src/northbridge/intel/pineview/early_init.c b/src/northbridge/intel/pineview/early_init.c index ac187c1..d649c75 100644 --- a/src/northbridge/intel/pineview/early_init.c +++ b/src/northbridge/intel/pineview/early_init.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <console/console.h> #include <arch/io.h> #include <device/pci_ops.h> diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c index 4b67cfd..01d930b 100644 --- a/src/northbridge/intel/pineview/northbridge.c +++ b/src/northbridge/intel/pineview/northbridge.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <device/device.h> #include <device/pci.h> -#include <stdlib.h> #include <cpu/cpu.h> #include <boot/tables.h> #include <arch/acpi.h> diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index 282765e..c272767 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -21,10 +21,12 @@ #include <cpu/x86/cache.h> #include <delay.h> #include <lib.h> +#include <spd.h> +#include <stdlib.h> +#include <string.h> + #include "pineview.h" #include "raminit.h" -#include <spd.h> -#include <string.h> /* Debugging macros. */ #if CONFIG(DEBUG_RAM_SETUP) diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c index 7051b24..3ae1280 100644 --- a/src/northbridge/intel/sandybridge/finalize.c +++ b/src/northbridge/intel/sandybridge/finalize.c @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <device/pci_ops.h> + #include "sandybridge.h" #define PCI_DEV_SNB PCI_DEV(0, 0, 0) diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index b6616e1..f6e6671 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -20,7 +20,6 @@ #include <stdint.h> #include <device/device.h> #include <device/pci.h> -#include <stdlib.h> #include <cpu/cpu.h> #include <boot/tables.h> #include <arch/acpi.h> diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c index 163f6b1..bba8071 100644 --- a/src/northbridge/via/vx900/chrome9hd.c +++ b/src/northbridge/via/vx900/chrome9hd.c @@ -19,7 +19,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <pc80/vga_io.h> -#include <stdlib.h> #include "vx900.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/32826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ccbca68ac7a2c049d917968310a6346353f4548 Gerrit-Change-Number: 32826 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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