coreboot-gerrit May 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: src/soc: Use 'include <stdlib.h>' when appropriate
by HAOUAS Elyes (Code Review) 28 Nov '19

28 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32828 Change subject: src/soc: Use 'include <stdlib.h>' when appropriate ...................................................................... src/soc: Use 'include <stdlib.h>' when appropriate Change-Id: I46f60f8631601db1e2e654d638560d640bbcf403 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/sm.c M src/soc/amd/stoneyridge/spi.c M src/soc/cavium/cn81xx/cbmem.c M src/soc/imgtec/pistachio/cbmem.c M src/soc/intel/baytrail/gfx.c M src/soc/intel/baytrail/ramstage.c M src/soc/intel/baytrail/smihandler.c M src/soc/intel/braswell/ramstage.c M src/soc/intel/braswell/smihandler.c M src/soc/intel/broadwell/finalize.c M src/soc/intel/broadwell/igd.c M src/soc/intel/broadwell/me_status.c M src/soc/intel/broadwell/minihd.c M src/soc/intel/broadwell/pei_data.c M src/soc/intel/broadwell/ramstage.c M src/soc/intel/broadwell/romstage/cpu.c M src/soc/intel/broadwell/romstage/power_state.c M src/soc/intel/broadwell/romstage/systemagent.c M src/soc/intel/broadwell/serialio.c M src/soc/intel/broadwell/systemagent.c M src/soc/intel/cannonlake/finalize.c M src/soc/intel/common/acpi_wake_source.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/denverton_ns/csme_ie_kt.c M src/soc/intel/denverton_ns/smihandler.c M src/soc/intel/denverton_ns/systemagent.c M src/soc/intel/fsp_baytrail/gfx.c M src/soc/intel/fsp_baytrail/include/soc/i2c.h M src/soc/intel/fsp_baytrail/ramstage.c M src/soc/intel/fsp_baytrail/smihandler.c M src/soc/intel/fsp_broadwell_de/cpu.c M src/soc/intel/fsp_broadwell_de/ramstage.c M src/soc/intel/icelake/finalize.c M src/soc/intel/icelake/pmutil.c M src/soc/intel/skylake/finalize.c M src/soc/intel/skylake/memmap.c M src/soc/intel/skylake/pmutil.c M src/soc/mediatek/mt8173/ddp.c M src/soc/mediatek/mt8173/include/soc/gpio.h M src/soc/nvidia/tegra124/clock.c M src/soc/nvidia/tegra124/display.c M src/soc/nvidia/tegra124/dma.c M src/soc/nvidia/tegra124/include/soc/clock.h M src/soc/nvidia/tegra124/sdram.c M src/soc/nvidia/tegra124/sdram_lp0.c M src/soc/nvidia/tegra124/sor.c M src/soc/nvidia/tegra124/verstage.c M src/soc/nvidia/tegra210/clock.c M src/soc/nvidia/tegra210/dma.c M src/soc/nvidia/tegra210/include/soc/clock.h M src/soc/nvidia/tegra210/include/soc/mipi-phy.h M src/soc/nvidia/tegra210/mipi-phy.c M src/soc/nvidia/tegra210/sdram.c M src/soc/nvidia/tegra210/sdram_lp0.c M src/soc/nvidia/tegra210/sor.c M src/soc/qualcomm/ipq40xx/i2c.c M src/soc/qualcomm/ipq40xx/qup.c M src/soc/qualcomm/ipq40xx/spi.c M src/soc/qualcomm/ipq40xx/uart.c M src/soc/qualcomm/ipq806x/i2c.c M src/soc/qualcomm/ipq806x/qup.c M src/soc/qualcomm/ipq806x/uart.c M src/soc/rockchip/common/gpio.c M src/soc/rockchip/common/i2c.c M src/soc/rockchip/common/include/soc/edp.h M src/soc/rockchip/common/pwm.c M src/soc/rockchip/common/rk808.c M src/soc/rockchip/common/vop.c M src/soc/rockchip/rk3288/clock.c M src/soc/rockchip/rk3288/display.c M src/soc/rockchip/rk3288/gpio.c M src/soc/rockchip/rk3288/hdmi.c M src/soc/rockchip/rk3288/include/soc/hdmi.h M src/soc/rockchip/rk3288/soc.c M src/soc/rockchip/rk3288/tsadc.c M src/soc/rockchip/rk3399/clock.c M src/soc/rockchip/rk3399/display.c M src/soc/rockchip/rk3399/gpio.c M src/soc/rockchip/rk3399/include/soc/mipi.h M src/soc/rockchip/rk3399/mipi.c M src/soc/rockchip/rk3399/saradc.c M src/soc/rockchip/rk3399/soc.c M src/soc/rockchip/rk3399/tsadc.c M src/soc/samsung/exynos5250/alternate_cbfs.c M src/soc/samsung/exynos5250/clock.c M src/soc/samsung/exynos5250/cpu.c M src/soc/samsung/exynos5250/fb.c M src/soc/samsung/exynos5420/alternate_cbfs.c M src/soc/samsung/exynos5420/clock.c M src/soc/samsung/exynos5420/cpu.c M src/soc/samsung/exynos5420/dp.c M src/soc/samsung/exynos5420/dp_lowlevel.c M src/soc/samsung/exynos5420/pinmux.c M src/soc/samsung/exynos5420/smp.c 95 files changed, 7 insertions(+), 99 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/32828/1 diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 5985832..8aada17 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -35,8 +35,8 @@ #include <soc/southbridge.h> #include <soc/pci_devs.h> #include <soc/iomap.h> +#include <stddef.h> #include <stdint.h> -#include <stdlib.h> #include <string.h> #include <arch/bert_storage.h> diff --git a/src/soc/amd/stoneyridge/sm.c b/src/soc/amd/stoneyridge/sm.c index 803e628..438909d 100644 --- a/src/soc/amd/stoneyridge/sm.c +++ b/src/soc/amd/stoneyridge/sm.c @@ -20,7 +20,6 @@ #include <device/smbus.h> #include <cpu/x86/lapic.h> #include <arch/ioapic.h> -#include <stdlib.h> #include <soc/southbridge.h> #include <soc/smbus.h> diff --git a/src/soc/amd/stoneyridge/spi.c b/src/soc/amd/stoneyridge/spi.c index c682d98..9f787da 100644 --- a/src/soc/amd/stoneyridge/spi.c +++ b/src/soc/amd/stoneyridge/spi.c @@ -14,7 +14,6 @@ */ #include <stdint.h> -#include <stdlib.h> #include <device/mmio.h> #include <lib.h> #include <timer.h> @@ -27,6 +26,7 @@ #include <device/pci_ops.h> #include <soc/southbridge.h> #include <soc/pci_devs.h> +#include <stddef.h> #define SPI_DEBUG_DRIVER CONFIG(DEBUG_SPI_FLASH) diff --git a/src/soc/cavium/cn81xx/cbmem.c b/src/soc/cavium/cn81xx/cbmem.c index bb6fa18..5a4ad19 100644 --- a/src/soc/cavium/cn81xx/cbmem.c +++ b/src/soc/cavium/cn81xx/cbmem.c @@ -17,7 +17,6 @@ #include <cbmem.h> #include <soc/addressmap.h> #include <soc/sdram.h> -#include <stdlib.h> #include <symbols.h> void *cbmem_top(void) diff --git a/src/soc/imgtec/pistachio/cbmem.c b/src/soc/imgtec/pistachio/cbmem.c index 112df7c..964300e 100644 --- a/src/soc/imgtec/pistachio/cbmem.c +++ b/src/soc/imgtec/pistachio/cbmem.c @@ -15,7 +15,6 @@ */ #include <cbmem.h> -#include <stdlib.h> #include <symbols.h> void *cbmem_top(void) diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 2048c13..ab30785 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -21,7 +21,6 @@ #include <device/pci_ids.h> #include <drivers/intel/gma/opregion.h> #include <reg_script.h> -#include <stdlib.h> #include <soc/gfx.h> #include <soc/iosf.h> #include <soc/nvs.h> diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 1715198..eb3e327 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -23,9 +23,7 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <stdlib.h> #include <string.h> - #include <soc/gpio.h> #include <soc/lpc.h> #include <soc/msr.h> diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c index 1bc9ed1..3679b55 100644 --- a/src/soc/intel/baytrail/smihandler.c +++ b/src/soc/intel/baytrail/smihandler.c @@ -14,7 +14,6 @@ */ #include <stdint.h> -#include <stdlib.h> #include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index d6a1cda..f8011fd 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -37,7 +37,6 @@ #include <soc/ramstage.h> #include <soc/intel/common/acpi.h> #include <boardid.h> -#include <stdlib.h> #include <string.h> #define SHOW_PATTRS 1 diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index a723309..f9d931e 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -28,7 +28,6 @@ #include <soc/pm.h> #include <spi-generic.h> #include <stdint.h> -#include <stdlib.h> #include <soc/gpio.h> /* GNVS needs to be set by coreboot initiating a software SMI. */ diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 1adbbc8..f270f9b 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -20,7 +20,6 @@ #include <cpu/x86/smm.h> #include <reg_script.h> #include <spi-generic.h> -#include <stdlib.h> #include <soc/pci_devs.h> #include <soc/lpc.h> #include <soc/me.h> diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index 9107b23..d539183 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -22,7 +22,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <stdlib.h> #include <string.h> #include <reg_script.h> #include <cbmem.h> diff --git a/src/soc/intel/broadwell/me_status.c b/src/soc/intel/broadwell/me_status.c index 08fd48f..3b2c680 100644 --- a/src/soc/intel/broadwell/me_status.c +++ b/src/soc/intel/broadwell/me_status.c @@ -16,7 +16,6 @@ #include <device/pci_ops.h> #include <console/console.h> #include <device/pci.h> -#include <stdlib.h> #include <string.h> #include <soc/pci_devs.h> #include <soc/me.h> diff --git a/src/soc/intel/broadwell/minihd.c b/src/soc/intel/broadwell/minihd.c index d44e153..ff12ac5 100644 --- a/src/soc/intel/broadwell/minihd.c +++ b/src/soc/intel/broadwell/minihd.c @@ -21,7 +21,6 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/mmio.h> -#include <stdlib.h> #include <soc/intel/common/hda_verb.h> #include <soc/ramstage.h> #include <soc/igd.h> diff --git a/src/soc/intel/broadwell/pei_data.c b/src/soc/intel/broadwell/pei_data.c index d8059ec..0a3ec5a 100644 --- a/src/soc/intel/broadwell/pei_data.c +++ b/src/soc/intel/broadwell/pei_data.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <stdint.h> #include <console/streams.h> #include <soc/iomap.h> diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c index 7065369..bad9f96 100644 --- a/src/soc/intel/broadwell/ramstage.c +++ b/src/soc/intel/broadwell/ramstage.c @@ -16,7 +16,6 @@ #include <arch/acpi.h> #include <cbmem.h> #include <device/device.h> -#include <stdlib.h> #include <string.h> #include <soc/nvs.h> #include <soc/pm.h> diff --git a/src/soc/intel/broadwell/romstage/cpu.c b/src/soc/intel/broadwell/romstage/cpu.c index f251652..5a45697 100644 --- a/src/soc/intel/broadwell/romstage/cpu.c +++ b/src/soc/intel/broadwell/romstage/cpu.c @@ -14,7 +14,6 @@ */ #include <arch/cpu.h> -#include <stdlib.h> #include <console/console.h> #include <cpu/x86/msr.h> #include <soc/cpu.h> diff --git a/src/soc/intel/broadwell/romstage/power_state.c b/src/soc/intel/broadwell/romstage/power_state.c index ca22b4e..1970c31 100644 --- a/src/soc/intel/broadwell/romstage/power_state.c +++ b/src/soc/intel/broadwell/romstage/power_state.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <reg_script.h> #include <stdint.h> -#include <stdlib.h> #include <string.h> #include <soc/iomap.h> #include <soc/lpc.h> diff --git a/src/soc/intel/broadwell/romstage/systemagent.c b/src/soc/intel/broadwell/romstage/systemagent.c index 8be5b82..5c0224a 100644 --- a/src/soc/intel/broadwell/romstage/systemagent.c +++ b/src/soc/intel/broadwell/romstage/systemagent.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <device/mmio.h> #include <device/pci_ops.h> #include <device/pci_def.h> diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c index 12e458c..58a0444 100644 --- a/src/soc/intel/broadwell/serialio.c +++ b/src/soc/intel/broadwell/serialio.c @@ -20,7 +20,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <stdlib.h> #include <soc/iobp.h> #include <soc/nvs.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index c6444b1..9af55c9 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -22,7 +22,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <stdlib.h> #include <vendorcode/google/chromeos/chromeos.h> #include <soc/cpu.h> #include <soc/iomap.h> diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 4dfd15b..c284263 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -32,7 +32,6 @@ #include <soc/pm.h> #include <soc/smbus.h> #include <soc/systemagent.h> -#include <stdlib.h> #include "chip.h" diff --git a/src/soc/intel/common/acpi_wake_source.c b/src/soc/intel/common/acpi_wake_source.c index f66706c..d3955fd 100644 --- a/src/soc/intel/common/acpi_wake_source.c +++ b/src/soc/intel/common/acpi_wake_source.c @@ -19,7 +19,7 @@ #include <console/console.h> #include <soc/nvs.h> #include <stdint.h> -#include <stdlib.h> + #include "acpi.h" __weak int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0) diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 7aa69c5..39be081 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -35,7 +35,6 @@ #include <soc/smbus.h> #include <spi-generic.h> #include <stdint.h> -#include <stdlib.h> /* GNVS needs to be set by coreboot initiating a software SMI. */ static struct global_nvs_t *gnvs; diff --git a/src/soc/intel/denverton_ns/csme_ie_kt.c b/src/soc/intel/denverton_ns/csme_ie_kt.c index 5967840..143e7b6 100644 --- a/src/soc/intel/denverton_ns/csme_ie_kt.c +++ b/src/soc/intel/denverton_ns/csme_ie_kt.c @@ -15,7 +15,6 @@ */ #include <stdint.h> -#include <stdlib.h> #include <device/pci.h> #include <device/pci_ids.h> #include <console/console.h> diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index 4d748b2..d8e967f 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -16,7 +16,6 @@ */ #include <stdint.h> -#include <stdlib.h> #include <arch/hlt.h> #include <arch/io.h> #include <device/pci_ops.h> diff --git a/src/soc/intel/denverton_ns/systemagent.c b/src/soc/intel/denverton_ns/systemagent.c index cc1d696..3d77e21 100644 --- a/src/soc/intel/denverton_ns/systemagent.c +++ b/src/soc/intel/denverton_ns/systemagent.c @@ -23,9 +23,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <stdlib.h> #include <timer.h> - #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> diff --git a/src/soc/intel/fsp_baytrail/gfx.c b/src/soc/intel/fsp_baytrail/gfx.c index dab9972..7029067 100644 --- a/src/soc/intel/fsp_baytrail/gfx.c +++ b/src/soc/intel/fsp_baytrail/gfx.c @@ -19,7 +19,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <reg_script.h> -#include <stdlib.h> #include <soc/gfx.h> #include <soc/iosf.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/fsp_baytrail/include/soc/i2c.h b/src/soc/intel/fsp_baytrail/include/soc/i2c.h index f0ae0b3..a966fe4 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/i2c.h +++ b/src/soc/intel/fsp_baytrail/include/soc/i2c.h @@ -17,7 +17,6 @@ #define __SOC_INTEL_FSP_BAYTRAIL_I2C_H__ #include <device/pci_def.h> -#include <stdlib.h> /* SMBus controller settings in PCI configuration space */ #define I2C_PCI_VENDOR_ID 0x8086 diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c index 754c5f5..29cfc62 100644 --- a/src/soc/intel/fsp_baytrail/ramstage.c +++ b/src/soc/intel/fsp_baytrail/ramstage.c @@ -23,9 +23,7 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <stdlib.h> #include <string.h> - #include <soc/gpio.h> #include <soc/lpc.h> #include <soc/nvs.h> diff --git a/src/soc/intel/fsp_baytrail/smihandler.c b/src/soc/intel/fsp_baytrail/smihandler.c index f2abd99..7eedfac 100644 --- a/src/soc/intel/fsp_baytrail/smihandler.c +++ b/src/soc/intel/fsp_baytrail/smihandler.c @@ -14,7 +14,6 @@ */ #include <stdint.h> -#include <stdlib.h> #include <arch/io.h> #include <device/pci_ops.h> #include <console/console.h> @@ -23,7 +22,6 @@ #include <device/pci_def.h> #include <elog.h> #include <halt.h> - #include <soc/pci_devs.h> #include <soc/pmc.h> #include <soc/nvs.h> diff --git a/src/soc/intel/fsp_broadwell_de/cpu.c b/src/soc/intel/fsp_broadwell_de/cpu.c index 0b933c5..4814596 100644 --- a/src/soc/intel/fsp_broadwell_de/cpu.c +++ b/src/soc/intel/fsp_broadwell_de/cpu.c @@ -15,7 +15,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <console/console.h> #include <cpu/cpu.h> #include <cpu/intel/microcode.h> diff --git a/src/soc/intel/fsp_broadwell_de/ramstage.c b/src/soc/intel/fsp_broadwell_de/ramstage.c index 96b3888..e892c5b 100644 --- a/src/soc/intel/fsp_broadwell_de/ramstage.c +++ b/src/soc/intel/fsp_broadwell_de/ramstage.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <arch/cpu.h> #include <console/console.h> #include <cpu/intel/microcode.h> diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c index e061cda..2cf167f 100644 --- a/src/soc/intel/icelake/finalize.c +++ b/src/soc/intel/icelake/finalize.c @@ -31,7 +31,6 @@ #include <soc/pm.h> #include <soc/smbus.h> #include <soc/systemagent.h> -#include <stdlib.h> #include "chip.h" diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index 1c47783..ec81cfe 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -29,7 +29,6 @@ #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> #include <intelblocks/tco.h> -#include <stdlib.h> #include <soc/gpe.h> #include <soc/gpio.h> #include <soc/iomap.h> @@ -38,6 +37,7 @@ #include <soc/pm.h> #include <soc/smbus.h> #include <security/vboot/vbnv.h> +#include <stddef.h> #include "chip.h" diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index 5d7e1e0..0248a54 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -37,7 +37,6 @@ #include <soc/smbus.h> #include <soc/systemagent.h> #include <soc/thermal.h> -#include <stdlib.h> #include <timer.h> #include "chip.h" diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index ff7edbc..575a3f8 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -26,7 +26,7 @@ #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/systemagent.h> -#include <stdlib.h> +#include <stddef.h> #include "chip.h" diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 7d0dc0a..62eabab 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -29,7 +29,6 @@ #include <intelblocks/pmclib.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/tco.h> -#include <stdlib.h> #include <soc/gpe.h> #include <soc/gpio.h> #include <soc/iomap.h> @@ -38,6 +37,7 @@ #include <soc/pmc.h> #include <soc/smbus.h> #include <security/vboot/vbnv.h> +#include <stddef.h> #include "chip.h" diff --git a/src/soc/mediatek/mt8173/ddp.c b/src/soc/mediatek/mt8173/ddp.c index f8896d3..a335ff2 100644 --- a/src/soc/mediatek/mt8173/ddp.c +++ b/src/soc/mediatek/mt8173/ddp.c @@ -15,7 +15,6 @@ #include <device/mmio.h> #include <edid.h> -#include <stdlib.h> #include <stddef.h> #include <soc/addressmap.h> #include <soc/ddp.h> diff --git a/src/soc/mediatek/mt8173/include/soc/gpio.h b/src/soc/mediatek/mt8173/include/soc/gpio.h index ec08334..8a6e13a 100644 --- a/src/soc/mediatek/mt8173/include/soc/gpio.h +++ b/src/soc/mediatek/mt8173/include/soc/gpio.h @@ -16,7 +16,6 @@ #define SOC_MEDIATEK_MT8173_GPIO_H #include <stdint.h> -#include <stdlib.h> #include <soc/addressmap.h> #include <soc/gpio_common.h> diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index 6877c04..3c8ddb2 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -24,7 +24,6 @@ #include <soc/maincpu.h> #include <soc/pmc.h> #include <soc/sysctr.h> -#include <stdlib.h> #include <symbols.h> static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 51f7215..6fa3bdf 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -26,7 +26,6 @@ #include <soc/nvidia/tegra/dc.h> #include <soc/nvidia/tegra/pwm.h> #include <stdint.h> -#include <stdlib.h> #include <string.h> #include "chip.h" diff --git a/src/soc/nvidia/tegra124/dma.c b/src/soc/nvidia/tegra124/dma.c index 73d050f..a0bd5c0 100644 --- a/src/soc/nvidia/tegra124/dma.c +++ b/src/soc/nvidia/tegra124/dma.c @@ -21,7 +21,6 @@ #include <soc/addressmap.h> #include <soc/dma.h> #include <stddef.h> -#include <stdlib.h> struct apb_dma * const apb_dma = (struct apb_dma *)TEGRA_APB_DMA_BASE; diff --git a/src/soc/nvidia/tegra124/include/soc/clock.h b/src/soc/nvidia/tegra124/include/soc/clock.h index 00744ce..5538b78 100644 --- a/src/soc/nvidia/tegra124/include/soc/clock.h +++ b/src/soc/nvidia/tegra124/include/soc/clock.h @@ -22,7 +22,6 @@ #include <device/mmio.h> #include <soc/clk_rst.h> #include <stdint.h> -#include <stdlib.h> enum { CLK_L_CPU = 0x1 << 0, diff --git a/src/soc/nvidia/tegra124/sdram.c b/src/soc/nvidia/tegra124/sdram.c index 9af116c..7c5d304 100644 --- a/src/soc/nvidia/tegra124/sdram.c +++ b/src/soc/nvidia/tegra124/sdram.c @@ -22,7 +22,6 @@ #include <soc/mc.h> #include <soc/pmc.h> #include <soc/sdram.h> -#include <stdlib.h> #include <symbols.h> diff --git a/src/soc/nvidia/tegra124/sdram_lp0.c b/src/soc/nvidia/tegra124/sdram_lp0.c index 731fc61..aade07c 100644 --- a/src/soc/nvidia/tegra124/sdram_lp0.c +++ b/src/soc/nvidia/tegra124/sdram_lp0.c @@ -20,7 +20,6 @@ #include <soc/clk_rst.h> #include <soc/pmc.h> #include <soc/sdram.h> -#include <stdlib.h> /* * This function reads SDRAM parameters (and a few CLK_RST register values) from diff --git a/src/soc/nvidia/tegra124/sor.c b/src/soc/nvidia/tegra124/sor.c index 9188f83..8c03a7e 100644 --- a/src/soc/nvidia/tegra124/sor.c +++ b/src/soc/nvidia/tegra124/sor.c @@ -29,7 +29,6 @@ #include <soc/nvidia/tegra/displayport.h> #include <soc/sor.h> #include <stdint.h> -#include <stdlib.h> #include "chip.h" diff --git a/src/soc/nvidia/tegra124/verstage.c b/src/soc/nvidia/tegra124/verstage.c index 2495351..9899fcb 100644 --- a/src/soc/nvidia/tegra124/verstage.c +++ b/src/soc/nvidia/tegra124/verstage.c @@ -20,7 +20,6 @@ #include <program_loading.h> #include <soc/cache.h> #include <soc/early_configs.h> -#include <stdlib.h> #include <symbols.h> #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/soc/nvidia/tegra210/clock.c b/src/soc/nvidia/tegra210/clock.c index 55ee50b..236a450 100644 --- a/src/soc/nvidia/tegra210/clock.c +++ b/src/soc/nvidia/tegra210/clock.c @@ -18,7 +18,6 @@ #include <assert.h> #include <console/console.h> #include <delay.h> -#include <stdlib.h> #include <soc/addressmap.h> #include <soc/clk_rst.h> #include <soc/clock.h> diff --git a/src/soc/nvidia/tegra210/dma.c b/src/soc/nvidia/tegra210/dma.c index 03c5e67..bbc5c8f 100644 --- a/src/soc/nvidia/tegra210/dma.c +++ b/src/soc/nvidia/tegra210/dma.c @@ -21,7 +21,6 @@ #include <soc/addressmap.h> #include <soc/dma.h> #include <stddef.h> -#include <stdlib.h> struct apb_dma * const apb_dma = (struct apb_dma *)TEGRA_APB_DMA_BASE; diff --git a/src/soc/nvidia/tegra210/include/soc/clock.h b/src/soc/nvidia/tegra210/include/soc/clock.h index 6d8c338..3694285 100644 --- a/src/soc/nvidia/tegra210/include/soc/clock.h +++ b/src/soc/nvidia/tegra210/include/soc/clock.h @@ -22,7 +22,6 @@ #include <device/mmio.h> #include <soc/clk_rst.h> #include <stdint.h> -#include <stdlib.h> enum { CLK_L_CPU = 0x1 << 0, diff --git a/src/soc/nvidia/tegra210/include/soc/mipi-phy.h b/src/soc/nvidia/tegra210/include/soc/mipi-phy.h index 852c5a3..e9b5797 100644 --- a/src/soc/nvidia/tegra210/include/soc/mipi-phy.h +++ b/src/soc/nvidia/tegra210/include/soc/mipi-phy.h @@ -15,7 +15,6 @@ #ifndef _TEGRA_MIPI_PHY_H #define _TEGRA_MIPI_PHY_H -#include <stdlib.h> /* * Macros for calculating the phy timings diff --git a/src/soc/nvidia/tegra210/mipi-phy.c b/src/soc/nvidia/tegra210/mipi-phy.c index 4e56730..72dd57d 100644 --- a/src/soc/nvidia/tegra210/mipi-phy.c +++ b/src/soc/nvidia/tegra210/mipi-phy.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <stdlib.h> #include <soc/addressmap.h> #include <soc/clock.h> #include <device/device.h> diff --git a/src/soc/nvidia/tegra210/sdram.c b/src/soc/nvidia/tegra210/sdram.c index e1d91fd..c609921 100644 --- a/src/soc/nvidia/tegra210/sdram.c +++ b/src/soc/nvidia/tegra210/sdram.c @@ -23,7 +23,6 @@ #include <soc/mc.h> #include <soc/pmc.h> #include <soc/sdram.h> -#include <stdlib.h> #include <soc/nvidia/tegra/apbmisc.h> static void sdram_patch(uintptr_t addr, uint32_t value) diff --git a/src/soc/nvidia/tegra210/sdram_lp0.c b/src/soc/nvidia/tegra210/sdram_lp0.c index 9eaf5f0..09747ea 100644 --- a/src/soc/nvidia/tegra210/sdram_lp0.c +++ b/src/soc/nvidia/tegra210/sdram_lp0.c @@ -19,7 +19,6 @@ #include <soc/addressmap.h> #include <soc/pmc.h> #include <soc/sdram.h> -#include <stdlib.h> /* * This function reads SDRAM parameters from the common BCT format and diff --git a/src/soc/nvidia/tegra210/sor.c b/src/soc/nvidia/tegra210/sor.c index 3055b29..8caf050 100644 --- a/src/soc/nvidia/tegra210/sor.c +++ b/src/soc/nvidia/tegra210/sor.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <stdint.h> -#include <stdlib.h> #include <delay.h> #include <soc/addressmap.h> #include <device/device.h> diff --git a/src/soc/qualcomm/ipq40xx/i2c.c b/src/soc/qualcomm/ipq40xx/i2c.c index f20dada..7262bb0 100644 --- a/src/soc/qualcomm/ipq40xx/i2c.c +++ b/src/soc/qualcomm/ipq40xx/i2c.c @@ -31,7 +31,6 @@ #include <console/console.h> #include <device/i2c_simple.h> -#include <stdlib.h> #include <string.h> #include <soc/blsp.h> #include <soc/qup.h> diff --git a/src/soc/qualcomm/ipq40xx/qup.c b/src/soc/qualcomm/ipq40xx/qup.c index 438bd14..f708892 100644 --- a/src/soc/qualcomm/ipq40xx/qup.c +++ b/src/soc/qualcomm/ipq40xx/qup.c @@ -33,7 +33,6 @@ #include <console/console.h> #include <delay.h> #include <soc/iomap.h> -#include <stdlib.h> #include <soc/qup.h> #define TIMEOUT_CNT 100 diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c index b68e1cb..72a5b9d 100644 --- a/src/soc/qualcomm/ipq40xx/spi.c +++ b/src/soc/qualcomm/ipq40xx/spi.c @@ -33,7 +33,7 @@ #include <gpio.h> #include <soc/iomap.h> #include <soc/spi.h> -#include <stdlib.h> +#include <stddef.h> static const struct blsp_spi spi_reg[] = { /* BLSP0 registers for SPI interface */ diff --git a/src/soc/qualcomm/ipq40xx/uart.c b/src/soc/qualcomm/ipq40xx/uart.c index eb3731b..d17a926 100644 --- a/src/soc/qualcomm/ipq40xx/uart.c +++ b/src/soc/qualcomm/ipq40xx/uart.c @@ -37,7 +37,6 @@ #include <soc/blsp.h> #include <soc/ipq_uart.h> #include <stdint.h> -#include <stdlib.h> #define FIFO_DATA_SIZE 4 diff --git a/src/soc/qualcomm/ipq806x/i2c.c b/src/soc/qualcomm/ipq806x/i2c.c index c81373f..652215e 100644 --- a/src/soc/qualcomm/ipq806x/i2c.c +++ b/src/soc/qualcomm/ipq806x/i2c.c @@ -29,7 +29,6 @@ #include <console/console.h> #include <device/i2c_simple.h> -#include <stdlib.h> #include <string.h> #include <soc/gsbi.h> #include <soc/qup.h> diff --git a/src/soc/qualcomm/ipq806x/qup.c b/src/soc/qualcomm/ipq806x/qup.c index 3ceb84d..b9fc95d 100644 --- a/src/soc/qualcomm/ipq806x/qup.c +++ b/src/soc/qualcomm/ipq806x/qup.c @@ -31,7 +31,6 @@ #include <console/console.h> #include <delay.h> #include <soc/iomap.h> -#include <stdlib.h> #include <soc/qup.h> #define TIMEOUT_CNT 100000 diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c index 66c3103..e662d59 100644 --- a/src/soc/qualcomm/ipq806x/uart.c +++ b/src/soc/qualcomm/ipq806x/uart.c @@ -40,7 +40,6 @@ #include <soc/gsbi.h> #include <soc/ipq_uart.h> #include <stdint.h> -#include <stdlib.h> #define FIFO_DATA_SIZE 4 diff --git a/src/soc/rockchip/common/gpio.c b/src/soc/rockchip/common/gpio.c index 3d7e161..223ed27 100644 --- a/src/soc/rockchip/common/gpio.c +++ b/src/soc/rockchip/common/gpio.c @@ -19,7 +19,6 @@ #include <soc/gpio.h> #include <soc/grf.h> #include <soc/soc.h> -#include <stdlib.h> #include <types.h> static void gpio_set_dir(gpio_t gpio, enum gpio_dir dir) diff --git a/src/soc/rockchip/common/i2c.c b/src/soc/rockchip/common/i2c.c index e5f5a9a..4df6e0e 100644 --- a/src/soc/rockchip/common/i2c.c +++ b/src/soc/rockchip/common/i2c.c @@ -23,7 +23,6 @@ #include <soc/soc.h> #include <soc/i2c.h> #include <soc/clock.h> -#include <stdlib.h> #define RETRY_COUNT 3 /* 100000us = 100ms */ diff --git a/src/soc/rockchip/common/include/soc/edp.h b/src/soc/rockchip/common/include/soc/edp.h index a9ebbc5..58986d1 100644 --- a/src/soc/rockchip/common/include/soc/edp.h +++ b/src/soc/rockchip/common/include/soc/edp.h @@ -17,7 +17,6 @@ #define __RK_DP_H #include <edid.h> -#include <stdlib.h> struct rk_edp_regs { u8 res0[0x10]; diff --git a/src/soc/rockchip/common/pwm.c b/src/soc/rockchip/common/pwm.c index e5da05e..98ef21f 100644 --- a/src/soc/rockchip/common/pwm.c +++ b/src/soc/rockchip/common/pwm.c @@ -19,7 +19,6 @@ #include <soc/soc.h> #include <soc/pwm.h> #include <soc/clock.h> -#include <stdlib.h> #include <timer.h> struct pwm_ctl { diff --git a/src/soc/rockchip/common/rk808.c b/src/soc/rockchip/common/rk808.c index 58d910c..66a085c 100644 --- a/src/soc/rockchip/common/rk808.c +++ b/src/soc/rockchip/common/rk808.c @@ -21,7 +21,6 @@ #include <rtc.h> #include <soc/rk808.h> #include <stdint.h> -#include <stdlib.h> #if CONFIG_PMIC_BUS < 0 #error "PMIC_BUS must be set in mainboard's Kconfig." diff --git a/src/soc/rockchip/common/vop.c b/src/soc/rockchip/common/vop.c index 9c70b78..f617b4a 100644 --- a/src/soc/rockchip/common/vop.c +++ b/src/soc/rockchip/common/vop.c @@ -14,7 +14,6 @@ */ #include <device/mmio.h> -#include <stdlib.h> #include <stddef.h> #include <soc/addressmap.h> #include <soc/clock.h> diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index cee1ee2..6e0c139 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -24,7 +24,6 @@ #include <soc/i2c.h> #include <soc/soc.h> #include <stdint.h> -#include <stdlib.h> #include <string.h> struct pll_div { diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c index 04a5992..a66b2d4 100644 --- a/src/soc/rockchip/rk3288/display.c +++ b/src/soc/rockchip/rk3288/display.c @@ -20,7 +20,6 @@ #include <delay.h> #include <edid.h> #include <gpio.h> -#include <stdlib.h> #include <stddef.h> #include <string.h> #include <soc/addressmap.h> diff --git a/src/soc/rockchip/rk3288/gpio.c b/src/soc/rockchip/rk3288/gpio.c index 0f9d85c..8eeed88 100644 --- a/src/soc/rockchip/rk3288/gpio.c +++ b/src/soc/rockchip/rk3288/gpio.c @@ -18,7 +18,6 @@ #include <soc/grf.h> #include <soc/pmu.h> #include <soc/soc.h> -#include <stdlib.h> struct rockchip_gpio_regs *gpio_port[] = { (struct rockchip_gpio_regs *)0xff750000, diff --git a/src/soc/rockchip/rk3288/hdmi.c b/src/soc/rockchip/rk3288/hdmi.c index b4de270..9616ee8 100644 --- a/src/soc/rockchip/rk3288/hdmi.c +++ b/src/soc/rockchip/rk3288/hdmi.c @@ -24,7 +24,6 @@ #include <delay.h> #include <edid.h> #include <gpio.h> -#include <stdlib.h> #include <stdint.h> #include <soc/addressmap.h> #include <soc/hdmi.h> diff --git a/src/soc/rockchip/rk3288/include/soc/hdmi.h b/src/soc/rockchip/rk3288/include/soc/hdmi.h index fb20b4a..3089949 100644 --- a/src/soc/rockchip/rk3288/include/soc/hdmi.h +++ b/src/soc/rockchip/rk3288/include/soc/hdmi.h @@ -19,7 +19,6 @@ #define __SOC_HDMI_H__ #include <types.h> -#include <stdlib.h> #define HDMI_EDID_BLOCK_SIZE 128 diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c index bda9553..31c9998 100644 --- a/src/soc/rockchip/rk3288/soc.c +++ b/src/soc/rockchip/rk3288/soc.c @@ -22,7 +22,6 @@ #include <soc/soc.h> #include <soc/sdram.h> #include <stddef.h> -#include <stdlib.h> #include <symbols.h> #include "chip.h" diff --git a/src/soc/rockchip/rk3288/tsadc.c b/src/soc/rockchip/rk3288/tsadc.c index 3223a4d..7e5823c 100644 --- a/src/soc/rockchip/rk3288/tsadc.c +++ b/src/soc/rockchip/rk3288/tsadc.c @@ -19,7 +19,6 @@ #include <soc/pmu.h> #include <soc/tsadc.h> #include <stdint.h> -#include <stdlib.h> struct rk3288_tsadc_regs { u32 user_con; diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 5252232..9364ecf 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -23,7 +23,6 @@ #include <soc/i2c.h> #include <soc/soc.h> #include <stdint.h> -#include <stdlib.h> #include <string.h> struct pll_div { diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c index e2e9f7d..9cd4053 100644 --- a/src/soc/rockchip/rk3399/display.c +++ b/src/soc/rockchip/rk3399/display.c @@ -21,7 +21,6 @@ #include <delay.h> #include <edid.h> #include <gpio.h> -#include <stdlib.h> #include <stddef.h> #include <soc/addressmap.h> #include <soc/clock.h> diff --git a/src/soc/rockchip/rk3399/gpio.c b/src/soc/rockchip/rk3399/gpio.c index 7fe2c19..9a01abc 100644 --- a/src/soc/rockchip/rk3399/gpio.c +++ b/src/soc/rockchip/rk3399/gpio.c @@ -18,7 +18,6 @@ #include <soc/gpio.h> #include <soc/grf.h> #include <soc/soc.h> -#include <stdlib.h> struct rockchip_gpio_regs *gpio_port[] = { (struct rockchip_gpio_regs *)GPIO0_BASE, diff --git a/src/soc/rockchip/rk3399/include/soc/mipi.h b/src/soc/rockchip/rk3399/include/soc/mipi.h index 43ab7b9..469a052 100644 --- a/src/soc/rockchip/rk3399/include/soc/mipi.h +++ b/src/soc/rockchip/rk3399/include/soc/mipi.h @@ -16,7 +16,6 @@ #ifndef __RK_MIPI_H #define __RK_MIPI_H -#include <stdlib.h> #include <types.h> struct rk_mipi_regs { diff --git a/src/soc/rockchip/rk3399/mipi.c b/src/soc/rockchip/rk3399/mipi.c index 1f3f02c..aebc90f 100644 --- a/src/soc/rockchip/rk3399/mipi.c +++ b/src/soc/rockchip/rk3399/mipi.c @@ -19,7 +19,6 @@ #include <device/device.h> #include <edid.h> #include <gpio.h> -#include <stdlib.h> #include <string.h> #include <soc/addressmap.h> #include <soc/clock.h> diff --git a/src/soc/rockchip/rk3399/saradc.c b/src/soc/rockchip/rk3399/saradc.c index 3c6cbe6..8dd3cb4 100644 --- a/src/soc/rockchip/rk3399/saradc.c +++ b/src/soc/rockchip/rk3399/saradc.c @@ -20,7 +20,6 @@ #include <soc/clock.h> #include <soc/saradc.h> #include <stdint.h> -#include <stdlib.h> #include <timer.h> struct rk3399_saradc_regs { diff --git a/src/soc/rockchip/rk3399/soc.c b/src/soc/rockchip/rk3399/soc.c index 3f3ff97..807a7bc 100644 --- a/src/soc/rockchip/rk3399/soc.c +++ b/src/soc/rockchip/rk3399/soc.c @@ -23,7 +23,6 @@ #include <soc/sdram.h> #include <soc/symbols.h> #include <stddef.h> -#include <stdlib.h> #include <symbols.h> void bootmem_platform_add_ranges(void) diff --git a/src/soc/rockchip/rk3399/tsadc.c b/src/soc/rockchip/rk3399/tsadc.c index 7ec24648..b81aa93 100644 --- a/src/soc/rockchip/rk3399/tsadc.c +++ b/src/soc/rockchip/rk3399/tsadc.c @@ -19,7 +19,6 @@ #include <soc/grf.h> #include <soc/tsadc.h> #include <stdint.h> -#include <stdlib.h> struct rk3399_tsadc_regs { u32 user_con; diff --git a/src/soc/samsung/exynos5250/alternate_cbfs.c b/src/soc/samsung/exynos5250/alternate_cbfs.c index e431672..5fb69c9 100644 --- a/src/soc/samsung/exynos5250/alternate_cbfs.c +++ b/src/soc/samsung/exynos5250/alternate_cbfs.c @@ -18,7 +18,6 @@ #include <soc/alternate_cbfs.h> #include <soc/power.h> #include <soc/spi.h> -#include <stdlib.h> #include <symbols.h> /* This allows USB A-A firmware upload from a compatible host in four parts: diff --git a/src/soc/samsung/exynos5250/clock.c b/src/soc/samsung/exynos5250/clock.c index 7e7fe97..1006a98 100644 --- a/src/soc/samsung/exynos5250/clock.c +++ b/src/soc/samsung/exynos5250/clock.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <soc/clk.h> #include <soc/periph.h> -#include <stdlib.h> #include <timer.h> /* input clock of PLL: SMDK5250 has 24MHz input clock */ diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c index f00351e..5f99899 100644 --- a/src/soc/samsung/exynos5250/cpu.c +++ b/src/soc/samsung/exynos5250/cpu.c @@ -23,7 +23,6 @@ #include <soc/dp-core.h> #include <soc/fimd.h> #include <stddef.h> -#include <stdlib.h> #include <string.h> #include "chip.h" diff --git a/src/soc/samsung/exynos5250/fb.c b/src/soc/samsung/exynos5250/fb.c index 64980a1..8181c29 100644 --- a/src/soc/samsung/exynos5250/fb.c +++ b/src/soc/samsung/exynos5250/fb.c @@ -25,7 +25,6 @@ #include <soc/i2c.h> #include <soc/power.h> #include <soc/sysreg.h> -#include <stdlib.h> #include <timer.h> /* diff --git a/src/soc/samsung/exynos5420/alternate_cbfs.c b/src/soc/samsung/exynos5420/alternate_cbfs.c index ba3f9a3..93a4d3f 100644 --- a/src/soc/samsung/exynos5420/alternate_cbfs.c +++ b/src/soc/samsung/exynos5420/alternate_cbfs.c @@ -19,7 +19,6 @@ #include <soc/alternate_cbfs.h> #include <soc/power.h> #include <soc/spi.h> -#include <stdlib.h> #include <symbols.h> /* This allows USB A-A firmware upload from a compatible host in four parts: diff --git a/src/soc/samsung/exynos5420/clock.c b/src/soc/samsung/exynos5420/clock.c index 720506c..5a7467c 100644 --- a/src/soc/samsung/exynos5420/clock.c +++ b/src/soc/samsung/exynos5420/clock.c @@ -18,7 +18,6 @@ #include <console/console.h> #include <soc/clk.h> #include <soc/periph.h> -#include <stdlib.h> #include <timer.h> /* input clock of PLL: SMDK5420 has 24MHz input clock */ diff --git a/src/soc/samsung/exynos5420/cpu.c b/src/soc/samsung/exynos5420/cpu.c index 55b0512..375b370 100644 --- a/src/soc/samsung/exynos5420/cpu.c +++ b/src/soc/samsung/exynos5420/cpu.c @@ -24,7 +24,6 @@ #include <soc/cpu.h> #include <soc/clk.h> #include <stddef.h> -#include <stdlib.h> #include <string.h> #include "chip.h" diff --git a/src/soc/samsung/exynos5420/dp.c b/src/soc/samsung/exynos5420/dp.c index 5ad3dd3..c48ea8c 100644 --- a/src/soc/samsung/exynos5420/dp.c +++ b/src/soc/samsung/exynos5420/dp.c @@ -21,7 +21,6 @@ #include <soc/i2c.h> #include <soc/power.h> #include <soc/sysreg.h> -#include <stdlib.h> #include <string.h> /* diff --git a/src/soc/samsung/exynos5420/dp_lowlevel.c b/src/soc/samsung/exynos5420/dp_lowlevel.c index 164704b..df579b0 100644 --- a/src/soc/samsung/exynos5420/dp_lowlevel.c +++ b/src/soc/samsung/exynos5420/dp_lowlevel.c @@ -22,7 +22,6 @@ #include <soc/i2c.h> #include <soc/power.h> #include <soc/sysreg.h> -#include <stdlib.h> /* FIXME: I think the DP controller shouldn't be hardcoded here... */ static struct exynos_dp * const dp_regs = (void *)EXYNOS5_DP1_BASE; diff --git a/src/soc/samsung/exynos5420/pinmux.c b/src/soc/samsung/exynos5420/pinmux.c index 999afa0..347c669 100644 --- a/src/soc/samsung/exynos5420/pinmux.c +++ b/src/soc/samsung/exynos5420/pinmux.c @@ -15,7 +15,6 @@ #include <soc/gpio.h> #include <soc/pinmux.h> -#include <stdlib.h> static void exynos_pinmux_uart(int start, int count) { diff --git a/src/soc/samsung/exynos5420/smp.c b/src/soc/samsung/exynos5420/smp.c index 5e16063..27c0fa6 100644 --- a/src/soc/samsung/exynos5420/smp.c +++ b/src/soc/samsung/exynos5420/smp.c @@ -18,7 +18,6 @@ #include <device/mmio.h> #include <soc/cpu.h> #include <soc/power.h> -#include <stdlib.h> #include <string.h> #include <types.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/32828 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I46f60f8631601db1e2e654d638560d640bbcf403 Gerrit-Change-Number: 32828 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: {gm45,pineview,x4x}: Remove redundant use of ACPI offset operator
by HAOUAS Elyes (Code Review) 28 Nov '19

28 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32586 Change subject: {gm45,pineview,x4x}: Remove redundant use of ACPI offset operator ...................................................................... {gm45,pineview,x4x}: Remove redundant use of ACPI offset operator Change-Id: Ie7a9df2275d9e02bc2793064903228c8cac4d17f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/gm45/acpi/hostbridge.asl M src/northbridge/intel/pineview/acpi/hostbridge.asl M src/northbridge/intel/x4x/acpi/hostbridge.asl 3 files changed, 18 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/32586/1 diff --git a/src/northbridge/intel/gm45/acpi/hostbridge.asl b/src/northbridge/intel/gm45/acpi/hostbridge.asl index afa7a61..624ca99 100644 --- a/src/northbridge/intel/gm45/acpi/hostbridge.asl +++ b/src/northbridge/intel/gm45/acpi/hostbridge.asl @@ -56,32 +56,32 @@ , 4, PM0H, 2, , 2, - Offset (0x91), // PAM1 + // PAM1 PM1L, 2, , 2, PM1H, 2, , 2, - Offset (0x92), // PAM2 + // PAM2 PM2L, 2, , 2, PM2H, 2, , 2, - Offset (0x93), // PAM3 + // PAM3 PM3L, 2, , 2, PM3H, 2, , 2, - Offset (0x94), // PAM4 + // PAM4 PM4L, 2, , 2, PM4H, 2, , 2, - Offset (0x95), // PAM5 + // PAM5 PM5L, 2, , 2, PM5H, 2, , 2, - Offset (0x96), // PAM6 + // PAM6 PM6L, 2, , 2, PM6H, 2, diff --git a/src/northbridge/intel/pineview/acpi/hostbridge.asl b/src/northbridge/intel/pineview/acpi/hostbridge.asl index 3eff101..5fe1453 100644 --- a/src/northbridge/intel/pineview/acpi/hostbridge.asl +++ b/src/northbridge/intel/pineview/acpi/hostbridge.asl @@ -56,32 +56,32 @@ , 4, PM0H, 2, , 2, - Offset (0x91), /* PAM1 */ + /* PAM1 */ PM1L, 2, , 2, PM1H, 2, , 2, - Offset (0x92), /* PAM2 */ + /* PAM2 */ PM2L, 2, , 2, PM2H, 2, , 2, - Offset (0x93), /* PAM3 */ + /* PAM3 */ PM3L, 2, , 2, PM3H, 2, , 2, - Offset (0x94), /* PAM4 */ + /* PAM4 */ PM4L, 2, , 2, PM4H, 2, , 2, - Offset (0x95), /* PAM5 */ + /* PAM5 */ PM5L, 2, , 2, PM5H, 2, , 2, - Offset (0x96), /* PAM6 */ + /* PAM6 */ PM6L, 2, , 2, PM6H, 2, diff --git a/src/northbridge/intel/x4x/acpi/hostbridge.asl b/src/northbridge/intel/x4x/acpi/hostbridge.asl index 90f15c7..1e43511 100644 --- a/src/northbridge/intel/x4x/acpi/hostbridge.asl +++ b/src/northbridge/intel/x4x/acpi/hostbridge.asl @@ -57,32 +57,32 @@ , 4, PM0H, 2, , 2, - Offset (0x91), // PAM1 + // PAM1 PM1L, 2, , 2, PM1H, 2, , 2, - Offset (0x92), // PAM2 + // PAM2 PM2L, 2, , 2, PM2H, 2, , 2, - Offset (0x93), // PAM3 + // PAM3 PM3L, 2, , 2, PM3H, 2, , 2, - Offset (0x94), // PAM4 + // PAM4 PM4L, 2, , 2, PM4H, 2, , 2, - Offset (0x95), // PAM5 + // PAM5 PM5L, 2, , 2, PM5H, 2, , 2, - Offset (0x96), // PAM6 + // PAM6 PM6L, 2, , 2, PM6H, 2, -- To view, visit https://review.coreboot.org/c/coreboot/+/32586 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7a9df2275d9e02bc2793064903228c8cac4d17f Gerrit-Change-Number: 32586 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: /mainboard/pcengines/apu2: implement POSTCAR_STAGE
by Krystian Hebel (Code Review) 27 Nov '19

27 Nov '19

Krystian Hebel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32363 Change subject: /mainboard/pcengines/apu2: implement POSTCAR_STAGE ...................................................................... /mainboard/pcengines/apu2: implement POSTCAR_STAGE As in [1], POSTCAR_STAGE will be required since October 2019. [1]https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/HN… Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Change-Id: Iff3dbe68ac17eb2947ff40b9769c6650255656cf --- M src/mainboard/pcengines/apu2/BiosCallOuts.c M src/mainboard/pcengines/apu2/Kconfig M src/mainboard/pcengines/apu2/Makefile.inc M src/mainboard/pcengines/apu2/OemCustomize.c A src/mainboard/pcengines/apu2/postcar.c M src/mainboard/pcengines/apu2/romstage.c A src/mainboard/pcengines/apu2/state_machine.c 7 files changed, 213 insertions(+), 136 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/32363/1 diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index 535024a..0178018 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -16,6 +16,7 @@ #include <AGESA.h> #include <spd_bin.h> #include <northbridge/amd/agesa/BiosCallOuts.h> +#include <northbridge/amd/agesa/state_machine.h> #include <FchPlatform.h> #include <stdlib.h> @@ -23,7 +24,6 @@ #include "imc.h" #include "hudson.h" -static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr); static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr); const BIOS_CALLOUT_STRUCT BiosCallouts[] = @@ -34,8 +34,7 @@ {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, - {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config } + {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess } }; const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); @@ -56,75 +55,66 @@ FchParams->Hwm.HwmFchtsiAutoPoll = FALSE; /* 1 enable, 0 disable TSI Auto Polling */ } -/** - * Fch Oem setting callback - * - * Configure platform specific Hudson device, - * such Azalia, SATA, IMC etc. - */ -static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) +void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams) { - AMD_CONFIG_PARAMS *StdHeader = (AMD_CONFIG_PARAMS *)ConfigPtr; - if (StdHeader->Func == AMD_INIT_RESET) { - FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *) FchData; - printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ - FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); - FchParams->FchReset.SataEnable = hudson_sata_enable(); - FchParams->FchReset.IdeEnable = hudson_ide_enable(); - FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); - FchParams->FchReset.Xhci1Enable = FALSE; - } else if (StdHeader->Func == AMD_INIT_ENV) { - FCH_DATA_BLOCK *FchParams = (FCH_DATA_BLOCK *)FchData; - printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); + printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); + //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + FchParams->LegacyFree = CONFIG(HUDSON_LEGACY_FREE); + FchParams->FchReset.SataEnable = hudson_sata_enable(); + FchParams->FchReset.IdeEnable = hudson_ide_enable(); + FchParams->FchReset.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); + FchParams->FchReset.Xhci1Enable = FALSE; + printk(BIOS_DEBUG, "Done\n"); +} + +void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams) +{ + printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); - FchParams->Azalia.AzaliaEnable = AzDisable; + FchParams->Azalia.AzaliaEnable = AzDisable; - /* Fan Control */ - oem_fan_control(FchParams); + /* Fan Control */ + oem_fan_control(FchParams); - /* XHCI configuration */ - FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); - FchParams->Usb.Xhci1Enable = FALSE; + /* XHCI configuration */ + FchParams->Usb.Xhci0Enable = CONFIG(HUDSON_XHCI_ENABLE); + FchParams->Usb.Xhci1Enable = FALSE; - /* EHCI configuration */ - FchParams->Usb.Ehci3Enable = !CONFIG(HUDSON_XHCI_ENABLE); + /* EHCI configuration */ + FchParams->Usb.Ehci3Enable = !CONFIG(HUDSON_XHCI_ENABLE); - if (CONFIG(BOARD_PCENGINES_APU2)) { - // Disable EHCI 0 (port 0 to 3) - FchParams->Usb.Ehci1Enable = FALSE; - } else { - // Enable EHCI 0 (port 0 to 3) - FchParams->Usb.Ehci1Enable = TRUE; - } + if (CONFIG(BOARD_PCENGINES_APU2)) { + // Disable EHCI 0 (port 0 to 3) + FchParams->Usb.Ehci1Enable = FALSE; + } else { + // Enable EHCI 0 (port 0 to 3) + FchParams->Usb.Ehci1Enable = TRUE; + } - // Enable EHCI 1 (port 4 to 7) - // port 4 and 5 to EHCI header port 6 and 7 to PCIe slot. - FchParams->Usb.Ehci2Enable = TRUE; + // Enable EHCI 1 (port 4 to 7) + // port 4 and 5 to EHCI header port 6 and 7 to PCIe slot. + FchParams->Usb.Ehci2Enable = TRUE; - /* sata configuration */ - FchParams->Sata.SataDevSlpPort0 = 0; // Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP - FchParams->Sata.SataDevSlpPort1 = 0; + /* sata configuration */ + FchParams->Sata.SataDevSlpPort0 = 0; // Disable DEVSLP0 and 1 to make sure GPIO55 and 59 are not used by DEVSLP + FchParams->Sata.SataDevSlpPort1 = 0; - FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE; - switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) { - case SataRaid: - case SataAhci: - case SataAhci7804: - case SataLegacyIde: - FchParams->Sata.SataIdeMode = FALSE; - break; - case SataIde2Ahci: - case SataIde2Ahci7804: - default: /* SataNativeIde */ - FchParams->Sata.SataIdeMode = TRUE; - break; - } + FchParams->Sata.SataClass = CONFIG_HUDSON_SATA_MODE; + switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) { + case SataRaid: + case SataAhci: + case SataAhci7804: + case SataLegacyIde: + FchParams->Sata.SataIdeMode = FALSE; + break; + case SataIde2Ahci: + case SataIde2Ahci7804: + default: /* SataNativeIde */ + FchParams->Sata.SataIdeMode = TRUE; + break; } printk(BIOS_DEBUG, "Done\n"); - - return AGESA_SUCCESS; } static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr) diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 6c3958b..28f9eb8 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -20,7 +20,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select BINARYPI_LEGACY_WRAPPER select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/mainboard/pcengines/apu2/Makefile.inc b/src/mainboard/pcengines/apu2/Makefile.inc index 4e6364e..7824996 100644 --- a/src/mainboard/pcengines/apu2/Makefile.inc +++ b/src/mainboard/pcengines/apu2/Makefile.inc @@ -14,10 +14,14 @@ # GNU General Public License for more details. # +romstage-y += state_machine.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c romstage-y += gpio_ftns.c +postcar-y += postcar.c + +ramstage-y += state_machine.c ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c ramstage-y += gpio_ftns.c diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c index 700f4c7..7ef7e00 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -14,7 +14,7 @@ */ #include <AGESA.h> -#include <northbridge/amd/pi/agesawrapper.h> +#include <northbridge/amd/agesa/state_machine.h> static const PCIe_PORT_DESCRIPTOR PortList[] = { @@ -76,25 +76,7 @@ .DdiLinkList = NULL, }; -/*---------------------------------------------------------------------------------------*/ -/** - * OemCustomizeInitEarly - * - * Description: - * This stub function will call the host environment through the binary block - * interface (call-out port) to provide a user hook opportunity - * - * Parameters: - * @param[in] *InitEarly - * - * @retval VOID - * - **/ -/*---------------------------------------------------------------------------------------*/ -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { InitEarly->GnbConfig.PcieComplexList = &PcieComplex; InitEarly->PlatformConfig.CStateMode = CStateModeC6; diff --git a/src/mainboard/pcengines/apu2/postcar.c b/src/mainboard/pcengines/apu2/postcar.c new file mode 100644 index 0000000..b57ea94 --- /dev/null +++ b/src/mainboard/pcengines/apu2/postcar.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> +#include <arch/io.h> + +void late_car_teardown(void) +{ + /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ + outb(0xEA, 0xCD6); + outb(0x1, 0xcd7); +} diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index bd3c421..a6fe713 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -40,9 +40,11 @@ static void early_lpc_init(void); -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void board_BeforeAgesa(struct sysinfo *cb) { u32 val; + pci_devfn_t dev; + u32 data; /* * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for @@ -57,51 +59,32 @@ hudson_lpc_port80(); - if (!cpu_init_detectedx && boot_cpu()) { - pci_devfn_t dev; - u32 data; + timestamp_init(timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); - timestamp_init(timestamp_get()); - timestamp_add_now(TS_START_ROMSTAGE); + post_code(0x30); + early_lpc_init(); - post_code(0x30); - early_lpc_init(); + hudson_clk_output_48Mhz(); + post_code(0x31); - hudson_clk_output_48Mhz(); - post_code(0x31); + dev = PCI_DEV(0, 0x14, 3); + data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); + /* enable 0x2e/0x4e IO decoding before configuring SuperIO */ + pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); - dev = PCI_DEV(0, 0x14, 3); - data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); - /* enable 0x2e/0x4e IO decoding before configuring SuperIO */ - pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3); + /* COM2 on apu5 is reserved so only COM1 should be supported */ + if ((CONFIG_UART_FOR_CONSOLE == 1) && + !CONFIG(BOARD_PCENGINES_APU5)) + nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE); + else if (CONFIG_UART_FOR_CONSOLE == 0) + nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); - /* COM2 on apu5 is reserved so only COM1 should be supported */ - if ((CONFIG_UART_FOR_CONSOLE == 1) && - !CONFIG(BOARD_PCENGINES_APU5)) - nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE); - else if (CONFIG_UART_FOR_CONSOLE == 0) - nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); - - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); + console_init(); /* Load MPB */ val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - post_code(0x37); - AGESAWRAPPER(amdinitreset); - - post_code(0x38); - printk(BIOS_DEBUG, "Got past avalon_early_setup\n"); - - post_code(0x39); - AGESAWRAPPER(amdinitearly); /* Disable SVI2 controller to wait for command completion */ val = pci_read_config32(PCI_DEV(0, 0x18, 5), 0x12C); @@ -112,27 +95,17 @@ val |= (1 << 30); pci_write_config32(PCI_DEV(0, 0x18, 5), 0x12C, val); } - - timestamp_add_now(TS_BEFORE_INITRAM); - - post_code(0x40); - AGESAWRAPPER(amdinitpost); - - /* FIXME: Detect if TSC frequency changed during raminit? */ - timestamp_rescale_table(1, 4); - - timestamp_add_now(TS_AFTER_INITRAM); } -void agesa_postcar(struct sysinfo *cb) -{ - //PspMboxBiosCmdDramInfo(); - post_code(0x41); - AGESAWRAPPER(amdinitenv); +//~ void agesa_postcar(struct sysinfo *cb) +//~ { + //~ //PspMboxBiosCmdDramInfo(); + //~ post_code(0x41); + //~ AGESAWRAPPER(amdinitenv); - outb(0xEA, 0xCD6); - outb(0x1, 0xcd7); -} + //~ outb(0xEA, 0xCD6); + //~ outb(0x1, 0xcd7); +//~ } static void early_lpc_init(void) { diff --git a/src/mainboard/pcengines/apu2/state_machine.c b/src/mainboard/pcengines/apu2/state_machine.c new file mode 100644 index 0000000..4a10df9 --- /dev/null +++ b/src/mainboard/pcengines/apu2/state_machine.c @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <Porting.h> +#include <AGESA.h> +#include <binaryPI/FieldAccessors.h> + +#include <cbmem.h> +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ +} + +void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop); +} + +void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ + EmptyHeap(); +} + +void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ +} + +void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ + amd_initcpuio(); +} + +void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) +{ + amd_initcpuio(); +} + +void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ +} + +void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) +{ +} + +AGESA_STATUS +AmdGetValue ( + IN CONST AGESA_FIELD_NAME name, + IN OUT VOID** value, + IN UINT32 size + ) +{ + AGESA_STATUS status; + struct sysinfo cb; + AMD_ACCESSOR_PARAMS Params = {}; + + agesa_set_interface(&cb); + Params.StdHeader.ImageBasePtr = cb.StdHeader.ImageBasePtr; + + Params.AllocationMethod = ByHost; + Params.FieldName = name; + Params.FieldValue = *value; + Params.FieldSize = size; + + status = module_dispatch(AMD_GET_VALUE, (AMD_CONFIG_PARAMS*) &Params); + + *value = Params.FieldValue; + size = Params.FieldSize; + + return status; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff3dbe68ac17eb2947ff40b9769c6650255656cf Gerrit-Change-Number: 32363 Gerrit-PatchSet: 1 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newchange

8 21

Change in ...coreboot[master]: nb/amd/pi: support for boards without BINARYPI_LEGACY_WRAPPER
by Krystian Hebel (Code Review) 26 Nov '19

26 Nov '19

Krystian Hebel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32421 Change subject: nb/amd/pi: support for boards without BINARYPI_LEGACY_WRAPPER ...................................................................... nb/amd/pi: support for boards without BINARYPI_LEGACY_WRAPPER A stripped down version (without S3) of ../agesa/family*/state_machine.c is used to provide platform-specific hooks. AmdGetValue() is required by cpu_bus_scan(), it is adapted from binaryPI wrapper to use new interface for dispatcher. Tested only on 00730F01 (apu2) - no other platforms available. Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Change-Id: I700a7d8d3c77ee0525b2c764c720ab5bf39925f8 Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> --- M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/amd/pi/Makefile.inc A src/northbridge/amd/pi/state_machine.c 5 files changed, 164 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/32421/1 diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index eca2f0c..c64a7ba 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2019 3mdeb Embedded Systems Consulting * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -38,6 +39,8 @@ #if CONFIG(BINARYPI_LEGACY_WRAPPER) #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> +#else +#include <northbridge/amd/agesa/state_machine.h> #endif #define MAX_NODE_NUMS MAX_NODES @@ -1006,3 +1009,28 @@ return new_vendev; } + +#if !CONFIG_BINARYPI_LEGACY_WRAPPER +AGESA_STATUS +AmdGetValue(IN CONST AGESA_FIELD_NAME name, IN OUT VOID **value, IN UINT32 size) +{ + AGESA_STATUS status; + struct sysinfo cb; + AMD_ACCESSOR_PARAMS Params = {}; + + agesa_set_interface(&cb); + Params.StdHeader.ImageBasePtr = cb.StdHeader.ImageBasePtr; + + Params.AllocationMethod = ByHost; + Params.FieldName = name; + Params.FieldValue = *value; + Params.FieldSize = size; + + status = module_dispatch(AMD_GET_VALUE, (AMD_CONFIG_PARAMS*) &Params); + + *value = Params.FieldValue; + size = Params.FieldSize; + + return status; +} +#endif diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 43df725..08dfd84 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2019 3mdeb Embedded Systems Consulting * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -38,6 +39,8 @@ #if CONFIG(BINARYPI_LEGACY_WRAPPER) #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> +#else +#include <northbridge/amd/agesa/state_machine.h> #endif #define MAX_NODE_NUMS MAX_NODES @@ -991,3 +994,28 @@ return new_vendev; } + +#if !CONFIG_BINARYPI_LEGACY_WRAPPER +AGESA_STATUS +AmdGetValue(IN CONST AGESA_FIELD_NAME name, IN OUT VOID **value, IN UINT32 size) +{ + AGESA_STATUS status; + struct sysinfo cb; + AMD_ACCESSOR_PARAMS Params = {}; + + agesa_set_interface(&cb); + Params.StdHeader.ImageBasePtr = cb.StdHeader.ImageBasePtr; + + Params.AllocationMethod = ByHost; + Params.FieldName = name; + Params.FieldValue = *value; + Params.FieldSize = size; + + status = module_dispatch(AMD_GET_VALUE, (AMD_CONFIG_PARAMS*) &Params); + + *value = Params.FieldValue; + size = Params.FieldSize; + + return status; +} +#endif diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 926208c..f69f226 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -40,6 +40,8 @@ #if CONFIG(BINARYPI_LEGACY_WRAPPER) #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> +#else +#include <northbridge/amd/agesa/state_machine.h> #endif #define MAX_NODE_NUMS MAX_NODES @@ -1242,3 +1244,28 @@ return new_vendev; } + +#if !CONFIG_BINARYPI_LEGACY_WRAPPER +AGESA_STATUS +AmdGetValue(IN CONST AGESA_FIELD_NAME name, IN OUT VOID **value, IN UINT32 size) +{ + AGESA_STATUS status; + struct sysinfo cb; + AMD_ACCESSOR_PARAMS Params = {}; + + agesa_set_interface(&cb); + Params.StdHeader.ImageBasePtr = cb.StdHeader.ImageBasePtr; + + Params.AllocationMethod = ByHost; + Params.FieldName = name; + Params.FieldValue = *value; + Params.FieldSize = size; + + status = module_dispatch(AMD_GET_VALUE, (AMD_CONFIG_PARAMS*) &Params); + + *value = Params.FieldValue; + size = Params.FieldSize; + + return status; +} +#endif diff --git a/src/northbridge/amd/pi/Makefile.inc b/src/northbridge/amd/pi/Makefile.inc index c2c8d88..349761b 100644 --- a/src/northbridge/amd/pi/Makefile.inc +++ b/src/northbridge/amd/pi/Makefile.inc @@ -22,6 +22,9 @@ ifeq ($(CONFIG_BINARYPI_LEGACY_WRAPPER), y) romstage-y += agesawrapper.c ramstage-y += agesawrapper.c +else +romstage-y += state_machine.c +ramstage-y += state_machine.c endif romstage-y += ramtop.c diff --git a/src/northbridge/amd/pi/state_machine.c b/src/northbridge/amd/pi/state_machine.c new file mode 100644 index 0000000..f42e97f --- /dev/null +++ b/src/northbridge/amd/pi/state_machine.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Kyösti Mälkki + * Copyright (C) 2019 3mdeb Embedded Systems Consulting + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <Porting.h> +#include <AGESA.h> + +#include <cbmem.h> +#include <northbridge/amd/agesa/state_machine.h> +#include <northbridge/amd/agesa/agesa_helper.h> + +void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ +} + +void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) +{ +} + +void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ +} + +void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) +{ + backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop); +} + +void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume) +{ +} + +void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ + EmptyHeap(); +} + +void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) +{ +} + +void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ +} + +void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late) +{ + amd_initcpuio(); +} + +void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid) +{ + amd_initcpuio(); +} + +void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late) +{ +} + +void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save) +{ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32421 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I700a7d8d3c77ee0525b2c764c720ab5bf39925f8 Gerrit-Change-Number: 32421 Gerrit-PatchSet: 1 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-MessageType: newchange

6 24

Change in ...coreboot[master]: mb/lenovo/*: Add MAINBOARD_FAMILY
by Patrick Rudolph (Code Review) 23 Nov '19

23 Nov '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32727 Change subject: mb/lenovo/*: Add MAINBOARD_FAMILY ...................................................................... mb/lenovo/*: Add MAINBOARD_FAMILY The Kconfig MAINBOARD_FAMILY sets the family type of SMBIOS entry 1. Match what vendor firmware does and use the same value as in the version field. Required for fwupd which uses the family field to generate a GUID. Change-Id: I0033c42c5eac6b9d47d0acd16c67467b6d419534 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/lenovo/g505s/Kconfig M src/mainboard/lenovo/l520/Kconfig M src/mainboard/lenovo/s230u/Kconfig M src/mainboard/lenovo/t400/Kconfig M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420s/Kconfig M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430s/Kconfig M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t530/Kconfig M src/mainboard/lenovo/t60/Kconfig M src/mainboard/lenovo/thinkcentre_a58/Kconfig M src/mainboard/lenovo/x131e/Kconfig M src/mainboard/lenovo/x1_carbon_gen1/Kconfig M src/mainboard/lenovo/x200/Kconfig M src/mainboard/lenovo/x220/Kconfig M src/mainboard/lenovo/x230/Kconfig M src/mainboard/lenovo/x60/Kconfig M src/mainboard/lenovo/z61t/Kconfig 19 files changed, 84 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/32727/1 diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index 883ef27..e6dbddd 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -39,6 +39,10 @@ string default "LENOVO G505S" +config MAINBOARD_FAMILY + string + default "LENOVO G505S" + config HW_MEM_HOLE_SIZEK hex default 0x200000 diff --git a/src/mainboard/lenovo/l520/Kconfig b/src/mainboard/lenovo/l520/Kconfig index 4495d79..8066bf3 100644 --- a/src/mainboard/lenovo/l520/Kconfig +++ b/src/mainboard/lenovo/l520/Kconfig @@ -26,6 +26,10 @@ string default "ThinkPad L520" +config MAINBOARD_FAMILY + string + default "ThinkPad L520" + config VGA_BIOS_FILE string default "pci8086,0126.rom" diff --git a/src/mainboard/lenovo/s230u/Kconfig b/src/mainboard/lenovo/s230u/Kconfig index 9200ad5..b388646 100644 --- a/src/mainboard/lenovo/s230u/Kconfig +++ b/src/mainboard/lenovo/s230u/Kconfig @@ -28,6 +28,10 @@ string default "ThinkPad S230U (Twist)" +config MAINBOARD_FAMILY + string + default "ThinkPad S230U (Twist)" + config EC_BASE_ADDRESS hex default 0xff000000 diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 9f94051..db6c98a 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -37,6 +37,13 @@ default "ThinkPad R400" if BOARD_LENOVO_R400 default "ThinkPad W500" if BOARD_LENOVO_W500 +config MAINBOARD_FAMILY + string + default "ThinkPad T400" if BOARD_LENOVO_T400 + default "ThinkPad T500" if BOARD_LENOVO_T500 + default "ThinkPad R400" if BOARD_LENOVO_R400 + default "ThinkPad W500" if BOARD_LENOVO_W500 + config USBDEBUG_HCD_INDEX int default 2 diff --git a/src/mainboard/lenovo/t420/Kconfig b/src/mainboard/lenovo/t420/Kconfig index ce81907..fb4f0ee 100644 --- a/src/mainboard/lenovo/t420/Kconfig +++ b/src/mainboard/lenovo/t420/Kconfig @@ -36,6 +36,10 @@ string default "ThinkPad T420" +config MAINBOARD_FAMILY + string + default "ThinkPad T420" + config MAX_CPUS int default 8 diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index c5efb55..c603753 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -35,6 +35,10 @@ string default "ThinkPad T420s" +config MAINBOARD_FAMILY + string + default "ThinkPad T420s" + config MAX_CPUS int default 8 diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig index dbeaadb..3c2a473 100644 --- a/src/mainboard/lenovo/t430/Kconfig +++ b/src/mainboard/lenovo/t430/Kconfig @@ -34,6 +34,10 @@ string default "ThinkPad T430" +config MAINBOARD_FAMILY + string + default "ThinkPad T430" + config VGA_BIOS_ID string default "8086,0166" diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index bad1837..9f69430 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -40,6 +40,11 @@ default "ThinkPad T430s" if BOARD_LENOVO_T430S default "ThinkPad T431s" if BOARD_LENOVO_T431S +config MAINBOARD_FAMILY + string + default "ThinkPad T430s" if BOARD_LENOVO_T430S + default "ThinkPad T431s" if BOARD_LENOVO_T431S + config OVERRIDE_DEVICETREE string default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 06f296b..62a91a6 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -45,6 +45,11 @@ default "ThinkPad T520" if BOARD_LENOVO_T520 default "ThinkPad W520" if BOARD_LENOVO_W520 +config MAINBOARD_FAMILY + string + default "ThinkPad T520" if BOARD_LENOVO_T520 + default "ThinkPad W520" if BOARD_LENOVO_W520 + config MAX_CPUS int default 8 diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index b36460d..62a3ac8 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -45,6 +45,11 @@ default "ThinkPad T530" if BOARD_LENOVO_T530 default "ThinkPad W530" if BOARD_LENOVO_W530 +config MAINBOARD_FAMILY + string + default "ThinkPad T530" if BOARD_LENOVO_T530 + default "ThinkPad W530" if BOARD_LENOVO_W530 + config MAX_CPUS int default 8 diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index a6a88b3..2ef5ebf 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -33,6 +33,10 @@ string default "ThinkPad T60" +config MAINBOARD_FAMILY + string + default "ThinkPad T60" + config MAX_CPUS int default 2 diff --git a/src/mainboard/lenovo/thinkcentre_a58/Kconfig b/src/mainboard/lenovo/thinkcentre_a58/Kconfig index fc1c6a7..1e31c89 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/Kconfig +++ b/src/mainboard/lenovo/thinkcentre_a58/Kconfig @@ -43,6 +43,10 @@ string default "ThinkCentre A58" +config MAINBOARD_FAMILY + string + default "ThinkCentre A58" + config MAX_CPUS int default 4 diff --git a/src/mainboard/lenovo/x131e/Kconfig b/src/mainboard/lenovo/x131e/Kconfig index e7da8d0..a61c1bd 100644 --- a/src/mainboard/lenovo/x131e/Kconfig +++ b/src/mainboard/lenovo/x131e/Kconfig @@ -29,6 +29,10 @@ string default "ThinkPad X131e" +config MAINBOARD_FAMILY + string + default "ThinkPad X131e" + config MAX_CPUS int default 4 diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig index 520853c..6c84ba6 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig +++ b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig @@ -34,6 +34,10 @@ string default "ThinkPad X1 carbon gen 1" +config MAINBOARD_FAMILY + string + default "ThinkPad X1 Carbon gen 1" + config MAX_CPUS int default 8 diff --git a/src/mainboard/lenovo/x200/Kconfig b/src/mainboard/lenovo/x200/Kconfig index 7b905bc..8b341cc 100644 --- a/src/mainboard/lenovo/x200/Kconfig +++ b/src/mainboard/lenovo/x200/Kconfig @@ -32,6 +32,10 @@ string default "ThinkPad X200" +config MAINBOARD_FAMILY + string + default "ThinkPad X200" + config USBDEBUG_HCD_INDEX int default 2 diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index 16f42e8..1861984 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -35,13 +35,18 @@ default "x220" if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I default "x1" if BOARD_LENOVO_X1 - config MAINBOARD_PART_NUMBER string default "ThinkPad X220" if BOARD_LENOVO_X220 default "ThinkPad X220i" if BOARD_LENOVO_X220I default "ThinkPad X1" if BOARD_LENOVO_X1 +config MAINBOARD_FAMILY + string + default "ThinkPad X220" if BOARD_LENOVO_X220 + default "ThinkPad X220i" if BOARD_LENOVO_X220I + default "ThinkPad X1" if BOARD_LENOVO_X1 + config OVERRIDE_DEVICETREE string default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 5b34b83..2da651e 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -35,6 +35,10 @@ string default "ThinkPad X230" +config MAINBOARD_FAMILY + string + default "ThinkPad X230" + config MAX_CPUS int default 8 diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 6db7f11..6ffe3b6 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -36,6 +36,10 @@ string default "ThinkPad X60" +config MAINBOARD_FAMILY + string + default "ThinkPad X60" + config IRQ_SLOT_COUNT int default 18 diff --git a/src/mainboard/lenovo/z61t/Kconfig b/src/mainboard/lenovo/z61t/Kconfig index a223077..f0a20fd 100644 --- a/src/mainboard/lenovo/z61t/Kconfig +++ b/src/mainboard/lenovo/z61t/Kconfig @@ -33,6 +33,10 @@ string default "ThinkPad Z61t" +config MAINBOARD_FAMILY + string + default "ThinkPad Z61t" + config MAX_CPUS int default 2 -- To view, visit https://review.coreboot.org/c/coreboot/+/32727 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0033c42c5eac6b9d47d0acd16c67467b6d419534 Gerrit-Change-Number: 32727 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 7

Change in ...coreboot[master]: nb/intel/sandybridge: Fill common MRC settings in northbridge code
by Patrick Rudolph (Code Review) 23 Nov '19

23 Nov '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32069 Change subject: nb/intel/sandybridge: Fill common MRC settings in northbridge code ...................................................................... nb/intel/sandybridge: Fill common MRC settings in northbridge code Fill northbridge and southbridge BARs in raminit code. Allows to drop duplicated code from mainboard directories. Change-Id: Ic6d9f0fd6a2b792ac693d6016ed9ce44945c900c Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/raminit_mrc.c 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/32069/1 diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 852da7a..c544a74 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -275,6 +275,24 @@ u32 reserved[4]; } __packed; +static void northbridge_fill_pei_data(struct pei_data *pei_data) +{ + pei_data->mchbar = (uintptr_t)DEFAULT_MCHBAR; + pei_data->dmibar = (uintptr_t)DEFAULT_DMIBAR; + pei_data->epbar = DEFAULT_EPBAR; + pei_data->pciexbar = CONFIG_MMCONF_BASE_ADDRESS; + pei_data->smbusbar = SMBUS_IO_BASE; + pei_data->wdbbar = 0x4000000; + pei_data->wdbsize = 0x1000; + pei_data->hpet_address = CONFIG_HPET_ADDRESS; + pei_data->rcba = (uintptr_t)DEFAULT_RCBABASE; + pei_data->pmbase = DEFAULT_PMBASE; + pei_data->gpiobase = DEFAULT_GPIOBASE; + pei_data->thermalbase = 0xfed08000; + pei_data->system_type = get_platform_type() == PLATFORM_MOBILE ? 0 : 1; + pei_data->tseg_size = CONFIG_SMM_TSEG_SIZE; +} + void perform_raminit(int s3resume) { int cbmem_was_initted; @@ -286,6 +304,7 @@ enable_usb_bar(); mainboard_fill_pei_data(&pei_data); + northbridge_fill_pei_data(&pei_data); post_code(0x3a); pei_data.boot_mode = s3resume ? 2 : 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/32069 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6d9f0fd6a2b792ac693d6016ed9ce44945c900c Gerrit-Change-Number: 32069 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 14

Change in ...coreboot[master]: {apple/macbook21,lenovo/{t60,z61t}}: Remove 2nd write to RCBA32(V0CTL)
by HAOUAS Elyes (Code Review) 21 Nov '19

21 Nov '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32915 Change subject: {apple/macbook21,lenovo/{t60,z61t}}: Remove 2nd write to RCBA32(V0CTL) ...................................................................... {apple/macbook21,lenovo/{t60,z61t}}: Remove 2nd write to RCBA32(V0CTL) i945/early_init.c already set to 'RCBA32(V0CTL) = 0x80000001' Change-Id: I7d4d4de3f596b9ce8f1f9ea8cc9cc1910af8bed3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/z61t/romstage.c 3 files changed, 0 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/32915/1 diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 1c84c84..9ab4af1 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -140,9 +140,6 @@ static void rcba_config(void) { - /* V0CTL Virtual Channel 0 Resource Control */ - RCBA32(0x0014) = 0x80000001; - /* Device 1f interrupt pin register */ RCBA32(0x3100) = 0x00042210; RCBA32(0x3108) = 0x10004321; diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 0c7c0cf..8c0b3e4 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -74,9 +74,6 @@ static void rcba_config(void) { - /* Set up virtual channel 0 */ - RCBA32(V0CTL) = 0x80000001; - /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00001230; RCBA32(D29IP) = 0x40004321; diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 502eac3..2404fb7 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -74,9 +74,6 @@ static void rcba_config(void) { - /* Set up virtual channel 0 */ - RCBA32(V0CTL) = 0x80000001; - /* Device 1f interrupt pin register */ RCBA32(D31IP) = 0x00001230; RCBA32(D29IP) = 0x40004321; -- To view, visit https://review.coreboot.org/c/coreboot/+/32915 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d4d4de3f596b9ce8f1f9ea8cc9cc1910af8bed3 Gerrit-Change-Number: 32915 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 4

Change in ...coreboot[master]: build system: Add various compiler flags that enable warnings on UB
by Patrick Georgi (Code Review) 18 Nov '19

18 Nov '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32814 Change subject: build system: Add various compiler flags that enable warnings on UB ...................................................................... build system: Add various compiler flags that enable warnings on UB Some types of Undefined Behavior can be determined statically at compile time and gcc now has a set of flags that make it emit warnings in that case instead of doing the __builtin_trap() / optimize / UD2-opcode dance that silently breaks the resulting binary. Change-Id: I3aa5ca00c9838cc7517160069310a1ef85372027 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M Makefile.inc 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/32814/1 diff --git a/Makefile.inc b/Makefile.inc index 9860da1..f2e010c 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -410,6 +410,8 @@ ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),) CFLAGS_common += -Wno-packed-not-aligned CFLAGS_common += -fconserve-stack +CFLAGS_common += -pedantic-errors -Wnull-dereference +CFLAGS_common += -Wno-aggressive-loop-optimizations -Wreturn-type # cf. commit f69a99db (coreboot: x86: enable gc-sections) CFLAGS_common += -Wno-unused-but-set-variable endif -- To view, visit https://review.coreboot.org/c/coreboot/+/32814 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3aa5ca00c9838cc7517160069310a1ef85372027 Gerrit-Change-Number: 32814 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 6

Change in ...coreboot[master]: [TOTEST]soc/intel/baytrail: Implement C_ENVIRONMENT_BOOTBLOCK
by Arthur Heymans (Code Review) 17 Nov '19

17 Nov '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32970 Change subject: [TOTEST]soc/intel/baytrail: Implement C_ENVIRONMENT_BOOTBLOCK ...................................................................... [TOTEST]soc/intel/baytrail: Implement C_ENVIRONMENT_BOOTBLOCK untested. Change-Id: I81cc5904d88d8aea523163d16644b228f53575d7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/Makefile.inc A src/soc/intel/baytrail/bootblock/Makefile.inc M src/soc/intel/baytrail/bootblock/bootblock.c R src/soc/intel/baytrail/bootblock/uart.c A src/soc/intel/baytrail/include/soc/bootblock.h M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/pmutil.c M src/soc/intel/baytrail/romstage/Makefile.inc M src/soc/intel/baytrail/romstage/pmc.c M src/soc/intel/baytrail/romstage/romstage.c 11 files changed, 118 insertions(+), 101 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/32970/1 diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 03ad31d..f71fc02 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -41,14 +41,12 @@ select POSTCAR_CONSOLE select CPU_INTEL_COMMON select CPU_HAS_L2_ENABLE_MSR + select C_ENVIRONMENT_BOOTBLOCK config VBOOT select VBOOT_MUST_REQUEST_DISPLAY - select VBOOT_STARTS_IN_ROMSTAGE - -config BOOTBLOCK_CPU_INIT - string - default "soc/intel/baytrail/bootblock/bootblock.c" + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE config MMCONF_BASE_ADDRESS hex @@ -94,6 +92,13 @@ bool "Enable MRC RMT training + debug prints" default n +# The UEFI System Agent binary needs to be at a fixed offset in the flash +# and can therefore only reside in the COREBOOT fmap region +config RO_REGION_ONLY + string + depends on VBOOT + default "mrc.bin" + # Cache As RAM region layout: # # +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE + DCACHE_RAM_MRC_VAR_SIZE @@ -132,6 +137,13 @@ help The amount of cache-as-ram region required by the reference code. +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + config RESET_ON_INVALID_RAMSTAGE_CACHE bool "Reset the system on S3 wake when ramstage cache invalid." default n diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 6e6eb9c..e6a5704 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -1,6 +1,7 @@ ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y) subdirs-y += romstage +subdirs-y += bootblock subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm @@ -12,13 +13,16 @@ ramstage-y += memmap.c romstage-y += memmap.c postcar-y += memmap.c +bootblock-y += tsc_freq.c ramstage-y += tsc_freq.c romstage-y += tsc_freq.c postcar-y += tsc_freq.c smm-y += tsc_freq.c +verstage-y += tsc_freq.c romstage-y += spi.c postcar-y += spi.c ramstage-y += spi.c +verstage-y += spi.c smm-y += spi.c ramstage-y += chip.c ramstage-y += gfx.c @@ -30,6 +34,8 @@ ramstage-y += ramstage.c ramstage-y += gpio.c ramstage-y += cpu.c +bootblock-y += pmutil.c +verstage-y += pmutil.c romstage-y += pmutil.c ramstage-y += pmutil.c smm-y += pmutil.c diff --git a/src/soc/intel/baytrail/bootblock/Makefile.inc b/src/soc/intel/baytrail/bootblock/Makefile.inc new file mode 100644 index 0000000..d093550 --- /dev/null +++ b/src/soc/intel/baytrail/bootblock/Makefile.inc @@ -0,0 +1,5 @@ +bootblock-y += ../../../../cpu/intel/car/bootblock.c +bootblock-y += ../../../../cpu/intel/car/non-evict/cache_as_ram.S +bootblock-y += ../../../../cpu/x86/early_reset.S +bootblock-y += bootblock.c +bootblock-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index b2cdf9d..d371a98 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -18,32 +18,56 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <soc/iosf.h> -#include <cpu/intel/microcode/microcode.c> +#include <soc/iomap.h> +#include <soc/lpc.h> +#include <soc/spi.h> +#include <soc/pmc.h> +#include <soc/bootblock.h> +#include <cpu/intel/car/bootblock.h> -static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) +static void program_base_addresses(void) { - msr_t basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); + uint32_t reg; + const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); + + /* Memory Mapped IO registers. */ + reg = PMC_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, PBASE, reg); + reg = IO_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, IOBASE, reg); + reg = ILB_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, IBASE, reg); + reg = SPI_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, SBASE, reg); + reg = MPHY_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, MPBASE, reg); + reg = PUNIT_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, PUBASE, reg); + reg = RCBA_BASE_ADDRESS | 1; + pci_write_config32(lpc_dev, RCBA, reg); + + /* IO Port Registers. */ + reg = ACPI_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, ABASE, reg); + reg = GPIO_BASE_ADDRESS | 2; + pci_write_config32(lpc_dev, GBASE, reg); } -static void enable_rom_caching(void) +static void spi_init(void) { - msr_t msr; + u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS); + u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); + uint32_t reg; - disable_cache(); - /* Why only top 4MiB ? */ - set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT); - enable_cache(); - - /* Enable Variable MTRRs */ - msr.hi = 0x00000000; - msr.lo = 0x00000800; - wrmsr(MTRR_DEF_TYPE_MSR, msr); + /* Disable generating SMI when setting WPD bit. */ + write32(scs, read32(scs) & ~SMIWPEN); + /* + * Enable caching and prefetching in the SPI controller. Disable + * the SMM-only BIOS write and set WPD bit. + */ + reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD; + reg &= ~EISS; + write32(bcr, reg); } static void setup_mmconfig(void) @@ -64,12 +88,22 @@ pci_io_write_config32(IOSF_PCI_DEV, MCR_REG, reg); } -static void bootblock_cpu_init(void) +static void tco_disable(void) +{ + uint32_t reg; + + reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); + reg |= TCO_TMR_HALT; + outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); +} + +void bootblock_early_cpu_init(void) { /* Allow memory-mapped PCI config access. */ setup_mmconfig(); - /* Load microcode before any caching. */ - intel_update_microcode_from_cbfs(); - enable_rom_caching(); + program_base_addresses(); + tco_disable(); + byt_config_com1_and_enable(); + spi_init(); } diff --git a/src/soc/intel/baytrail/romstage/uart.c b/src/soc/intel/baytrail/bootblock/uart.c similarity index 96% rename from src/soc/intel/baytrail/romstage/uart.c rename to src/soc/intel/baytrail/bootblock/uart.c index f9f2fe4..e5788cb 100644 --- a/src/soc/intel/baytrail/romstage/uart.c +++ b/src/soc/intel/baytrail/bootblock/uart.c @@ -18,7 +18,7 @@ #include <soc/iomap.h> #include <soc/lpc.h> #include <soc/pci_devs.h> -#include <soc/romstage.h> +#include <soc/bootblock.h> void byt_config_com1_and_enable(void) { diff --git a/src/soc/intel/baytrail/include/soc/bootblock.h b/src/soc/intel/baytrail/include/soc/bootblock.h new file mode 100644 index 0000000..65ba6bb --- /dev/null +++ b/src/soc/intel/baytrail/include/soc/bootblock.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _BAYTRAIL_BOOTBLOCK_H_ +#define _BAYTRAIL_BOOTBLOCK_H_ + +#if CONFIG(ENABLE_BUILTIN_COM1) +void byt_config_com1_and_enable(void); +#else +static inline void byt_config_com1_and_enable(void) { } +#endif + + +#endif /* _BAYTRAIL_BOOTBLOCK_H_ */ diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index 7730893..248112f 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -27,15 +27,8 @@ void mainboard_pre_raminit(struct mrc_params *mrc_params); void raminit(struct mrc_params *mp, int prev_sleep_state); void gfx_init(void); -void tco_disable(void); void punit_init(void); void set_max_freq(void); int early_spi_read_wpsr(u8 *sr); -#if CONFIG(ENABLE_BUILTIN_COM1) -void byt_config_com1_and_enable(void); -#else -static inline void byt_config_com1_and_enable(void) { } -#endif - #endif /* _BAYTRAIL_ROMSTAGE_H_ */ diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index b740a03..1fa22f6 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -369,7 +369,12 @@ { uint32_t gen_pmcon1; int rtc_fail; + +#if !(ENV_BOOTBLOCK || ENV_VERSTAGE) struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); +#else + struct chipset_power_state *ps = NULL; +#endif if (ps != NULL) gen_pmcon1 = ps->gen_pmcon1; diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc index 8f009bd..afab9c0 100644 --- a/src/soc/intel/baytrail/romstage/Makefile.inc +++ b/src/soc/intel/baytrail/romstage/Makefile.inc @@ -1,9 +1,7 @@ -cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S cpu_incs-y += $(obj)/fmap_config.h romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += raminit.c -romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c romstage-y += gfx.c romstage-y += pmc.c romstage-y += early_spi.c diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c index 596ed11..9fc3538 100644 --- a/src/soc/intel/baytrail/romstage/pmc.c +++ b/src/soc/intel/baytrail/romstage/pmc.c @@ -27,15 +27,6 @@ #include <soc/romstage.h> #include "../chip.h" -void tco_disable(void) -{ - uint32_t reg; - - reg = inl(ACPI_BASE_ADDRESS + TCO1_CNT); - reg |= TCO_TMR_HALT; - outl(reg, ACPI_BASE_ADDRESS + TCO1_CNT); -} - /* This sequence signals the PUNIT to start running. */ void punit_init(void) { diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 2a530b4..a9b6566 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -50,51 +50,6 @@ * Because we can't use global variables the stack is used for allocations -- * thus the need to call back and forth. */ -static void program_base_addresses(void) -{ - uint32_t reg; - const uint32_t lpc_dev = PCI_DEV(0, LPC_DEV, LPC_FUNC); - - /* Memory Mapped IO registers. */ - reg = PMC_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, PBASE, reg); - reg = IO_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, IOBASE, reg); - reg = ILB_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, IBASE, reg); - reg = SPI_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, SBASE, reg); - reg = MPHY_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, MPBASE, reg); - reg = PUNIT_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, PUBASE, reg); - reg = RCBA_BASE_ADDRESS | 1; - pci_write_config32(lpc_dev, RCBA, reg); - - /* IO Port Registers. */ - reg = ACPI_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, ABASE, reg); - reg = GPIO_BASE_ADDRESS | 2; - pci_write_config32(lpc_dev, GBASE, reg); -} - -static void spi_init(void) -{ - u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS); - u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR); - uint32_t reg; - - /* Disable generating SMI when setting WPD bit. */ - write32(scs, read32(scs) & ~SMIWPEN); - /* - * Enable caching and prefetching in the SPI controller. Disable - * the SMM-only BIOS write and set WPD bit. - */ - reg = (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH | BCR_WPD; - reg &= ~EISS; - write32(bcr, reg); -} - static struct chipset_power_state power_state; static void migrate_power_state(int is_recovery) @@ -171,16 +126,8 @@ struct chipset_power_state *ps; int prev_sleep_state; - program_base_addresses(); - - tco_disable(); - - byt_config_com1_and_enable(); - console_init(); - spi_init(); - set_max_freq(); punit_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/32970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81cc5904d88d8aea523163d16644b228f53575d7 Gerrit-Change-Number: 32970 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP] soc/amd/common: Use static allocation for params
by Kyösti Mälkki (Code Review) 15 Nov '19

15 Nov '19

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31489 Change subject: [WIP] soc/amd/common: Use static allocation for params ...................................................................... [WIP] soc/amd/common: Use static allocation for params Lifetime of the structure is the duration of call to AGESA. There is no need to allocate and release these from AGESA's internal heap for every single call. Change-Id: Ibef6ca8481f926d4e18e1aef5136e69f5834feb1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/soc/amd/common/block/pi/agesawrapper.c 1 file changed, 22 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/31489/1 diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 821535d..e769a45 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -410,6 +410,26 @@ } +union AMD_MAX_ALLOC_PARAMS { + AMD_INTERFACE_PARAMS p1; + AMD_RESET_PARAMS p2; + AMD_EARLY_PARAMS p3; + AMD_POST_PARAMS p4; + AMD_RESUME_PARAMS p5; + AMD_ENV_PARAMS p6; + AMD_MID_PARAMS p7; + AMD_LATE_PARAMS p8; +#if 1 + AMD_RTB_PARAMS p9; +#else + AMD_S3SAVE_PARAMS p10; +#endif + AMD_S3LATE_PARAMS p11; + AMD_S3FINAL_PARAMS p12; +}; + +static union AMD_MAX_ALLOC_PARAMS sp; + AGESA_STATUS agesa_execute_state(AGESA_STRUCT_NAME func) { AGESA_STATUS status = AGESA_UNSUPPORTED; @@ -417,19 +437,9 @@ AMD_CONFIG_PARAMS *StdHeader = &template; AMD_INTERFACE_PARAMS AmdParamStruct; AMD_INTERFACE_PARAMS *aip = &AmdParamStruct; - union { - AMD_RESET_PARAMS ResetParams; - AMD_S3LATE_PARAMS S3LateParams; - AMD_S3FINAL_PARAMS S3FinalParams; - } sp; - if ((func == AMD_INIT_RESET) || (func == AMD_S3LATE_RESTORE) || - (func == AMD_S3FINAL_RESTORE)) { - memset(&sp, 0, sizeof(sp)); - amd_create_struct(aip, func, &sp, sizeof(sp)); - } else { - amd_create_struct(aip, func, NULL, 0); - } + memset(&sp, 0, sizeof(sp)); + amd_create_struct(aip, func, &sp, sizeof(sp)); StdHeader = aip->NewStructPtr; StdHeader->Func = func; -- To view, visit https://review.coreboot.org/c/coreboot/+/31489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibef6ca8481f926d4e18e1aef5136e69f5834feb1 Gerrit-Change-Number: 31489 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newchange

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