Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30806
Change subject: x86/acpi_s3: Remove trailing dots from debug message
......................................................................
x86/acpi_s3: Remove trailing dots from debug message
The dot is not needed, as it is no sentence and followed by a line
break.
Change-Id: I3905853eb7039f9c6d2486a77da47a4460276624
Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de>
---
M src/arch/x86/acpi_s3.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/30806/1
diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c
index ad9fe00..07c0332 100644
--- a/src/arch/x86/acpi_s3.c
+++ b/src/arch/x86/acpi_s3.c
@@ -34,10 +34,10 @@
{
if (acpi_slp_type < 0) {
if (romstage_handoff_is_resume()) {
- printk(BIOS_DEBUG, "S3 Resume.\n");
+ printk(BIOS_DEBUG, "S3 Resume\n");
acpi_slp_type = ACPI_S3;
} else {
- printk(BIOS_DEBUG, "Normal boot.\n");
+ printk(BIOS_DEBUG, "Normal boot\n");
acpi_slp_type = ACPI_S0;
}
}
--
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Gerrit-Change-Id: I3905853eb7039f9c6d2486a77da47a4460276624
Gerrit-Change-Number: 30806
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Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net>
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Nicola Corna has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31470
Change subject: mb/lenovo/x1_carbon_gen1: Swap Fn-F2 and Fn-F3
......................................................................
mb/lenovo/x1_carbon_gen1: Swap Fn-F2 and Fn-F3
thinkpad_acpi expects the battery hotkey (KEY_BATTERY) on scancode 0x01
(Fn-F2) and the lock hotkey (KEY_COFFEE) on scancode 0x02 (Fn-F3).
This is true for most of the Thinkpads, however on the X1 Carbon Gen1
(and possibly others), the battery hotkey is not present and the lock
one is instead on Fn-F3.
Swap the RHK calls in _Q11 (Fn-F2) and _Q12 (Fn-F3) to fix the issue, so
that the lock hotkey is on F3 and the battery one is on F2 (even if it's
not marked so).
Change-Id: Ib2d96be1a7815d7d03e6e8c6d300fd671c8598ca
Signed-off-by: Nicola Corna <nicola(a)corna.info>
---
M src/ec/lenovo/h8/acpi/ec.asl
M src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl
2 files changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/31470/1
diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl
index 327a2cf..6ffba5e 100644
--- a/src/ec/lenovo/h8/acpi/ec.asl
+++ b/src/ec/lenovo/h8/acpi/ec.asl
@@ -197,12 +197,20 @@
Method (_Q11, 0, NotSerialized)
{
+#if IS_ENABLED(EC_LENOVO_H8_SWAP_FNF2_FNF3)
+ ^HKEY.RHK (0x03)
+#else
^HKEY.RHK (0x02)
+#endif
}
Method (_Q12, 0, NotSerialized)
{
+#if IS_ENABLED(EC_LENOVO_H8_SWAP_FNF2_FNF3)
+ ^HKEY.RHK (0x02)
+#else
^HKEY.RHK (0x03)
+#endif
}
Method (_Q64, 0, NotSerialized)
diff --git a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl
index 8c9bd5a..2696607 100644
--- a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl
+++ b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl
@@ -20,6 +20,7 @@
#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
#define EC_LENOVO_H8_ME_WORKAROUND 1
+#define EC_LENOVO_H8_SWAP_FNF2_FNF3 1
#include <arch/acpi.h>
DefinitionBlock(
--
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Gerrit-Change-Id: Ib2d96be1a7815d7d03e6e8c6d300fd671c8598ca
Gerrit-Change-Number: 31470
Gerrit-PatchSet: 1
Gerrit-Owner: Nicola Corna <nicola(a)corna.info>
Gerrit-MessageType: newchange
Evgeny Zinoviev has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33045
Change subject: mb/apple/macbookair4_2: Add CMOS support
......................................................................
mb/apple/macbookair4_2: Add CMOS support
Added CMOS support for MacBook Air 4,2. In future, I hope there will
be more useful options available, because I'm working on macbooks
support.
Also, it may be necessary for hyper_threading support (#29669) once it
will be ready.
Change-Id: I369ed9aeff2098a4840918531be6a34cfc8d2a1e
Signed-off-by: Evgeny Zinoviev <me(a)ch1p.io>
---
M src/mainboard/apple/macbookair4_2/Kconfig
A src/mainboard/apple/macbookair4_2/cmos.default
A src/mainboard/apple/macbookair4_2/cmos.layout
3 files changed, 100 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/33045/1
diff --git a/src/mainboard/apple/macbookair4_2/Kconfig b/src/mainboard/apple/macbookair4_2/Kconfig
index 4b2ee8f..263d550 100644
--- a/src/mainboard/apple/macbookair4_2/Kconfig
+++ b/src/mainboard/apple/macbookair4_2/Kconfig
@@ -14,6 +14,8 @@
select SYSTEM_TYPE_LAPTOP
select GFX_GMA_INTERNAL_IS_EDP
select MAINBOARD_HAS_LIBGFXINIT
+ select HAVE_CMOS_DEFAULT
+ select HAVE_OPTION_TABLE
config MAINBOARD_DIR
string
diff --git a/src/mainboard/apple/macbookair4_2/cmos.default b/src/mainboard/apple/macbookair4_2/cmos.default
new file mode 100644
index 0000000..53e85a3
--- /dev/null
+++ b/src/mainboard/apple/macbookair4_2/cmos.default
@@ -0,0 +1 @@
+debug_level=Debug
diff --git a/src/mainboard/apple/macbookair4_2/cmos.layout b/src/mainboard/apple/macbookair4_2/cmos.layout
new file mode 100644
index 0000000..86d55b4
--- /dev/null
+++ b/src/mainboard/apple/macbookair4_2/cmos.layout
@@ -0,0 +1,97 @@
+##
+## This file is part of the coreboot project.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+# -----------------------------------------------------------------
+entries
+# -----------------------------------------------------------------
+# Status Register A
+# -----------------------------------------------------------------
+# Status Register B
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+#390 2 r 0 unused?
+# -----------------------------------------------------------------
+# coreboot config options: console
+#392 3 r 0 unused
+395 4 e 6 debug_level
+#399 1 r 0 unused
+#400 8 r 0 reserved for century byte
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+# coreboot config options: EC
+#411 1 e 8 first_battery
+#412 1 e 1 bluetooth
+#413 1 e 1 wwan
+#414 1 e 1 touchpad
+#415 1 e 1 wlan
+#416 1 e 1 trackpoint
+#417 1 e 1 fn_ctrl_swap
+#418 1 e 1 sticky_fn
+#419 2 e 13 usb_always_on
+#421 1 e 9 sata_mode
+#422 2 e 10 backlight
+# coreboot config options: cpu
+#424 8 r 0 unused
+# coreboot config options: northbridge
+#432 5 e 11 gfx_uma_size
+#437 3 r 0 unused
+#440 8 h 0 volume
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+960 16 r 0 mrc_scrambler_seed_chk
+# coreboot config options: check sums
+984 16 h 0 check_sum
+# -----------------------------------------------------------------
+enumerations
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+# -----------------------------------------------------------------
+checksums
+checksum 392 447 984
--
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Gerrit-Change-Id: I369ed9aeff2098a4840918531be6a34cfc8d2a1e
Gerrit-Change-Number: 33045
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Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32414
Change subject: arch/x86: Add option for running Romstage out of RAM
......................................................................
arch/x86: Add option for running Romstage out of RAM
AMD's Picasso SOC brings up memory before releasing the X86 processor,
and jumps directly to Romstage. Add a global config option to handle
that.
TEST=None
BUG=b:130804851
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Change-Id: I678b1f74546ea30abcc655a0daed795d6cfa0034
---
M src/Kconfig
M src/arch/x86/assembly_entry.S
M src/arch/x86/memlayout.ld
3 files changed, 25 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/32414/1
diff --git a/src/Kconfig b/src/Kconfig
index 62b3818..bfa0b51 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -146,6 +146,16 @@
time spent decompressing. Doesn't work for XIP stages (assume all
ARCH_X86 for now) for obvious reasons.
+config ROMSTAGE_IN_RAM
+ bool
+ depends on ARCH_X86
+ help
+ Some newer x86 processors come alive with memory enabled, and the
+ reset vector's physical address falling within DRAM. Select this
+ item to build romstage to execute in DRAM instead of XIP. Because
+ this is not a standard, the soc/ or cpu/ code must handle the reset
+ natively before jumping into the standard romstage code.
+
config COMPRESS_BOOTBLOCK
bool
help
diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S
index 4ead9ea..01c0865 100644
--- a/src/arch/x86/assembly_entry.S
+++ b/src/arch/x86/assembly_entry.S
@@ -26,6 +26,16 @@
* variables that are stage specific.
*/
.section ".text._start", "ax", @progbits
+#if ENV_ROMSTAGE && IS_ENABLED(CONFIG_ROMSTAGE_IN_RAM)
+/*
+ * Systems that run romstage in DRAM, i.e. where romstage is the first
+ * executed code, are responsible for getting the processor into protected
+ * mode, setting the stack pointer, and jumping to this location.
+ */
+.global _romstage_in_ram_continue
+_romstage_in_ram_continue:
+
+#else
.global _start
_start:
@@ -34,6 +44,7 @@
/* reset stack pointer to CAR stack */
mov $_car_stack_end, %esp
+#endif
/* clear CAR_GLOBAL area as it is not shared */
cld
diff --git a/src/arch/x86/memlayout.ld b/src/arch/x86/memlayout.ld
index cc72552..da63b05 100644
--- a/src/arch/x86/memlayout.ld
+++ b/src/arch/x86/memlayout.ld
@@ -57,6 +57,10 @@
#endif
}
+#if ENV_ROMSTAGE && CONFIG(ROMSTAGE_IN_RAM)
+#include <soc/romstage.ld>
+#endif
+
#if ENV_BOOTBLOCK
/* Bootblock specific scripts which provide more SECTION directives. */
#include <cpu/x86/16bit/entry16.ld>
--
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Gerrit-Change-Id: I678b1f74546ea30abcc655a0daed795d6cfa0034
Gerrit-Change-Number: 32414
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Gerrit-Owner: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
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Hello Mike Banon,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/31450
to review the following change.
Change subject: lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop
......................................................................
lenovo/g505s: Add the discrete VGA support for AMD Lenovo G505S laptop
Make it possible to enable CONFIG_MULTIPLE_VGA_ADAPTERS option for G505S
which is currently not used by any of coreboot-supported boards. Also
enable the discrete graphics PCI bus leading to HD 8570M (1002,6663)
or R5 M230 (1002,6665) discrete VGA and add the G505S-specific workaround
for PCI resource allocation problems to AMD AGESA vendorcode.
Based on the original patches by Hans Jürgen Kitter <eforname(a)freemail.hu>.
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
Signed-off-by: Hans Jürgen Kitter <eforname(a)freemail.hu>
Change-Id: I98793fa3b1ad8ee7d0b7962a328f7d5c1b0c2f88
---
M src/device/Kconfig
M src/mainboard/lenovo/g505s/devicetree.cb
M src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c
3 files changed, 17 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/31450/1
diff --git a/src/device/Kconfig b/src/device/Kconfig
index 33c1e5b3..5d2087e 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -247,8 +247,15 @@
Enable this option for a good compromise between security and speed.
config MULTIPLE_VGA_ADAPTERS
+ prompt "Multiple VGA Adapters"
bool
+ depends on BOARD_LENOVO_G505S
default n
+ help
+ Some motherboards may have more than one VGA adapter - for example,
+ there are versions of Lenovo G505S that have a discrete VGA adapter
+ in addition to its' integrated VGA adapter which is a part of APU.
+ Enable this option to try to initialize this discrete VGA adapter.
menu "Display"
depends on HAVE_VGA_TEXT_FRAMEBUFFER || HAVE_LINEAR_FRAMEBUFFER
diff --git a/src/mainboard/lenovo/g505s/devicetree.cb b/src/mainboard/lenovo/g505s/devicetree.cb
index 99f42d6..1f33c27 100644
--- a/src/mainboard/lenovo/g505s/devicetree.cb
+++ b/src/mainboard/lenovo/g505s/devicetree.cb
@@ -27,7 +27,7 @@
device pci 0.2 on end # IOMMU
device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX
device pci 1.1 on end # Internal Multimedia
- device pci 2.0 off end
+ device pci 2.0 on end # Discrete Graphics PCI bus 0x666X
device pci 3.0 off end
device pci 4.0 on end # PCIE MINI0
device pci 5.0 on end # PCIE MINI1
diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c
index c566061..ee6d2c2 100644
--- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c
+++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c
@@ -437,8 +437,15 @@
RefPtr = MemPtr->ParameterListPtr;
// Memory Map/Mgt.
- // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
- RefPtr->BottomIo = 0xE0;
+ if ((IS_ENABLED(CONFIG_BOARD_LENOVO_G505S)) &&
+ (IS_ENABLED(CONFIG_MULTIPLE_VGA_ADAPTERS))) {
+ // Set to 0xD0 instead of 0xE0 to avoid the PCI resource allocation problems
+ RefPtr->BottomIo = 0xD0;
+ }
+ else {
+ // Mask Bottom IO with 0xF8 to force hole size to have granularity of 128MB
+ RefPtr->BottomIo = 0xE0;
+ }
RefPtr->UmaMode = UserOptions.CfgUmaMode;
RefPtr->UmaSize = UserOptions.CfgUmaSize;
RefPtr->MemHoleRemapping = TRUE;
--
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Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com>
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