coreboot-gerrit May 2019

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Change in ...coreboot[master]: TEMP: NOT FOR REVIEW: google/mistral: Support dev physical button
by SANTHOSH JANARDHANA HASSAN (Code Review) 11 Mar '20

11 Mar '20

SANTHOSH JANARDHANA HASSAN has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31826 Change subject: TEMP: NOT FOR REVIEW: google/mistral: Support dev physical button ...................................................................... TEMP: NOT FOR REVIEW: google/mistral: Support dev physical button Change-Id: Id0093dec38720bb54c7b0f35db42bd851ab875ba Signed-off-by: Santhosh Hassan <sahassan(a)google.com> --- M src/mainboard/google/mistral/board.h M src/mainboard/google/mistral/chromeos.c 2 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/31826/1 diff --git a/src/mainboard/google/mistral/board.h b/src/mainboard/google/mistral/board.h index 2e23ce3..51e4bf2 100644 --- a/src/mainboard/google/mistral/board.h +++ b/src/mainboard/google/mistral/board.h @@ -19,7 +19,7 @@ #include <gpio.h> #include <soc/gpio.h> - +#define GPIO_DEV_STATE GPIO(45) #define GPIO_H1_AP_INT GPIO(53) #define GPIO_WP_STATE GPIO(54) #define GPIO_REC_STATE GPIO(77) diff --git a/src/mainboard/google/mistral/chromeos.c b/src/mainboard/google/mistral/chromeos.c index 838691b..9b69a4f 100644 --- a/src/mainboard/google/mistral/chromeos.c +++ b/src/mainboard/google/mistral/chromeos.c @@ -24,11 +24,14 @@ { gpio_input(GPIO_WP_STATE); gpio_input(GPIO_REC_STATE); + gpio_input(GPIO_DEV_STATE); } void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { + {GPIO_DEV_STATE.addr, ACTIVE_HIGH, + gpio_get(GPIO_DEV_STATE), "developer"}, {GPIO_REC_STATE.addr, ACTIVE_LOW, gpio_get(GPIO_REC_STATE), "recovery"}, {GPIO_WP_STATE.addr, ACTIVE_LOW, -- To view, visit https://review.coreboot.org/c/coreboot/+/31826 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id0093dec38720bb54c7b0f35db42bd851ab875ba Gerrit-Change-Number: 31826 Gerrit-PatchSet: 1 Gerrit-Owner: SANTHOSH JANARDHANA HASSAN <sahassan(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/mistral: Ignore REC switch if TPM isn't ready
by Patrick Georgi (Code Review) 11 Mar '20

11 Mar '20

Hello SANTHOSH JANARDHANA HASSAN, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32272 to review the following change. Change subject: mb/google/mistral: Ignore REC switch if TPM isn't ready ...................................................................... mb/google/mistral: Ignore REC switch if TPM isn't ready The recovery button's state is cached in the TPM, but on first boot Cr50 isn't ready yet for this task, which leads to a reboot further down the road (to get TPM up). To not confuse matters further, only act on the recovery button if the TPM is in fact able to cache the state. BUG=b:129878075 BRANCH=none TEST=recovery button is only read on second boot Change-Id: I1ad2c148be4cbdbb2afa05c46c483d89855e1959 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/google/mistral/chromeos.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/32272/1 diff --git a/src/mainboard/google/mistral/chromeos.c b/src/mainboard/google/mistral/chromeos.c index 9b69a4f..e0306b16 100644 --- a/src/mainboard/google/mistral/chromeos.c +++ b/src/mainboard/google/mistral/chromeos.c @@ -72,6 +72,9 @@ gpio_t rec_sw; static enum switch_state saved_state = not_probed; + if (is_tpm_detected() == 0) + return saved_state; + if (saved_state != not_probed) return saved_state; -- To view, visit https://review.coreboot.org/c/coreboot/+/32272 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1ad2c148be4cbdbb2afa05c46c483d89855e1959 Gerrit-Change-Number: 32272 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: SANTHOSH JANARDHANA HASSAN <sahassan(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: TEMP: NOT FOR REVIEW: google/mistral: Add LP5562 driver
by SANTHOSH JANARDHANA HASSAN (Code Review) 11 Mar '20

11 Mar '20

Hello Yuji Sasaki, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32693 to review the following change. Change subject: TEMP: NOT FOR REVIEW: google/mistral: Add LP5562 driver ...................................................................... TEMP: NOT FOR REVIEW: google/mistral: Add LP5562 driver Add LP5562 driver to mistral board file. BUG=b:116352348 TEST=build coreboot and chromeos-bootimage, run on mistral. Signed-off-by: Yuji Sasaki <sasakiy(a)chromium.org> Change-Id: I0c26ac952671cb94a2e5681da6e2f2eafddedb48 --- M src/drivers/i2c/lp5562/led_lp5562_programs.c M src/mainboard/google/mistral/Kconfig M src/mainboard/google/mistral/board.h M src/mainboard/google/mistral/bootblock.c M src/mainboard/google/mistral/chromeos.c 5 files changed, 119 insertions(+), 94 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/32693/1 diff --git a/src/drivers/i2c/lp5562/led_lp5562_programs.c b/src/drivers/i2c/lp5562/led_lp5562_programs.c index f322f6a..e837dfd 100644 --- a/src/drivers/i2c/lp5562/led_lp5562_programs.c +++ b/src/drivers/i2c/lp5562/led_lp5562_programs.c @@ -60,12 +60,12 @@ /* RGB set to 000000, resulting in all LEDs off. */ static const uint8_t solid_00_text[] = { - 0x40, 0x00, 0xc0, 0x00 + 0x40, 0, 0xc0, 0x00 }; /* Rgb set to 128, resulting in a brightish white color. */ -static const uint8_t solid_80_text[] = { - 0x40, 0x80, 0xc0, 0x00 +static const uint8_t solid_FF_text[] = { + 0x40, 255, 0xc0, 0x00 }; static const TiLp5562Program solid_000000_program = { @@ -88,44 +88,94 @@ } }; -static const TiLp5562Program solid_808080_program = { +static const TiLp5562Program solid_FFFFFF_program = { { { /* Engine1:Blue */ - solid_80_text, - sizeof(solid_80_text), + solid_FF_text, + sizeof(solid_FF_text), 0, }, { /* Engine2:Green */ - solid_80_text, - sizeof(solid_80_text), + solid_FF_text, + sizeof(solid_FF_text), 0, }, { /* Engine3:Red */ - solid_80_text, - sizeof(solid_80_text), + solid_FF_text, + sizeof(solid_FF_text), 0, }, } }; /* + * fdr_press1.src + * + 1 00 .ENGINE1(B) + 2 00 4000 set_pwm 0 + 3 01 C000 end + 4 + 5 10 .ENGINE2(G) + 6 10 40CC set_pwm 204 + 7 11 C000 end + 8 + 9 20 .ENGINE3(R) + 10 20 40FF set_pwm 255 + 11 21 C000 end +*/ + +static const uint8_t fdr_press1_b_text[] = { + 0x40, 0, 0xc0, 0x00, +}; + +static const uint8_t fdr_press1_g_text[] = { + 0x40, 204, 0xc0, 0x00 +}; + +static const uint8_t fdr_press1_r_text[] = { + 0x40, 255, 0xc0, 0x00 +}; + +static const TiLp5562Program fdr_press1_program = { + { + { + fdr_press1_b_text, + sizeof(fdr_press1_b_text), + 0, + }, + { + fdr_press1_g_text, + sizeof(fdr_press1_g_text), + 0, + }, + { + fdr_press1_r_text, + sizeof(fdr_press1_r_text), + 0, + }, + } +}; + +/* + * blink_recovery1.src + * 1 00 .ENGINE1(B) 2 00 E200 trigger w3 - 3 01 409B set_pwm 155 + 3 01 4000 set_pwm 0 4 02 E200 trigger w3 5 03 4000 set_pwm 0 6 04 0000 gotostart 7 8 10 .ENGINE2(G) 9 10 E200 trigger w3 - 10 11 4032 set_pwm 50 + 10 11 40CC set_pwm 204 11 12 E200 trigger w3 12 13 4000 set_pwm 0 13 14 0000 gotostart 14 15 20 .ENGINE3(R) 16 20 E006 trigger s21 - 17 21 4001 set_pwm 1 + 17 21 40FF set_pwm 255 18 22 5300 wait 300 19 23 E006 trigger s21 20 24 4000 set_pwm 0 @@ -133,48 +183,13 @@ 22 26 0000 gotostart */ -static const uint8_t blink_wipeout1_b_text[] = { - 0xe2, 0x00, 0x40, 155, 0xe2, 0x00, 0x40, 0, - 0x00, 0x00, -}; - -static const uint8_t blink_wipeout1_g_text[] = { - 0xe2, 0x00, 0x40, 50, 0xe2, 0x00, 0x40, 0, - 0x00, 0x00, -}; - -static const uint8_t blink_wipeout1_r_text[] = { - 0xe0, 0x06, 0x40, 1, 0x53, 0x00, 0xe0, 0x06, - 0x40, 0, 0x53, 0x00, 0x00, 0x00 -}; - -static const TiLp5562Program blink_wipeout1_program = { - { - { - blink_wipeout1_b_text, - sizeof(blink_wipeout1_b_text), - 0, - }, - { - blink_wipeout1_g_text, - sizeof(blink_wipeout1_g_text), - 0, - }, - { - blink_wipeout1_r_text, - sizeof(blink_wipeout1_r_text), - 0, - }, - } -}; - static const uint8_t blink_recovery1_b_text[] = { - 0xe2, 0x00, 0x40, 10, 0xe2, 0x00, 0x40, 0, + 0xe2, 0x00, 0x40, 0, 0xe2, 0x00, 0x40, 0, 0x00, 0x00, }; static const uint8_t blink_recovery1_g_text[] = { - 0xe2, 0x00, 0x40, 100, 0xe2, 0x00, 0x40, 0, + 0xe2, 0x00, 0x40, 204, 0xe2, 0x00, 0x40, 0, 0x00, 0x00, }; @@ -187,73 +202,69 @@ { { blink_recovery1_b_text, - sizeof(blink_wipeout1_b_text), + sizeof(blink_recovery1_b_text), 0, }, { blink_recovery1_g_text, - sizeof(blink_wipeout1_g_text), + sizeof(blink_recovery1_g_text), 0, }, { blink_recovery1_r_text, - sizeof(blink_wipeout1_r_text), + sizeof(blink_recovery1_r_text), 0, }, } }; /* - * fade_in1.src + * preboot1.src * 1 00 .ENGINE1(B) 2 00 4000 set_pwm 0 3 01 E200 trigger w3 - 4 02 1B4C ramp 1000, 77 # ramp up to 155 for 2 seconds - 5 03 1A4D ramp 1000, 78 - 6 04 C000 end - 7 - 8 10 .ENGINE2(G) - 9 10 4000 set_pwm 0 - 10 11 E200 trigger w3 - 11 12 4318 ramp 1000, 25 # ramp up to 50 for 2 seconds - 12 13 4318 ramp 1000, 25 - 13 14 C000 end - 14 - 15 20 .ENGINE3(R) - 16 20 E006 trigger s21 - 17 21 4001 set_pwm 1 - 18 22 E006 trigger s21 - 19 23 C000 end + 4 02 0D4C ramp 500, 77 + 5 03 C000 end + 6 + 7 10 .ENGINE2(G) + 8 10 4000 set_pwm 0 + 9 11 E200 trigger w3 + 10 12 0D4C ramp 500, 77 + 11 13 C000 end + 12 + 13 20 .ENGINE3(R) + 14 20 4000 set_pwm 0 + 15 21 E006 trigger s21 + 16 22 0D4C ramp 500, 77 + 17 23 C000 end */ -static const uint8_t fade_in1_b_text[] = { - 0x40, 0, 0xe2, 0x00, 0x1b, 0x4c, 0x1a, 0x4d, - 0xc0, 0x00 +static const uint8_t preboot1_b_text[] = { + 0x40, 0x00, 0xe2, 0x00, 0x0d, 0x4c, 0xc0, 0x00 }; -static const uint8_t fade_in1_g_text[] = { - 0x40, 0, 0xe2, 0x00, 0x43, 0x18, 0x43, 0x18, - 0xc0, 0x00 +static const uint8_t preboot1_g_text[] = { + 0x40, 0x00, 0xe2, 0x00, 0x0d, 0x4c, 0xc0, 0x00 }; -static const uint8_t fade_in1_r_text[] = { - 0xe0, 0x06, 0x40, 1, 0xe0, 0x06, 0x00 +static const uint8_t preboot1_r_text[] = { + 0x40, 0x00, 0xe0, 0x06, 0x0d, 0x4c, 0xc0, 0x00 }; -static const TiLp5562Program fade_in1_program = { +static const TiLp5562Program preboot1_program = { { { - fade_in1_b_text, - sizeof(fade_in1_b_text), + preboot1_b_text, + sizeof(preboot1_b_text), 0, }, { - fade_in1_g_text, - sizeof(fade_in1_g_text), + preboot1_g_text, + sizeof(preboot1_g_text), 0, }, { - fade_in1_r_text, - sizeof(fade_in1_r_text), + preboot1_r_text, + sizeof(preboot1_r_text), 0, }, } @@ -265,9 +276,9 @@ * be changed soon. */ {LED_ALL_OFF, {&solid_000000_program} }, - {LED_RECOVERY_PUSHED, {&solid_808080_program} }, - {LED_WIPEOUT_REQUEST, {&blink_wipeout1_program} }, + {LED_RECOVERY_PUSHED, {&solid_FFFFFF_program} }, + {LED_WIPEOUT_REQUEST, {&fdr_press1_program} }, {LED_RECOVERY_REQUEST, {&blink_recovery1_program} }, - {LED_NORMAL_BOOT, {&fade_in1_program} }, + {LED_NORMAL_BOOT, {&preboot1_program} }, {}, /* Empty record to mark the end of the table. */ }; diff --git a/src/mainboard/google/mistral/Kconfig b/src/mainboard/google/mistral/Kconfig index 87d2df8..4529abd 100644 --- a/src/mainboard/google/mistral/Kconfig +++ b/src/mainboard/google/mistral/Kconfig @@ -15,6 +15,7 @@ select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_SPI_TPM_CR50 + select DRIVERS_I2C_LED_LP5562 config VBOOT select VBOOT_VBNV_FLASH diff --git a/src/mainboard/google/mistral/board.h b/src/mainboard/google/mistral/board.h index 51e4bf2..88db42c 100644 --- a/src/mainboard/google/mistral/board.h +++ b/src/mainboard/google/mistral/board.h @@ -23,6 +23,7 @@ #define GPIO_H1_AP_INT GPIO(53) #define GPIO_WP_STATE GPIO(54) #define GPIO_REC_STATE GPIO(77) +#define GPIO_LED_ENABLE GPIO(119) void setup_chromeos_gpios(void); diff --git a/src/mainboard/google/mistral/bootblock.c b/src/mainboard/google/mistral/bootblock.c index be7a71e..da9dda8 100644 --- a/src/mainboard/google/mistral/bootblock.c +++ b/src/mainboard/google/mistral/bootblock.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -15,9 +15,14 @@ #include <bootblock_common.h> #include <timestamp.h> +#include <delay.h> #include "board.h" void bootblock_mainboard_init(void) { + gpio_output(GPIO_LED_ENABLE, 0); + udelay(2); + gpio_set(GPIO_LED_ENABLE, 1); + mdelay(2); gpio_input_pullup(GPIO_H1_AP_INT); } diff --git a/src/mainboard/google/mistral/chromeos.c b/src/mainboard/google/mistral/chromeos.c index e0306b16..f220151 100644 --- a/src/mainboard/google/mistral/chromeos.c +++ b/src/mainboard/google/mistral/chromeos.c @@ -18,6 +18,8 @@ #include <console/console.h> #include <security/tpm/tis.h> #include <timer.h> +#include <drivers/i2c/lp5562/led_lp5562.h> +#include <soc/blsp.h> #include "board.h" void setup_chromeos_gpios(void) @@ -65,6 +67,11 @@ wipeout_req }; +static void display_pattern(int pattern) +{ + led_lp5562_display_pattern(BLSP_QUP_ID_1, pattern); +} + static enum switch_state get_rec_sw_state(void) { struct stopwatch sw; @@ -83,11 +90,11 @@ if (!sampled_value) { saved_state = no_req; - //display_pattern(WWR_NORMAL_BOOT); + display_pattern(LED_NORMAL_BOOT); return saved_state; } - //display_pattern(WWR_RECOVERY_PUSHED); + display_pattern(LED_RECOVERY_PUSHED); printk(BIOS_INFO, "recovery button pressed\n"); stopwatch_init_msecs_expire(&sw, WIPEOUT_MODE_DELAY_MS); @@ -99,7 +106,7 @@ } while (!stopwatch_expired(&sw)); if (sampled_value) { - //display_pattern(WWR_WIPEOUT_REQUEST); + display_pattern(LED_WIPEOUT_REQUEST); printk(BIOS_INFO, "wipeout requested, checking recovery\n"); stopwatch_init_msecs_expire(&sw, RECOVERY_MODE_EXTRA_DELAY_MS); do { @@ -110,14 +117,14 @@ if (sampled_value) { saved_state = recovery_req; - //display_pattern(WWR_RECOVERY_REQUEST); + display_pattern(LED_RECOVERY_REQUEST); printk(BIOS_INFO, "recovery requested\n"); } else { saved_state = wipeout_req; } } else { saved_state = no_req; - //display_pattern(WWR_NORMAL_BOOT); + display_pattern(LED_NORMAL_BOOT); } return saved_state; -- To view, visit https://review.coreboot.org/c/coreboot/+/32693 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0c26ac952671cb94a2e5681da6e2f2eafddedb48 Gerrit-Change-Number: 32693 Gerrit-PatchSet: 1 Gerrit-Owner: SANTHOSH JANARDHANA HASSAN <sahassan(a)google.com> Gerrit-Reviewer: Yuji Sasaki <sasakiy(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: TEMP: NOT FOR REVIEW: google/mistral: Limit FDR detection for verstage
by Yuji Sasaki (Code Review) 11 Mar '20

11 Mar '20

Yuji Sasaki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32904 Change subject: TEMP: NOT FOR REVIEW: google/mistral: Limit FDR detection for verstage ...................................................................... TEMP: NOT FOR REVIEW: google/mistral: Limit FDR detection for verstage FDR switch detection and LED state change must only be functional when called in verstage. get_recovery_mode_switch() is called from ramstage as part of elog function but this is informational purpose, should not affecting LED state and boot mode. This CL is adding #if directives to limit FDR detection for verstage. When get_recovery_mode_switch() is called from other stages, it just return current FDR switch state but do not change LED state or boot mode. BUG=b:131622855 TEST=Build and run on DUT, keep pushing FDR switch and power on, verify it do not fall into secondary FDR detection loop in ramstage after "recovery requested" in verstage. Signed-off-by: Yuji Sasaki <sasakiy(a)chromium.org> Change-Id: Ib034acca2bcf39728e58b468e69e74620b086a10 --- M src/mainboard/google/mistral/chromeos.c 1 file changed, 19 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/32904/1 diff --git a/src/mainboard/google/mistral/chromeos.c b/src/mainboard/google/mistral/chromeos.c index f220151..8873edd 100644 --- a/src/mainboard/google/mistral/chromeos.c +++ b/src/mainboard/google/mistral/chromeos.c @@ -67,6 +67,11 @@ wipeout_req }; +/* + * FDR switch detection and LED state change is only functional + * when called in verstage. + */ +#if defined(__VERSTAGE__) static void display_pattern(int pattern) { led_lp5562_display_pattern(BLSP_QUP_ID_1, pattern); @@ -130,6 +135,20 @@ return saved_state; } +/* + * get_recovery_mode_switch is called from ramstage as part of + * elog function, but this is informational purpose to show current + * FDR switch state, should not affecting LED and boot mode. + */ +#else // defined(__VERSTAGE) +static enum switch_state get_rec_sw_state(void) +{ + gpio_t rec_sw = GPIO_REC_STATE; + int sampled_value = !gpio_get(rec_sw); + return sampled_value ? recovery_req : no_req; +} +#endif // defined(__VERSTAGE) + int get_recovery_mode_switch(void) { return get_rec_sw_state() == recovery_req; -- To view, visit https://review.coreboot.org/c/coreboot/+/32904 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib034acca2bcf39728e58b468e69e74620b086a10 Gerrit-Change-Number: 32904 Gerrit-PatchSet: 1 Gerrit-Owner: Yuji Sasaki <sasakiy(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: TEMP: NOT FOR REVIEW qcs405: Enable bl31
by Name of user not set (Code Review) 11 Mar '20

11 Mar '20

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31899 Change subject: TEMP: NOT FOR REVIEW qcs405: Enable bl31 ...................................................................... TEMP: NOT FOR REVIEW qcs405: Enable bl31 Keeping it seperate to include bl31.elf till we can build bl31 from repo Change-Id: Icca865369358e54a042b2dce02072c05761194b2 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/arch/arm64/Makefile.inc M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/soc.c 3 files changed, 16 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/31899/1 diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 6bb7196..bf2f01b 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -157,6 +157,8 @@ ifeq ($(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE),y) +ifneq ($(CONFIG_SOC_QUALCOMM_QCS405),y) + ifeq ($(CONFIG_ARM64_BL31_EXTERNAL_FILE),"") BL31_SOURCE := $(top)/3rdparty/arm-trusted-firmware @@ -235,6 +237,8 @@ endif # CONFIG_ARM64_USE_SECURE_OS +endif # CONFIG_SOC_QUALCOMM_QCS405 + endif # CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE endif # CONFIG_ARCH_RAMSTAGE_ARM64 diff --git a/src/soc/qualcomm/qcs405/Makefile.inc b/src/soc/qualcomm/qcs405/Makefile.inc index 8c57f4a..b6ad8c2 100644 --- a/src/soc/qualcomm/qcs405/Makefile.inc +++ b/src/soc/qualcomm/qcs405/Makefile.inc @@ -107,4 +107,15 @@ @printf "Generating: $(subst $(obj)/,,$(@))\n" cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin endif +################################################################################ +BL31_FILE := $(QCS405_BLOB)/bl31.elf +bl31_file := $(shell ls $(BL31_FILE)) +ifneq (,$(findstring $(BL31_FILE),$(bl31_file))) + BL31_CBFS := $(CONFIG_CBFS_PREFIX)/bl31 + $(BL31_CBFS)-file := $(BL31_FILE) + $(BL31_CBFS)-type := payload + $(BL31_CBFS)-compression := none + cbfs-files-y += $(BL31_CBFS) +endif +################################################################################ endif diff --git a/src/soc/qualcomm/qcs405/soc.c b/src/soc/qualcomm/qcs405/soc.c index ea52eb8..e22a3d8 100644 --- a/src/soc/qualcomm/qcs405/soc.c +++ b/src/soc/qualcomm/qcs405/soc.c @@ -23,7 +23,7 @@ void bootmem_platform_add_ranges(void) { - bootmem_add_range((uintptr_t)_dram_reserved, _dram_reserved_size, BM_MEM_BL31); + bootmem_add_range((uintptr_t)_dram_reserved, REGION_SIZE(dram_reserved), BM_MEM_BL31); } static void soc_read_resources(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/31899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icca865369358e54a042b2dce02072c05761194b2 Gerrit-Change-Number: 31899 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

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Change in ...coreboot[master]: TEMP: NOT FOR REVIEW: Mistral: Add board id detection using TPM
by Name of user not set (Code Review) 11 Mar '20

11 Mar '20

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31898 Change subject: TEMP: NOT FOR REVIEW: Mistral: Add board id detection using TPM ...................................................................... TEMP: NOT FOR REVIEW: Mistral: Add board id detection using TPM This patch adds support to select the board id based on the TPM availability. Change-Id: Ifa7b17085364bb631f43a133839773033721062d Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/drivers/spi/tpm/tis.c M src/drivers/spi/tpm/tpm.c M src/mainboard/google/mistral/boardid.c M src/security/tpm/tis.h M src/soc/qualcomm/qcs405/include/soc/memlayout.ld M src/soc/qualcomm/qcs405/include/soc/symbols.h 6 files changed, 49 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/31898/1 diff --git a/src/drivers/spi/tpm/tis.c b/src/drivers/spi/tpm/tis.c index 40bf27d..9d0f664 100644 --- a/src/drivers/spi/tpm/tis.c +++ b/src/drivers/spi/tpm/tis.c @@ -4,6 +4,8 @@ * found in the LICENSE file. */ +#include <symbols.h> +#include <soc/symbols.h> #include <arch/early_variables.h> #include <console/console.h> #include <string.h> @@ -93,3 +95,13 @@ return 0; } + +unsigned int is_tpm_detected(void) +{ + if (0 == (*_tpm_detection)) + return 0; + else if (1 == (*_tpm_detection)) + return 1; + else + return 0; +} diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index aad7610..b2484aa0 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -15,6 +15,8 @@ * Specification Revision 00.43". */ +#include <symbols.h> +#include <soc/symbols.h> #include <arch/early_variables.h> #include <assert.h> #include <commonlib/endian.h> @@ -457,10 +459,13 @@ } if (!retries) { + *_tpm_detection = 0; printk(BIOS_ERR, "\n%s: Failed to connect to the TPM\n", __func__); return -1; } + else + *_tpm_detection = 1; printk(BIOS_INFO, " done!\n"); diff --git a/src/mainboard/google/mistral/boardid.c b/src/mainboard/google/mistral/boardid.c index b86f84e..66309c0 100644 --- a/src/mainboard/google/mistral/boardid.c +++ b/src/mainboard/google/mistral/boardid.c @@ -17,6 +17,7 @@ #include <gpio.h> #include <console/console.h> #include <stdlib.h> +#include <security/tpm/tis.h> /* * Mistral boards dedicate to the board ID three GPIOs in ternary mode: 105, 106 @@ -32,8 +33,22 @@ [1] = GPIO(106), [0] = GPIO(105)}; - bid = gpio_binary_first_base3_value(pins, ARRAY_SIZE(pins)); - printk(BIOS_INFO, "Board ID %d\n", bid); + if (0 == is_tpm_detected()) { + bid = 25; /* Assign 25 for EVB boards */ + printk(BIOS_DEBUG, "EVB Board ID: %d\n", bid); + } else { + bid = 0; /* Assign 0 for Proto boards */ + + /* The board id assigned for Proto boards is 0. + * Since gpios are not wired in the initial phase, + * we will get 0 whihch is a coincidence. + * To make sure it starts working, after gpios are + * wired, reassign the value read from gpios to id. + */ + bid = gpio_binary_first_base3_value(pins, ARRAY_SIZE(pins)); + + printk(BIOS_DEBUG, "Proto Board ID: %d\n", bid); + } return bid; } diff --git a/src/security/tpm/tis.h b/src/security/tpm/tis.h index c410838..dd2f348 100644 --- a/src/security/tpm/tis.h +++ b/src/security/tpm/tis.h @@ -97,4 +97,14 @@ */ int tis_plat_irq_status(void); +/* + * This function is_tpm_detected() sets tpm_detection value to be 1 upon TPM detection. + * The value is writted to the specific region of SRAM which will retain + * the TPM Detection information between various stages of the bootloader. + * + * Returns 0 if TPM is not detected + * Returns 1 if TPM is detected + */ +unsigned int is_tpm_detected(void); + #endif /* TIS_H_ */ diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld index c23f651..585abf5 100644 --- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld +++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld @@ -39,6 +39,7 @@ TIMESTAMP(0x8C50000, 1K) PRERAM_CBMEM_CONSOLE(0x8C50400, 32K) PRERAM_CBFS_CACHE(0x8C58400, 70K) + REGION(tpm_detection, 0x8CFD000, 0x8, 0x10) BSRAM_END(0x8D80000) DRAM_START(0x80000000) diff --git a/src/soc/qualcomm/qcs405/include/soc/symbols.h b/src/soc/qualcomm/qcs405/include/soc/symbols.h index 45e6988..ce6e7cb 100644 --- a/src/soc/qualcomm/qcs405/include/soc/symbols.h +++ b/src/soc/qualcomm/qcs405/include/soc/symbols.h @@ -23,4 +23,8 @@ DECLARE_REGION(bsram); DECLARE_REGION(dram_reserved); +extern u8 _tpm_detection[]; +extern u8 _etpm_detection[]; +#define _tpm_detection_size (_etpm_detection - _tpm_detection) + #endif // _SOC_QUALCOMM_QCS405_SYMBOLS_H_ -- To view, visit https://review.coreboot.org/c/coreboot/+/31898 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa7b17085364bb631f43a133839773033721062d Gerrit-Change-Number: 31898 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

6 16

Change in ...coreboot[master]: google/mistral: Support triggering Recovery/FDR.
by SANTHOSH JANARDHANA HASSAN (Code Review) 11 Mar '20

11 Mar '20

SANTHOSH JANARDHANA HASSAN has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31173 Change subject: google/mistral: Support triggering Recovery/FDR. ...................................................................... google/mistral: Support triggering Recovery/FDR. Implement triggering factory data reset and recovery mechanism based on Recovery/FDR switch(GPIO77) value. Change-Id: Ifdbd696ee3fd9f073cc44a49ad341cad7e33845e Signed-off-by: Santhosh Hassan <sahassan(a)google.com> --- M src/mainboard/google/mistral/Kconfig A src/mainboard/google/mistral/board.h M src/mainboard/google/mistral/chromeos.c M src/mainboard/google/mistral/verstage.c 4 files changed, 142 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/31173/1 diff --git a/src/mainboard/google/mistral/Kconfig b/src/mainboard/google/mistral/Kconfig index 5e97bb6..f28a382 100644 --- a/src/mainboard/google/mistral/Kconfig +++ b/src/mainboard/google/mistral/Kconfig @@ -23,6 +23,7 @@ select GBB_FLAG_DEV_SCREEN_SHORT_DELAY select GBB_FLAG_FORCE_DEV_SWITCH_ON select GBB_FLAG_FORCE_MANUAL_RECOVERY + select VBOOT_WIPEOUT_SUPPORTED config MAINBOARD_DIR string diff --git a/src/mainboard/google/mistral/board.h b/src/mainboard/google/mistral/board.h new file mode 100644 index 0000000..2e23ce3 --- /dev/null +++ b/src/mainboard/google/mistral/board.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __COREBOOT_SRC_MAINBOARD_GOOGLE_MISTRAL_BOARD_H +#define __COREBOOT_SRC_MAINBOARD_GOOGLE_MISTRAL_BOARD_H + +#include <gpio.h> +#include <soc/gpio.h> + + +#define GPIO_H1_AP_INT GPIO(53) +#define GPIO_WP_STATE GPIO(54) +#define GPIO_REC_STATE GPIO(77) + +void setup_chromeos_gpios(void); + +#endif /* ! __COREBOOT_SRC_MAINBOARD_GOOGLE_MISTRAL_BOARD_H */ diff --git a/src/mainboard/google/mistral/chromeos.c b/src/mainboard/google/mistral/chromeos.c index ba0b1da..0405c4e 100644 --- a/src/mainboard/google/mistral/chromeos.c +++ b/src/mainboard/google/mistral/chromeos.c @@ -14,11 +14,18 @@ */ #include <boot/coreboot_tables.h> -#include <gpio.h> #include <security/tpm/tis.h> -#include <soc/gpio.h> +#include <bootmode.h> +#include <timer.h> +#include <console/console.h> +#include "board.h" -#define GPIO_H1_AP_INT GPIO(53) +void setup_chromeos_gpios(void) +{ + gpio_input_pullup(GPIO_H1_AP_INT); + gpio_input(GPIO_WP_STATE); + gpio_input(GPIO_REC_STATE); +} void fill_lb_gpios(struct lb_gpios *gpios) { @@ -27,9 +34,109 @@ {GPIO_H1_AP_INT.addr, ACTIVE_LOW, gpio_get(GPIO_H1_AP_INT), "TPM interrupt"}, }; +#endif + struct lb_gpio chromeos_gpios[] = { + {GPIO_REC_STATE.addr, ACTIVE_LOW, + gpio_get(GPIO_REC_STATE), "recovery"}, + {GPIO_WP_STATE.addr, ACTIVE_LOW, + gpio_get(GPIO_WP_STATE), "write protect"}, + {-1, ACTIVE_LOW, 1, "power"}, + {-1, ACTIVE_LOW, 0, "lid"}, + }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); -#endif +} + +#define WIPEOUT_MODE_DELAY_MS (8 * 1000) +#define RECOVERY_MODE_EXTRA_DELAY_MS (8 * 1000) + +/* + * The recovery switch: it needs to be pressed for a + * certain duration at startup to signal different requests: + * + * - keeping it pressed for 8 to 16 seconds after startup signals the need for + * factory reset (wipeout); + * - keeping it pressed for longer than 16 seconds signals the need for Chrome + * OS recovery. + * + * The state is read once and cached for following inquiries. The below enum + * lists possible states. + */ +enum switch_state { + not_probed = -1, + no_req, + recovery_req, + wipeout_req +}; + +static enum switch_state get_rec_sw_state(void) +{ + struct stopwatch sw; + int sampled_value; + gpio_t rec_sw; + static enum switch_state saved_state = not_probed; + + if (saved_state != not_probed) + return saved_state; + + rec_sw = GPIO_REC_STATE; + sampled_value = !gpio_get(rec_sw); + + if (!sampled_value) { + saved_state = no_req; + //display_pattern(WWR_NORMAL_BOOT); + return saved_state; + } + + //display_pattern(WWR_RECOVERY_PUSHED); + printk(BIOS_INFO, "recovery button pressed\n"); + + stopwatch_init_msecs_expire(&sw, WIPEOUT_MODE_DELAY_MS); + + do { + sampled_value = !gpio_get(rec_sw); + if (!sampled_value) + break; + } while (!stopwatch_expired(&sw)); + + if (sampled_value) { + //display_pattern(WWR_WIPEOUT_REQUEST); + printk(BIOS_INFO, "wipeout requested, checking recovery\n"); + stopwatch_init_msecs_expire(&sw, RECOVERY_MODE_EXTRA_DELAY_MS); + do { + sampled_value = !gpio_get(rec_sw); + if (!sampled_value) + break; + } while (!stopwatch_expired(&sw)); + + if (sampled_value) { + saved_state = recovery_req; + //display_pattern(WWR_RECOVERY_REQUEST); + printk(BIOS_INFO, "recovery requested\n"); + } else { + saved_state = wipeout_req; + } + } else { + saved_state = no_req; + //display_pattern(WWR_NORMAL_BOOT); + } + + return saved_state; +} + +int get_recovery_mode_switch(void) +{ + return get_rec_sw_state() == recovery_req; +} + +int get_wipeout_mode_switch(void) +{ + return get_rec_sw_state() == wipeout_req; +} + +int get_write_protect_state(void) +{ + return !gpio_get(GPIO_WP_STATE); } #if 0 diff --git a/src/mainboard/google/mistral/verstage.c b/src/mainboard/google/mistral/verstage.c index 7ea21c7..a63f61e 100644 --- a/src/mainboard/google/mistral/verstage.c +++ b/src/mainboard/google/mistral/verstage.c @@ -15,18 +15,10 @@ */ #include <console/console.h> -#include <gpio.h> #include <security/vboot/vboot_common.h> #include <spi-generic.h> #include <soc/clock.h> -#include <soc/gpio.h> - -#define GPIO_H1_AP_INT GPIO(53) - -static void setup_chromeos_gpios(void) -{ - gpio_input_pullup(GPIO_H1_AP_INT); -} +#include "board.h" void verstage_mainboard_init(void) { -- To view, visit https://review.coreboot.org/c/coreboot/+/31173 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifdbd696ee3fd9f073cc44a49ad341cad7e33845e Gerrit-Change-Number: 31173 Gerrit-PatchSet: 1 Gerrit-Owner: SANTHOSH JANARDHANA HASSAN <sahassan(a)google.com> Gerrit-MessageType: newchange

5 12

Change in ...coreboot[master]: google/mistral: add CR50
by Patrick Georgi (Code Review) 11 Mar '20

11 Mar '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30716 Change subject: google/mistral: add CR50 ...................................................................... google/mistral: add CR50 Change-Id: Ia8184e48a43866b7d065952c13e7176bb3b52e4d Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/google/mistral/Kconfig 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/30716/1 diff --git a/src/mainboard/google/mistral/Kconfig b/src/mainboard/google/mistral/Kconfig index b614a37..eddc1a3 100644 --- a/src/mainboard/google/mistral/Kconfig +++ b/src/mainboard/google/mistral/Kconfig @@ -14,6 +14,8 @@ select SPI_FLASH_WINBOND select MAINBOARD_HAS_CHROMEOS select MISSING_BOARD_RESET + select MAINBOARD_HAS_TPM2 + select MAINBOARD_HAS_SPI_TPM_CR50 config VBOOT select VBOOT_VBNV_FLASH @@ -29,6 +31,10 @@ string default "Google" +config DRIVER_TPM_SPI_BUS + hex + default 0x4 + ########################################################## #### Update below when adding a new derivative board. #### ########################################################## -- To view, visit https://review.coreboot.org/c/coreboot/+/30716 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8184e48a43866b7d065952c13e7176bb3b52e4d Gerrit-Change-Number: 30716 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 5

Change in ...coreboot[master]: google/mistral: Enable additional GBB flags in vboot.
by SANTHOSH JANARDHANA HASSAN (Code Review) 11 Mar '20

11 Mar '20

SANTHOSH JANARDHANA HASSAN has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31171 Change subject: google/mistral: Enable additional GBB flags in vboot. ...................................................................... google/mistral: Enable additional GBB flags in vboot. Enable GBB_FLAG_FORCE_MANUAL_RECOVERY and GBB_FLAG_DEV_SCREEN_SHORT_DELAY as additional default flags. Change-Id: If1e7effb2d74b861f196ce861a3c8779ce89b3b2 Signed-off-by: Santhosh Hassan <sahassan(a)google.com> Change-Id: Ic0a00c6a7bfa5090461c2c9da0bc6ee73118ca74 --- M src/mainboard/google/mistral/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/31171/1 diff --git a/src/mainboard/google/mistral/Kconfig b/src/mainboard/google/mistral/Kconfig index c369472..5e97bb6 100644 --- a/src/mainboard/google/mistral/Kconfig +++ b/src/mainboard/google/mistral/Kconfig @@ -20,7 +20,9 @@ config VBOOT select VBOOT_VBNV_FLASH select VBOOT_NO_BOARD_SUPPORT + select GBB_FLAG_DEV_SCREEN_SHORT_DELAY select GBB_FLAG_FORCE_DEV_SWITCH_ON + select GBB_FLAG_FORCE_MANUAL_RECOVERY config MAINBOARD_DIR string -- To view, visit https://review.coreboot.org/c/coreboot/+/31171 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic0a00c6a7bfa5090461c2c9da0bc6ee73118ca74 Gerrit-Change-Number: 31171 Gerrit-PatchSet: 1 Gerrit-Owner: SANTHOSH JANARDHANA HASSAN <sahassan(a)google.com> Gerrit-MessageType: newchange

3 9

Change in ...coreboot[master]: qclib: Differentiate between ES_1.0 and ES1.1 silicon
by Name of user not set (Code Review) 11 Mar '20

11 Mar '20

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30903 Change subject: qclib: Differentiate between ES_1.0 and ES1.1 silicon ...................................................................... qclib: Differentiate between ES_1.0 and ES1.1 silicon The PBL data ptr gets passed at a different location for 1.0 vs 1.1. So let us read the revision from TCSR and pass the right value. Change-Id: Id23493c8cfc64f62964a453cd32a0ddc4bff9e84 Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/qclib_execute.c 1 file changed, 14 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/30903/1 diff --git a/src/soc/qualcomm/qcs405/qclib_execute.c b/src/soc/qualcomm/qcs405/qclib_execute.c index 917a04c..214128f 100644 --- a/src/soc/qualcomm/qcs405/qclib_execute.c +++ b/src/soc/qualcomm/qcs405/qclib_execute.c @@ -14,6 +14,7 @@ */ #include <string.h> +#include <arch/io.h> #include <arch/cache.h> #include <arch/mmu.h> #include <cbfs.h> @@ -28,7 +29,12 @@ #define DCB_NAME "/dcb" #define QCLIB_NAME "/qclib" -#define PBL_DATA_PTR 0x8c101a0 //0x14810188 +#define TCSR_SOC_HW_VERSION 0x0194D000 +#define ES_1_0 0x20140100 +#define ES_1_1 0x20140101 + +#define PBL_DATA_PTR_ES_1_0 0x8c101a0 +#define PBL_DATA_PTR_ES_1_1 0x8c111a0 void qclib_load_and_run(void) { @@ -36,6 +42,7 @@ void *arg; int ret_code; struct mmu_context pre_qclib_mmu_context; + void *pbl_data_ptr; struct prog qclib = PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX QCLIB_NAME); @@ -67,7 +74,12 @@ if (cbfs_prog_stage_load(&qclib)) goto fail; - prog_set_entry(&qclib, qclib.entry, (void *)PBL_DATA_PTR); + if (read32((void *) TCSR_SOC_HW_VERSION) == ES_1_1) + pbl_data_ptr = (void *) 0x8c111a0; + else + pbl_data_ptr = (void *) 0x8c101a0; + + prog_set_entry(&qclib, qclib.entry, (void *)pbl_data_ptr); printk(BIOS_DEBUG, "\n\n\nQCLib is about to Initialize PMIC and DDR\n"); printk(BIOS_DEBUG, "Jumping to QCLib code at %p(%p)\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/30903 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id23493c8cfc64f62964a453cd32a0ddc4bff9e84 Gerrit-Change-Number: 30903 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

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