coreboot-gerrit May 2019

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Change in ...coreboot[master]: qcs405: Update memory layout
by Name of user not set (Code Review) 11 Mar '20

11 Mar '20

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32108 Change subject: qcs405: Update memory layout ...................................................................... qcs405: Update memory layout Update the memory layout so that we get to use the unused space. This enables us to use default kernel size of 512 MB configuration in depthcharge. Change-Id: I419bfefadb610c3fdf2b8ed56965801be0dc4e90 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/include/soc/memlayout.ld 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/32108/1 diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld index 68642d6..6856919 100644 --- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld +++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld @@ -45,6 +45,6 @@ DRAM_START(0x80000000) /* DDR Carveout for BL31 usage */ REGION(dram_reserved, 0x85000000, 0x5100000, 4096) - POSTRAM_CBFS_CACHE(0x9F800000, 384K) - RAMSTAGE(0x9F860000, 128K) + POSTRAM_CBFS_CACHE(0x8A100000, 384K) + RAMSTAGE(0x8A160000, 128K) } -- To view, visit https://review.coreboot.org/c/coreboot/+/32108 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I419bfefadb610c3fdf2b8ed56965801be0dc4e90 Gerrit-Change-Number: 32108 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

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Change in ...coreboot[master]: google/mistral: move bootblock and fmap to their previous location
by Patrick Georgi (Code Review) 11 Mar '20

11 Mar '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30965 Change subject: google/mistral: move bootblock and fmap to their previous location ...................................................................... google/mistral: move bootblock and fmap to their previous location Helps with the current boot hack that requires them to be at certain locations. Also make GBB smaller. We don't store graphics in there anymore. Change-Id: I09c3a6d4221990cd51d4793693a7c7ae2df85105 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/google/mistral/chromeos.fmd 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/30965/1 diff --git a/src/mainboard/google/mistral/chromeos.fmd b/src/mainboard/google/mistral/chromeos.fmd index a9bdd7b..ffeec16 100644 --- a/src/mainboard/google/mistral/chromeos.fmd +++ b/src/mainboard/google/mistral/chromeos.fmd @@ -2,9 +2,9 @@ WP_RO@0x0 0x400000 { RO_SECTION@0x0 0x3e0000 { BOOTBLOCK@0 128K - COREBOOT(CBFS)@0x20000 0x2e0000 - FMAP@0x300000 0x1000 - GBB@0x301000 0xdef00 + COREBOOT(CBFS)@0x3e000 0x1e0000 + FMAP@0x21e000 0x1000 + GBB@0x3dd000 0x2f00 RO_FRID@0x3dff00 0x100 } RO_VPD@0x3e0000 0x20000 -- To view, visit https://review.coreboot.org/c/coreboot/+/30965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09c3a6d4221990cd51d4793693a7c7ae2df85105 Gerrit-Change-Number: 30965 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common: Add more GPIO definition macros
by Thomas Heijligen (Code Review) 10 Mar '20

10 Mar '20

Hello Nico Huber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/31350 to review the following change. Change subject: soc/intel/common: Add more GPIO definition macros ...................................................................... soc/intel/common: Add more GPIO definition macros Change-Id: Id1a3c00aa8a857afa08e745b0b6a578b01fa6d47 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/31350/1 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 35f89c9..4d9f2be 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -236,6 +236,16 @@ PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)) +#define PAD_CFG_GPI_IOSSTATE(pad, pull, rst, iosstate) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ + PAD_PULL(pull) | PAD_IOSSTATE(iosstate)) + +#define PAD_CFG_GPI_IOSSTATE_IOSTERM(pad, pull, rst, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_CFG0_TX_DISABLE, \ + PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) + /* General purpose input. The following macro sets the * Host Software Pad Ownership to GPIO Driver mode. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id1a3c00aa8a857afa08e745b0b6a578b01fa6d47 Gerrit-Change-Number: 31350 Gerrit-PatchSet: 1 Gerrit-Owner: Thomas Heijligen <src(a)posteo.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Set correct temperature threshold for PCH Therm...
by Sumeet R Pawnikar (Code Review) 09 Mar '20

09 Mar '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33129 Change subject: soc/intel/cannonlake: Set correct temperature threshold for PCH Thermal Sensor ...................................................................... soc/intel/cannonlake: Set correct temperature threshold for PCH Thermal Sensor PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown when S0ix is enabled. BUG=None BRANCH=None TEST=Verified Thermal Device (B0: D18: F0) TSPM offset 0x1c [LTT (8:0)] value is 0xFA. Change-Id: Ibd1e669fcbfe8dc6e6e5556aa5b1373ed19c3685 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/finalize.c M src/soc/intel/cannonlake/include/soc/iomap.h A src/soc/intel/cannonlake/include/soc/thermal.h A src/soc/intel/cannonlake/thermal.c 6 files changed, 147 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/33129/1 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 1328944..03faa3c 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -53,6 +53,7 @@ ramstage-y += smmrelocate.c ramstage-y += spi.c ramstage-y += systemagent.c +ramstage-y += thermal.c ramstage-y += uart.c ramstage-y += vr_config.c ramstage-y += sd.c diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index 0d51c1c..39f808b 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -421,6 +421,9 @@ * Bit 0: MISCCFG_GPDLCGEN */ uint8_t gpio_pm[TOTAL_GPIO_COMM]; + + /* PCH Trip Temperature */ + uint8_t pch_trip_temp; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 4dfd15b..d277658 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -32,6 +32,7 @@ #include <soc/pm.h> #include <soc/smbus.h> #include <soc/systemagent.h> +#include <soc/thermal.h> #include <stdlib.h> #include "chip.h" @@ -63,6 +64,16 @@ uint8_t reg8; tco_lockdown(); + + /* + * Set low maximum temp value used for dynamic thermal sensor + * shutdown consideration. + * + * If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the + * thermal sensor when CPU is in a C-state and DTS Temp <= LTT. + */ + pch_thermal_configuration(); + /* * Disable ACPI PM timer based on dt policy * diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h index 100bd11..488d938 100644 --- a/src/soc/intel/cannonlake/include/soc/iomap.h +++ b/src/soc/intel/cannonlake/include/soc/iomap.h @@ -76,6 +76,8 @@ #define HECI1_BASE_ADDRESS 0xfeda2000 +#define THERMAL_BASE_ADDRESS 0xfe600000 + #define VTD_BASE_ADDRESS 0xFED90000 #define VTD_BASE_SIZE 0x00004000 /* diff --git a/src/soc/intel/cannonlake/include/soc/thermal.h b/src/soc/intel/cannonlake/include/soc/thermal.h new file mode 100644 index 0000000..1f4085c --- /dev/null +++ b/src/soc/intel/cannonlake/include/soc/thermal.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_THERMAL_H_ +#define _SOC_THERMAL_H_ + +#define THERMAL_SENSOR_POWER_MANAGEMENT 0x1c + +/* Enable thermal sensor power management */ +void pch_thermal_configuration(void); + +#endif diff --git a/src/soc/intel/cannonlake/thermal.c b/src/soc/intel/cannonlake/thermal.c new file mode 100644 index 0000000..9d62843 --- /dev/null +++ b/src/soc/intel/cannonlake/thermal.c @@ -0,0 +1,106 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/mmio.h> +#include <device/pci_ops.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/thermal.h> + +#include "chip.h" + +#define MAX_TRIP_TEMP 205 +#define DEFAULT_TRIP_TEMP 50 + +static void *pch_thermal_get_bar(struct device *dev) +{ + uintptr_t bar; + + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + /* + * Bits [31:12] are the base address as per EDS for Thermal Device, + * Don't care about [11:0] bits + */ + return (void *)(bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK); +} + +static void pch_thermal_set_bar(struct device *dev, uintptr_t tempbar) +{ + uint8_t pcireg; + + /* Assign Resources to Thermal Device */ + /* Clear BIT 1-2 of Command Register */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config8(dev, PCI_COMMAND, pcireg); + + /* Program Temporary BAR for Thermal Device */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, tempbar); + pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0); + + /* Enable Bus Master and MMIO Space */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config8(dev, PCI_COMMAND, pcireg); +} + +/* PCH Low Temp Threshold (LTT) */ +static uint16_t pch_get_ltt_value(struct device *dev) +{ + static struct soc_intel_skylake_config *config; + uint16_t ltt_value; + uint16_t trip_temp = DEFAULT_TRIP_TEMP; + + config = dev->chip_info; + + if (config->pch_trip_temp) + trip_temp = config->pch_trip_temp; + + if (trip_temp > MAX_TRIP_TEMP) + die("Input PCH temp trip is higher than allowed range!"); + + /* Trip Point Temp = (LTT / 2 - 50 degree C) */ + ltt_value = (trip_temp + 50) * 2; + + return ltt_value; +} + +/* Enable thermal sensor power management */ +void pch_thermal_configuration(void) +{ + uint16_t reg16; + struct device *dev = PCH_DEV_THERMAL; + if (!dev) { + printk(BIOS_ERR, "PCH_DEV_THERMAL device not found!\n"); + return; + } + void *thermalbar = pch_thermal_get_bar(dev); + + /* Use default pre-ram bar */ + if (!thermalbar) { + pch_thermal_set_bar(dev, THERMAL_BASE_ADDRESS); + thermalbar = (void *)THERMAL_BASE_ADDRESS; + } + + /* Set Low Temp Threshold (LTT) at TSPM offset 0x1c[8:0] */ + reg16 = read16(thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT); + reg16 &= ~0x1ff; + /* Low Temp Threshold (LTT) */ + reg16 |= pch_get_ltt_value(dev); + write16(thermalbar + THERMAL_SENSOR_POWER_MANAGEMENT, reg16); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/33129 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd1e669fcbfe8dc6e6e5556aa5b1373ed19c3685 Gerrit-Change-Number: 33129 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/mainboard/protectli/vault: Add FW2B and FW4B boards support
by Michał Żygowski (Code Review) 09 Mar '20

09 Mar '20

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32076 Change subject: src/mainboard/protectli/vault: Add FW2B and FW4B boards support ...................................................................... src/mainboard/protectli/vault: Add FW2B and FW4B boards support Working and tested: - both HDMI (SeaBIOS + OS) - USB (SeaBIOS + OS: MSC, keyboard, mouse) - mSATA SSD (SeaBIOS detection and booting installed Debian Stretch) - Ethernet (PXE boot, OS network access) - serial debug port UART0 on SuperIO (coreboot + SeaBIOS, OS console) TODO: - mainboard documentation - Azalia configuration for audio - test mPCIe WiFi TEST=booting Debian Stretch with Linux kernel 4.9.0 on both platforms Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I553fd3a89299314a855f055014ca7645100e12e7 --- A src/mainboard/protectli/Kconfig A src/mainboard/protectli/Kconfig.name A src/mainboard/protectli/vault/Kconfig A src/mainboard/protectli/vault/Kconfig.name A src/mainboard/protectli/vault/Makefile.inc A src/mainboard/protectli/vault/acpi/ec.asl A src/mainboard/protectli/vault/acpi/mainboard.asl A src/mainboard/protectli/vault/acpi/superio.asl A src/mainboard/protectli/vault/acpi_tables.c A src/mainboard/protectli/vault/board_info.txt A src/mainboard/protectli/vault/boardid.c A src/mainboard/protectli/vault/cmos.layout A src/mainboard/protectli/vault/dsdt.asl A src/mainboard/protectli/vault/fadt.c A src/mainboard/protectli/vault/gpio.c A src/mainboard/protectli/vault/hda_verb.c A src/mainboard/protectli/vault/irqroute.c A src/mainboard/protectli/vault/irqroute.h A src/mainboard/protectli/vault/mainboard.c A src/mainboard/protectli/vault/onboard.h A src/mainboard/protectli/vault/ramstage.c A src/mainboard/protectli/vault/romstage.c A src/mainboard/protectli/vault/smihandler.c A src/mainboard/protectli/vault/variants/fw2b/devicetree.cb A src/mainboard/protectli/vault/variants/fw4b/devicetree.cb 25 files changed, 1,519 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/32076/1 diff --git a/src/mainboard/protectli/Kconfig b/src/mainboard/protectli/Kconfig new file mode 100644 index 0000000..3a1b7a4 --- /dev/null +++ b/src/mainboard/protectli/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_PROTECTLI + +choice + prompt "Mainboard model" + +source "src/mainboard/protectli/*/Kconfig.name" + +endchoice + +source "src/mainboard/protectli/*/Kconfig" + +config MAINBOARD_VENDOR + string "Mainboard Vendor" + default "Protectli" + +endif # VENDOR_PROTECTLI diff --git a/src/mainboard/protectli/Kconfig.name b/src/mainboard/protectli/Kconfig.name new file mode 100644 index 0000000..adc7f05 --- /dev/null +++ b/src/mainboard/protectli/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_PROTECTLI + bool "Protectli" diff --git a/src/mainboard/protectli/vault/Kconfig b/src/mainboard/protectli/vault/Kconfig new file mode 100644 index 0000000..d35f941 --- /dev/null +++ b/src/mainboard/protectli/vault/Kconfig @@ -0,0 +1,72 @@ +if BOARD_PROTECTLI_FW2B || BOARD_PROTECTLI_FW4B + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select SOC_INTEL_BRASWELL + select PCIEXP_L1_SUB_STATE + select CACHE_MRC_SETTINGS + select SUPERIO_ITE_IT8613E + +config MAINBOARD_DIR + string + default protectli/vault + +config VARIANT_DIR + string + default "fw2b" if BOARD_PROTECTLI_FW2B + default "fw4b" if BOARD_PROTECTLI_FW4B + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config MAINBOARD_PART_NUMBER + string + default "FW2B" if BOARD_PROTECTLI_FW2B + default "FW4B" if BOARD_PROTECTLI_FW4B + +config MAINBOARD_VENDOR + string + default "Protectli" + +config DIMM_MAX + int + default 1 + +config DIMM_SPD_SIZE + int + default 256 + +config MAX_CPUS + int + default 2 if BOARD_PROTECTLI_FW2B + default 4 if BOARD_PROTECTLI_FW4B + +config PXE_ROM_ID + string + default "8086,1539" if BOARD_PROTECTLI_FW2B + default "8086,157b" if BOARD_PROTECTLI_FW4B + +if !RUN_FSP_GOP +config VGA_BIOS_FILE + string + default "3rdparty/blobs/mainboard/protectli/vault/vgabios.bin" + help + The C0 version of the video bios gets computed from this name + so that they can both be added. Only the correct one for the + system will be run. + +config VGA_BIOS_ID + string + default "8086,22b0" + help + The VGA_BIOS_ID for the C0 version of the video bios is hardcoded + in soc/intel/braswell/Makefile.inc as 8086,22b1 + +endif #RUN_FSP_GOP + +endif # BOARD_PROTECTLI_FW2B diff --git a/src/mainboard/protectli/vault/Kconfig.name b/src/mainboard/protectli/vault/Kconfig.name new file mode 100644 index 0000000..2255371 --- /dev/null +++ b/src/mainboard/protectli/vault/Kconfig.name @@ -0,0 +1,5 @@ +config BOARD_PROTECTLI_FW2B + bool "FW2B" + +config BOARD_PROTECTLI_FW4B + bool "FW4B" diff --git a/src/mainboard/protectli/vault/Makefile.inc b/src/mainboard/protectli/vault/Makefile.inc new file mode 100644 index 0000000..507941d --- /dev/null +++ b/src/mainboard/protectli/vault/Makefile.inc @@ -0,0 +1,25 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2015 Intel Corp. +## Copyright (C) 2016 Andreas Galauner <andreas(a)galauner.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += boardid.c +ramstage-y += gpio.c +ramstage-y += irqroute.c +ramstage-y += ramstage.c +ramstage-y += hda_verb.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + diff --git a/src/mainboard/protectli/vault/acpi/ec.asl b/src/mainboard/protectli/vault/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/protectli/vault/acpi/ec.asl diff --git a/src/mainboard/protectli/vault/acpi/mainboard.asl b/src/mainboard/protectli/vault/acpi/mainboard.asl new file mode 100644 index 0000000..b43c757 --- /dev/null +++ b/src/mainboard/protectli/vault/acpi/mainboard.asl @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "onboard.h" + +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + Name (_UID, 1) + } +} + +Scope (\_SB.PCI0.I2C2) +{ + /* Realtek Audio Codec */ + Device (RTEK) + { + Name (_ADR, 0) // _ADR: Address + Name (_HID, AUDIO_CODEC_HID) // _HID: Hardware ID + Name (_CID, AUDIO_CODEC_CID) // _CID: Compatible ID + Name (_DDN, AUDIO_CODEC_DDN) // _DDN: DOS Device Name + Name (_UID, 1) // _UID: Unique ID + + Method(_CRS, 0x0, NotSerialized) + { + Name(SBUF,ResourceTemplate () + { + I2CSerialBus( + AUDIO_CODEC_I2C_ADDR, + ControllerInitiated, + 400000, + AddressingMode7Bit, + "\\_SB.PCI0.I2C2", + ) + GpioInt (Edge, ActiveHigh, ExclusiveAndWake, + PullNone, , "\\_SB.GPSE") + { JACK_DETECT_GPIO_INDEX } + } ) + Return (SBUF) + } + + Method (_STA) + { + Return (0xF) + } + + } +} + +Scope (\_SB.PCI0.LPEA) +{ + Name (GBUF, ResourceTemplate () + { + /* Jack Detect (index 0) */ + GpioInt (Edge, ActiveHigh, ExclusiveAndWake, PullNone,, + "\\_SB.GPSE") { JACK_DETECT_GPIO_INDEX } + }) +} + +Scope (\_SB.GPNC) +{ + Method (_AEI, 0, Serialized) // _AEI: ACPI Event Interrupts + { + Name (RBUF, ResourceTemplate () + { + GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, + "\\_SB.GPNC") { BOARD_SCI_GPIO_INDEX } + }) + Return (RBUF) + } + + Method (_E0F, 0, NotSerialized) // _Exx: Edge-Triggered GPE + { + } +} diff --git a/src/mainboard/protectli/vault/acpi/superio.asl b/src/mainboard/protectli/vault/acpi/superio.asl new file mode 100644 index 0000000..efa9b3e --- /dev/null +++ b/src/mainboard/protectli/vault/acpi/superio.asl @@ -0,0 +1,24 @@ +#include "onboard.h" + +Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, One) + Name (_ADR, 0) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () { + FixedIO (0x03F8, 0x08) + IRQNoFlags () {4} + }) + + Name (_PRS, ResourceTemplate () { + StartDependentFn (0, 0) { + FixedIO (0x03F8, 0x08) + IRQNoFlags () {4} + } + EndDependentFn () + }) +} diff --git a/src/mainboard/protectli/vault/acpi_tables.c b/src/mainboard/protectli/vault/acpi_tables.c new file mode 100644 index 0000000..e3275ed --- /dev/null +++ b/src/mainboard/protectli/vault/acpi_tables.c @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2017 Andreas Galauner <andreas(a)galauner.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <arch/smp/mpspec.h> +#include <cbmem.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/acpi.h> +#include <soc/iomap.h> +#include <soc/nvs.h> +#include <string.h> +#include <types.h> +#include <boardid.h> +#include "onboard.h" + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset(gnvs, 0, sizeof(*gnvs)); + + acpi_init_gnvs(gnvs); + + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* Disable DPTF */ + gnvs->dpte = 0; + + /* PMIC is configured in I2C0, hidden it from OS */ + gnvs->dev.lpss_en[LPSS_NVS_I2C1] = 0; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + current = acpi_madt_irq_overrides(current); + + return current; +} diff --git a/src/mainboard/protectli/vault/board_info.txt b/src/mainboard/protectli/vault/board_info.txt new file mode 100644 index 0000000..141a0e1 --- /dev/null +++ b/src/mainboard/protectli/vault/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Protectli +Board name: Vault +Category: sbc +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/protectli/vault/boardid.c b/src/mainboard/protectli/vault/boardid.c new file mode 100644 index 0000000..810be7e --- /dev/null +++ b/src/mainboard/protectli/vault/boardid.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright(C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2017 Andreas Galauner <andreas(a)galauner.de> + * Copyright (C) 2018 3mdeb Embedded Systems Consulting + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include <stdlib.h> + +uint32_t board_id(void) +{ + MAYBE_STATIC int id = -1; + + return (uint32_t) id; +} diff --git a/src/mainboard/protectli/vault/cmos.layout b/src/mainboard/protectli/vault/cmos.layout new file mode 100644 index 0000000..ae46e10 --- /dev/null +++ b/src/mainboard/protectli/vault/cmos.layout @@ -0,0 +1,133 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2015 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/protectli/vault/dsdt.asl b/src/mainboard/protectli/vault/dsdt.asl new file mode 100644 index 0000000..c965115 --- /dev/null +++ b/src/mainboard/protectli/vault/dsdt.asl @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2017 Andreas Galauner <andreas(a)galauner.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 // OEM revision +) +{ + /* Some generic macros */ + #include <acpi/platform.asl> + + /* global NVS and variables */ + #include <acpi/globalnvs.asl> + + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <acpi/southcluster.asl> + } + } + Scope (\_SB.PCI0) + { + Device (RP03) + { + Name (_ADR, 0x001C0002) // _ADR: Address + OperationRegion(RPXX, PCI_Config, 0x00, 0x10) + } + } + + /* Chipset specific sleep states */ + #include <acpi/sleepstates.asl> + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/protectli/vault/fadt.c b/src/mainboard/protectli/vault/fadt.c new file mode 100644 index 0000000..38ccd78 --- /dev/null +++ b/src/mainboard/protectli/vault/fadt.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2017 Andreas Galauner <andreas(a)galauner.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/acpi.h> +#include <string.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + acpi_fill_in_fadt(fadt); + + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES; + + fadt->pstate_cnt = 0x80; + fadt->cst_cnt = 0x85; + fadt->p_lvl2_lat = 0x65; + fadt->p_lvl3_lat = 0x3e9; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/protectli/vault/gpio.c b/src/mainboard/protectli/vault/gpio.c new file mode 100644 index 0000000..687d93b --- /dev/null +++ b/src/mainboard/protectli/vault/gpio.c @@ -0,0 +1,265 @@ +/* + * This file is part of the coreboot project. + * + * Copyright(C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2017 Andreas Galauner <andreas(a)galauner.de> + * Copyright (C) 2019 Protectli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "irqroute.h" +#include <soc/gpio.h> +#include <stdlib.h> +#include <boardid.h> +#include "onboard.h" +#include "gpio.h" + +/* South East Community */ +static const struct soc_gpio_map gpse_gpio_map[] = { + GPIO_NC, /* 00 MF_PLT_CLK0 */ + GPIO_NC, /* 01 PWM1 */ + GPIO_NC, /* 02 MF_PLT_CLK1 */ + GPIO_INPUT_PD_20K, /* 03 MF_PLT_CLK4 */ + GPIO_NC, /* 04 MF_PLT_CLK3 */ + GPIO_NC, /* 05 PWM0*/ + GPIO_INPUT_PD_20K, /* 06 MF_PLT_CLK5 */ + GPIO_INPUT_PD_20K, /* 07 MF_PLT_CLK2 */ + GPIO_NC, /* 15 SDMMC2_D3_CD_B */ + GPIO_NC, /* 16 SDMMC1_CLK */ + GPIO_NC, /* 17 SDMMC1_D0 */ + GPIO_NC, /* 18 SDMMC2_D1 */ + GPIO_NC, /* 19 SDMMC2_CLK */ + GPIO_NC, /* 20 SDMMC1_D2 */ + GPIO_NC, /* 21 SDMMC2_D2 */ + GPIO_NC, /* 22 SDMMC2_CMD */ + GPIO_NC, /* 23 SDMMC1_CMD */ + GPIO_NC, /* 24 SDMMC1_D1 */ + GPIO_NC, /* 25 SDMMC2_D0 */ + GPIO_NC, /* 26 SDMMC1_D3_CD_B */ + GPIO_NC, /* 30 SDMMC3_D1 */ + GPIO_NC, /* 31 SDMMC3_CLK */ + GPIO_NC, /* 32 SDMMC3_D3 */ + GPIO_NC, /* 33 SDMMC3_D2 */ + GPIO_NC, /* 34 SDMMC3_CMD */ + GPIO_NC, /* 35 SDMMC3_D0 */ + NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */ + NATIVE_PU20K(1), /* 46 LPC_CLKRUNB */ + NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */ + NATIVE_PU20K(1), /* 48 LPC_FRAMEB */ + NATIVE_PD20K(1), /* 49 MF_LPC_CLKOUT1 */ + NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */ + Native_M1, /* 51 MF_LPC_CLKOUT0 */ + NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */ + GPIO_NC, /* 60 SPI1_MISO */ + GPIO_NC, /* 61 SPI1_CS0_B */ + GPIO_NC, /* 62 SPI1_CLK */ + GPIO_NC, /* 63 MMC1_D6 */ + GPIO_NC, /* 64 SPI1_MOSI */ + GPIO_NC, /* 65 MMC1_D5 */ + GPIO_NC, /* 66 SPI1_CS1_B */ + GPIO_NC, /* 67 MMC1_D4_SD_WE */ + GPIO_NC, /* 68 MMC1_D7 */ + GPIO_NC, /* 69 MMC1_RCLK */ + NATIVE_PU20K(1), /* 75 USB_OC1_B */ + NATIVE_PU20K(1), /* 76 PMU_RESETBUTTON_B */ + GPI(trig_level_low, L2, P_20K_H, non_maskable, en_rx_data, NA, NA), + /* 77 GPIO_ALERT */ + GPIO_NC, /* 78 SDMMC3_PWR_EN_B */ + NATIVE_PU20K(1), /* 79 ILB_SERIRQ */ + NATIVE_PU20K(1), /* 80 USB_OC0_B */ + GPIO_NC, /* 81 SDMMC3_CD_B */ + NATIVE_PU20K(1), /* 82 SPKR */ + NATIVE_PD20K(1), /* 83 SUSPWRDNACK */ + GPIO_NC, /* 84 SDMMC1_RCLK */ + GPIO_NC, /* 85 SDMMC3_1P8_EN */ + GPIO_END +}; + +/* South West Community */ +static const struct soc_gpio_map gpsw_gpio_map[] = { + NATIVE_PU20K(1), /* 00 FST_SPI_D2 */ + NATIVE_PU20K(1), /* 01 FST_SPI_D0 */ + NATIVE_PU20K(1), /* 02 FST_SPI_CLK */ + NATIVE_PU20K(1), /* 03 FST_SPI_D3 */ + GPO_FUNC(P_20K_H, 1), /* 04 FST_SPI_CS1_B */ + NATIVE_PU20K(1), /* 05 FST_SPI_D1 */ + NATIVE_PU20K(1), /* 06 FST_SPI_CS0_B */ + GPO_FUNC(P_5K_L, 0), /* 07 FST_SPI_CS2_B */ + GPIO_NC, /* 15 UART1_RTS_B */ + GPIO_NC, /* 16 UART1_RXD */ + GPIO_NC, /* 17 UART2_RXD */ + GPIO_NC, /* 18 UART1_CTS_B */ + GPIO_NC, /* 19 UART2_RTS_B */ + GPIO_NC, /* 20 UART1_TXD */ + GPIO_NC, /* 21 UART2_TXD */ + NATIVE_PD20K(1), /* 22 UART2_CTS_B */ + NATIVE_PD20K(2), /* 30 MF_HDA_CLK */ + NATIVE_PD20K(2), /* 31 GPIO_SW31/MF_HDA_RSTB */ + NATIVE_PD20K(2), /* 32 GPIO_SW32 /MF_HDA_SDI0 */ + NATIVE_PD20K(2), /* 33 MF_HDA_SDO */ + GPO_FUNC(P_20K_L, 1), /* 34 MF_HDA_DOCKRSTB */ + NATIVE_PD20K(2), /* 35 MF_HDA_SYNC */ + NATIVE_PD20K(2), /* 36 GPIO_SW36 MF_HDA_SDI1 */ + GPIO_INPUT_PD_20K, /* 37 MF_HDA_DOCKENB */ + NATIVE_PU1K_INVTX(1), /* 45 I2C5_SDA */ + NATIVE_PU1K(1), /* 46 I2C4_SDA */ + NATIVE_PU1K_INVTX(1), /* 47 I2C6_SDA */ + NATIVE_PU1K_INVTX(1), /* 48 I2C5_SCL */ + NATIVE_FUNC(1, P_20K_H, inv_tx_enable), /* 49 I2C_NFC_SDA */ + NATIVE_PU1K(1), /* 50 I2C4_SCL */ + NATIVE_PU1K_INVTX(1), /* 51 I2C6_SCL */ + NATIVE_FUNC(1, P_20K_H, inv_tx_enable), /* 52 I2C_NFC_SCL */ + NATIVE_PU1K_INVTX(1), /* 60 I2C1_SDA */ + NATIVE_PU1K_INVTX(1), /* 61 I2C0_SDA */ + NATIVE_PU1K_INVTX(1), /* 62 I2C2_SDA */ + NATIVE_PU1K_INVTX(1), /* 63 I2C1_SCL */ + NATIVE_PU1K_INVTX(1), /* 64 I2C3_SDA */ + NATIVE_PU1K_INVTX(1), /* 65 I2C0_SCL */ + NATIVE_PU1K_INVTX(1), /* 66 I2C2_SCL */ + NATIVE_PU1K_INVTX(1), /* 67 I2C3_SCL */ + GPIO_NC, /* 75 SATA_GP0 */ + GPIO_NC, /* 76 SATA_GP1 */ + NATIVE_PD20K(1), /* 77 SATA_LEDN */ + NATIVE_PD20K(1), /* 78 SATA_GP2 */ + NATIVE_PU20K(1), /* 79 MF_SMB_ALERTB */ + NATIVE_PD20K(1), /* 80 SATA_GP3 */ + NATIVE_PU20K(1), /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ + NATIVE_PU20K(1), /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ + NATIVE_PU20K(1), /* 90 PCIE_CLKREQ0B */ + NATIVE_PU20K(1), /* 91 PCIE_CLKREQ1B */ + NATIVE_PD20K(1), /* 92 GP_SSP_2_CLK */ + NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B */ + NATIVE_PD20K(1), /* 94 GP_SSP_2_RXD */ + NATIVE_PU20K(1), /* 95 PCIE_CLKREQ3B */ + NATIVE_PD20K(1), /* 96 GP_SSP_2_FS */ + NATIVE_FUNC(1, P_20K_L, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ + GPIO_END +}; + + +/* North Community */ +static const struct soc_gpio_map gpn_gpio_map[] = { + NATIVE_PD20K(5), /* 00 GPIO_DFX0 */ + NATIVE_FUNC(5, P_20K_L, 0), /* 01 GPIO_DFX3 */ + GPO_FUNC(P_20K_H, 1), /* 02 GPIO_DFX7 */ + NATIVE_PD20K(5), /* 03 GPIO_DFX1 */ + GPO_FUNC(P_20K_H, 1), /* 04 GPIO_DFX5 */ + GPO_FUNC(P_20K_L, 1), /* 05 GPIO_DFX4 */ + NATIVE_PU20K(1), /* 06 GPIO_DFX8 */ + NATIVE_PD20K(5), /* 07 GPIO_DFX2 */ + NATIVE_PU20K(8), /* 08 GPIO_DFX6 */ + GPI(trig_edge_low, L8, P_20K_L, non_maskable, en_edge_rx_data, + UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ + GPO_FUNC(P_20K_L, 1), /* 16 SEC_GPIO_SUS10 */ + NATIVE_PD20K(1), /* 17 GPIO_SUS3 */ + GPI(trig_edge_low, L15, P_20K_H, non_maskable, en_edge_rx_data, NA, + SMI), /* 18 GPIO_SUS7 */ + NATIVE_PD20K(1), /* 19 GPIO_SUS1 */ + GPIO_INPUT_PU_20K, /* 20 GPIO_SUS5 */ + GPI(trig_edge_high, L2, P_20K_L, non_maskable, en_edge_rx_data, NA, + NA), /* 21 SEC_GPIO_SUS11 */ + NATIVE_PU20K(1), /* 22 GPIO_SUS4 */ + GPI(trig_level_high, L3, P_20K_H, non_maskable, en_rx_data, NA, NA), + /* 23 SEC_GPIO_SUS8 */ + NATIVE_PU20K(1), /* 24 GPIO_SUS2 */ + GPI(trig_edge_low, L14, P_20K_H, non_maskable, en_edge_rx_data, NA, + SCI), /* 25 GPIO_SUS6 */ + NATIVE_PU5K(1), /* 26 CX_PREQ_B */ + GPIO_INPUT_PD_20K, /* 27 SEC_GPIO_SUS9 */ + NATIVE_PU5K(1), /* 30 TRST_B */ + NATIVE_PD5K(1), /* 31 TCK */ + GPIO_SKIP, /* 32 PROCHOT_B */ + GPIO_SKIP, /* 33 SVID0_DATA */ + NATIVE_PU5K(1), /* 34 TMS */ + NATIVE_PU5K(1), /* 35 CX_PRDY_B_2 */ + Native_M1, /* 36 TDO_2 */ + NATIVE_PU5K(1), /* 37 CX_PRDY_B */ + GPIO_SKIP, /* 38 SVID0_ALERT_B */ + Native_M1, /* 39 TDO */ + GPIO_SKIP, /* 40 SVID0_CLK */ + NATIVE_PU5K(1), /* 41 TDI */ + GPIO_NC, /* 45 GP_CAMERASB05 */ + GPIO_NC, /* 46 GP_CAMERASB02 */ + GPIO_INPUT_PD_20K, /* 47 GP_CAMERASB08 */ + GPIO_NC, /* 48 GP_CAMERASB00 */ + GPIO_NC, /* 49 GP_CAMERASBO6 */ + GPIO_NC, /* 50 GP_CAMERASB10 */ + GPIO_NC, /* 51 GP_CAMERASB03 */ + GPIO_INPUT_PD_20K, /* 52 GP_CAMERASB09 */ + GPIO_NC, /* 53 GP_CAMERASB01 */ + GPIO_NC, /* 54 GP_CAMERASB07 */ + GPIO_INPUT_PD_20K, /* 55 GP_CAMERASB11 */ + GPIO_NC, /* 56 GP_CAMERASB04 */ + GPIO_OUT_HIGH, /* 60 PANEL0_BKLTEN */ + NATIVE_FUNC_TX_RX(en_edge_rx_data, 1, NA, inv_tx_enable), + /* 61 HV_DDI0_HPD */ + NATIVE_PU20K(1), /* 62 HV_DDI2_DDC_SDA */ + Native_M1, /* 63 PANEL1_BKLTCTL */ + NATIVE_FUNC_TX_RX(en_edge_rx_data, 1, NA, inv_tx_enable), + /* 64 HV_DDI1_HPD */ + GPIO_OUT_HIGH, /* 65 PANEL0_BKLTCTL */ + NATIVE_PU20K(1), /* 66 HV_DDI0_DDC_SDA */ + NATIVE_PU20K(1), /* 67 HV_DDI2_DDC_SCL */ + NATIVE_FUNC_TX_RX(en_edge_rx_data, 1, NA, inv_tx_enable), + /* 68 HV_DDI2_HPD */ + Native_M1, /* 69 PANEL1_VDDEN */ + Native_M1, /* 70 PANEL1_BKLTEN */ + NATIVE_PU20K(1), /* 71 HV_DDI0_DDC_SCL */ + GPIO_OUT_HIGH, /* 72 PANEL0_VDDEN */ + GPIO_END +}; + + +/* East Community */ +static const struct soc_gpio_map gpe_gpio_map[] = { + NATIVE_PU20K(1), /* 00 PMU_SLP_S3_B */ + NATIVE_PU20K(1), /* 01 PMU_BATLOW_B */ + NATIVE_PU20K(1), /* 02 SUS_STAT_B */ + NATIVE_PU20K(1), /* 03 PMU_SLP_S0IX_B */ + NATIVE_PD20K(1), /* 04 PMU_AC_PRESENT */ + NATIVE_PU20K(1), /* 05 PMU_PLTRST_B */ + NATIVE_PD20K(1), /* 06 PMU_SUSCLK */ + NATIVE_PU20K(1), /* 07 PMU_SLP_LAN_B */ + NATIVE_PU20K(1), /* 08 PMU_PWRBTN_B */ + NATIVE_PU20K(1), /* 09 PMU_SLP_S4_B */ + NATIVE_FUNC_TX_RX(en_rx_data << 2, 1, P_1K_H, NA), /* 10 PMU_WAKE_B */ + GPIO_NC, /* 11 PMU_WAKE_LAN_B */ + NATIVE_PD20K(1), /* 15 MF_GPIO_3 */ + GPO_FUNC(P_20K_L, 1), /* 16 MF_GPIO_7 */ + NATIVE_PU20K(1), /* 17 MF_I2C1_SCL */ + NATIVE_PD20K(1), /* 18 MF_GPIO_1 */ + GPO_FUNC(P_20K_L, 0), /* 19 MF_GPIO_5 */ + NATIVE_PU20K(1), /* 20 MF_GPIO_9 */ + NATIVE_PD20K(1), /* 21 MF_GPIO_0 */ + GPI(trig_level_low, L0, P_20K_H, NA, en_rx_data, NA, NA), + /* 22 MF_GPIO_4 */ + NATIVE_PU20K(1), /* 23 MF_GPIO_8 */ + NATIVE_PD20K(1), /* 24 MF_GPIO_2 */ + NATIVE_PD20K(1), /* 25 MF_GPIO_6 */ + NATIVE_PU20K(1), /* 26 MF_I2C1_SDA */ + GPIO_END +}; + + +static struct soc_gpio_config gpio_config = { + /* BSW */ + .north = gpn_gpio_map, + .southeast = gpse_gpio_map, + .southwest = gpsw_gpio_map, + .east = gpe_gpio_map +}; + +struct soc_gpio_config *mainboard_get_gpios(void) +{ + + return &gpio_config; +} diff --git a/src/mainboard/protectli/vault/hda_verb.c b/src/mainboard/protectli/vault/hda_verb.c new file mode 100644 index 0000000..ac10ef9 --- /dev/null +++ b/src/mainboard/protectli/vault/hda_verb.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Protectli + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[0] = {}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/protectli/vault/irqroute.c b/src/mainboard/protectli/vault/irqroute.c new file mode 100644 index 0000000..35a8fcc --- /dev/null +++ b/src/mainboard/protectli/vault/irqroute.c @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2017 Andreas Galauner <andreas(a)galauner.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/protectli/vault/irqroute.h b/src/mainboard/protectli/vault/irqroute.h new file mode 100644 index 0000000..250b227 --- /dev/null +++ b/src/mainboard/protectli/vault/irqroute.h @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2019 Protectli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/irq.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> + +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, D, B, C, A), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, C, A, A) + +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, 11), \ + PIRQ_PIC(B, 5), \ + PIRQ_PIC(C, 5), \ + PIRQ_PIC(D, 11), \ + PIRQ_PIC(E, 11), \ + PIRQ_PIC(F, 5), \ + PIRQ_PIC(G, 11), \ + PIRQ_PIC(H, 11) diff --git a/src/mainboard/protectli/vault/mainboard.c b/src/mainboard/protectli/vault/mainboard.c new file mode 100644 index 0000000..87f913b --- /dev/null +++ b/src/mainboard/protectli/vault/mainboard.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Protectli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/mmio.h> +#include <device/device.h> +#include <soc/iomap.h> + +#define BIOS_CONTROL_REG 0xFC +#define BIOS_CONTROL_WPD (1 << 0) + +#define IRQEN_REG 0x88 +#define UART_IRQ4_EN 0x10 + +static void mainboard_enable(struct device *dev) +{ + volatile void *addr = (void *)(SPI_BASE_ADDRESS + BIOS_CONTROL_REG); + + /* set Bios Write Protect Disable bit to allow saving MRC cache */ + write8(addr, read8(addr) | BIOS_CONTROL_WPD); + + /* Enable COM1 IRQ4 */ + addr = (void *)(ILB_BASE_ADDRESS + IRQEN_REG); + write8(addr, read8(addr) | UART_IRQ4_EN); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/protectli/vault/onboard.h b/src/mainboard/protectli/vault/onboard.h new file mode 100644 index 0000000..81170bd --- /dev/null +++ b/src/mainboard/protectli/vault/onboard.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2017 Andreas Galauner <andreas(a)galauner.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +/* + * Calculation of gpio based irq. + * Gpio banks ordering : GPSW, GPNC, GPEC, GPSE + * Max direct irq (MAX_DIRECT_IRQ) is 114. + * Size of gpio banks are + * GPSW_SIZE = 98 + * GPNC_SIZE = 73 + * GPEC_SIZE = 27 + * GPSE_SIZE = 86 + */ + + +/* Audio: Gpio index in SW bank */ +#define JACK_DETECT_GPIO_INDEX 77 + +/* SCI: Gpio index in N bank */ +#define BOARD_SCI_GPIO_INDEX 15 + +#define SDCARD_CD 81 + +#define AUDIO_CODEC_HID "10EC5670" +#define AUDIO_CODEC_CID "10EC5670" +#define AUDIO_CODEC_DDN "RTEK Codec Controller " +#define AUDIO_CODEC_I2C_ADDR 0x1C + +#define BCRD2_PMIC_I2C_BUS 0x01 + +#endif diff --git a/src/mainboard/protectli/vault/ramstage.c b/src/mainboard/protectli/vault/ramstage.c new file mode 100644 index 0000000..4d09f71 --- /dev/null +++ b/src/mainboard/protectli/vault/ramstage.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Intel Corporation + * Copyright (C) 2017 Andreas Galauner <andreas(a)galauner.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/ramstage.h> +#include <boardid.h> +#include "onboard.h" + +void mainboard_silicon_init_params(SILICON_INIT_UPD *params) +{ + //enable turbo mode + params->PcdTurboMode = 1; +} diff --git a/src/mainboard/protectli/vault/romstage.c b/src/mainboard/protectli/vault/romstage.c new file mode 100644 index 0000000..52260f4 --- /dev/null +++ b/src/mainboard/protectli/vault/romstage.c @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2017 Andreas Galauner <andreas(a)galauner.de> + * Copyright (C) 2019 Protectli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <device/pci_ops.h> +#include <fsp/car.h> +#include <soc/lpc.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8613e/it8613e.h> + +#define SERIAL1_DEV PNP_DEV(0x2e, IT8613E_SP1) +#define CLKIN_DEV PNP_DEV(0x2e, IT8613E_GPIO) + +/* Copy SPD data for on-board memory */ +void mainboard_fill_spd_data(struct pei_data *ps) +{ + struct spd_block blk = { + .addr_map = { 0x50 }, + }; + + get_spd_smbus(&blk); + + if (blk.spd_array[0][0] == 0) + die("No SPD present. Check DIMM!"); + + dump_spd_info(&blk); + + /* + * Set SPD and memory configuration: + * Memory type: 0=DimmInstalled, + * 1=SolderDownMemory, + * 2=DimmDisabled + */ + ps->spd_data_ch0 = blk.spd_array[0]; + ps->spd_ch0_config = 1; + ps->spd_ch1_config = 2; +} + +void car_mainboard_pre_console_init(void) +{ + ite_reg_write(CLKIN_DEV, 0x2c, 0x41); // disable K8 power seq + ite_reg_write(CLKIN_DEV, 0x2d, 0x02); // PCICLK 25MHz + ite_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); +} + +void mainboard_romstage_entry(struct romstage_params *rp) +{ + struct pei_data *ps = rp->pei_data; + + mainboard_fill_spd_data(ps); + + /* Call back into chipset code with platform values updated. */ + romstage_common(rp); + + /* + * FSP Memory Init enables built-in serial legacy port. + * Disable it and reconfigure serial port on SuperIO. + */ + pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, (u32) 0); + ite_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); +} + +void mainboard_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *memory_params) +{ + /* Update SPD data */ + memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0; + memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config; + memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config; +} diff --git a/src/mainboard/protectli/vault/smihandler.c b/src/mainboard/protectli/vault/smihandler.c new file mode 100644 index 0000000..d2cea20 --- /dev/null +++ b/src/mainboard/protectli/vault/smihandler.c @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2017 Andreas Galauner <andreas(a)galauner.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> + +#include <soc/nvs.h> +#include <soc/pm.h> +#include <soc/gpio.h> + +#include "onboard.h" + +/* The wake gpio is SUS_GPIO[0]. */ +#define WAKE_GPIO_EN SUS_GPIO_EN0 + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + smm_get_gnvs()->smif = 0; + break; + default: + return 0; + } + + /* + * On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + //gnvs->smif = 0; + return 1; +} + +/* + * The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that + * this includes the enable bits in the lower 16 bits. + */ +void mainboard_smi_gpi(uint32_t alt_gpio_smi) +{ +#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) + if (alt_gpio_smi & (1 << EC_SMI_GPI)) { + /* Process all pending events */ + while (mainboard_smi_ec() != 0) + ; + } +#endif +} + +void mainboard_smi_sleep(uint8_t slp_typ) +{ + /* Disable USB charging if required */ + switch (slp_typ) { + case ACPI_S3: + /* Enable wake pin in GPE block. */ + enable_gpe(WAKE_GPIO_EN); + break; + case ACPI_S5: + break; + } + +} + +int mainboard_smi_apmc(uint8_t apmc) +{ + switch (apmc) { + case APM_CNT_ACPI_ENABLE: + break; + case APM_CNT_ACPI_DISABLE: + break; + } + return 0; +} diff --git a/src/mainboard/protectli/vault/variants/fw2b/devicetree.cb b/src/mainboard/protectli/vault/variants/fw2b/devicetree.cb new file mode 100644 index 0000000..d9fd57e --- /dev/null +++ b/src/mainboard/protectli/vault/variants/fw2b/devicetree.cb @@ -0,0 +1,151 @@ +chip soc/intel/braswell + + ############################################################ + # Set the parameters for MemoryInit + ############################################################ + + register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB + + register "PcdMrcInitMmioSize" = "0x0800" + register "PcdMrcInitSpdAddr1" = "0xa0" + register "PcdMrcInitSpdAddr2" = "0xa2" + register "PcdIgdDvmt50PreAlloc" = "1" + register "PcdApertureSize" = "2" + register "PcdGttSize" = "1" + register "PcdDvfsEnable" = "0" + register "PcdCaMirrorEn" = "1" + + ############################################################ + # Set the parameters for SiliconInit + ############################################################ + + register "PcdSdcardMode" = "PCH_DISABLED" + register "PcdEnableHsuart0" = "0" + register "PcdEnableHsuart1" = "0" + register "PcdEnableAzalia" = "1" + register "PcdEnableXhci" = "1" + register "PcdEnableLpe" = "1" + register "PcdEnableDma0" = "1" + register "PcdEnableDma1" = "1" + register "PcdEnableI2C0" = "1" + register "PcdEnableI2C1" = "1" + register "PcdEnableI2C2" = "0" + register "PcdEnableI2C3" = "0" + register "PcdEnableI2C4" = "0" + register "PcdEnableI2C5" = "0" + register "PcdEnableI2C6" = "0" + register "PunitPwrConfigDisable" = "0" # Enable SVID + register "ChvSvidConfig" = "3" + register "PcdEmmcMode" = "PCH_DISABLED" + register "PcdUsb3ClkSsc" = "1" + register "PcdDispClkSsc" = "1" + register "PcdSataClkSsc" = "1" + register "PcdEnableSata" = "1" + register "Usb2Port0PerPortPeTxiSet" = "7" + register "Usb2Port0PerPortTxiSet" = "6" + register "Usb2Port0IUsbTxEmphasisEn" = "3" + register "Usb2Port0PerPortTxPeHalf" = "1" + register "Usb2Port1PerPortPeTxiSet" = "7" + register "Usb2Port1PerPortTxiSet" = "6" + register "Usb2Port1IUsbTxEmphasisEn" = "3" + register "Usb2Port1PerPortTxPeHalf" = "1" + register "Usb2Port2PerPortPeTxiSet" = "7" + register "Usb2Port2PerPortTxiSet" = "6" + register "Usb2Port2IUsbTxEmphasisEn" = "3" + register "Usb2Port2PerPortTxPeHalf" = "1" + register "Usb2Port3PerPortPeTxiSet" = "7" + register "Usb2Port3PerPortTxiSet" = "6" + register "Usb2Port3IUsbTxEmphasisEn" = "3" + register "Usb2Port3PerPortTxPeHalf" = "1" + register "Usb2Port4PerPortPeTxiSet" = "7" + register "Usb2Port4PerPortTxiSet" = "6" + register "Usb2Port4IUsbTxEmphasisEn" = "3" + register "Usb2Port4PerPortTxPeHalf" = "1" + register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a" + register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" + register "PcdSataInterfaceSpeed" = "3" + register "PcdPchSsicEnable" = "0" + register "PcdPchUsbSsicPort" = "0" + register "PcdPchUsbHsicPort" = "0" + register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM + register "PMIC_I2CBus" = "0" + register "ISPEnable" = "0" # Disable IUNIT + register "ISPPciDevConfig" = "3" + register "PcdSdDetectChk" = "0" # Disable SD card detect + # Follow Intel recommendation to set BSW D-stepping PERPORTRXISET 2 (low strength) + register "D0Usb2Port0PerPortRXISet" = "2" + register "D0Usb2Port1PerPortRXISet" = "2" + register "D0Usb2Port2PerPortRXISet" = "2" + register "D0Usb2Port3PerPortRXISet" = "2" + register "D0Usb2Port4PerPortRXISet" = "2" + + # LPE audio codec settings + register "lpe_codec_clk_src" = "LPE_CLK_SRC_PLL" # 19.2MHz clock + + # Disable devices in ACPI mode + register "lpss_acpi_mode" = "0" + register "emmc_acpi_mode" = "0" + register "sd_acpi_mode" = "0" + register "lpe_acpi_mode" = "0" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # 8086 2280 - SoC transaction router + device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display + device pci 03.0 off end # 8086 22b8 - Camera and Image Processor + device pci 0b.0 off end # 8086 22dc - PUNIT/DPTF + device pci 10.0 off end # 8086 2294 - MMC Port + device pci 12.0 off end # 8086 2296 - SD Port + device pci 13.0 on end # 8086 22a3 - Sata controller + device pci 14.0 on end # 8086 22b5 - USB XHCI + device pci 15.0 on end # 8086 22a8 - LP Engine Audio + device pci 16.0 off end # 8086 22b7 - USB device + device pci 18.0 on end # 8086 22c0 - SIO - DMA + device pci 18.1 on end # 8086 22c1 - I2C Port 1 + device pci 18.2 on end # 8086 22c2 - I2C Port 2 + device pci 18.3 off end # 8086 22c3 - I2C Port 3 + device pci 18.4 off end # 8086 22c4 - I2C Port 4 + device pci 18.5 off end # 8086 22c5 - I2C Port 5 + device pci 18.6 off end # 8086 22c6 - I2C Port 6 + device pci 18.7 off end # 8086 22c7 - I2C Port 7 + device pci 1a.0 on end # 8086 2298 - Trusted Execution Engine + device pci 1b.0 on end # 8086 2284 - HD Audio + device pci 1c.0 on end # 8086 22c8 - PCIe Root Port 1 + device pci 1c.1 on end # 8086 22ca - PCIe Root Port 2 + device pci 1c.2 on end # 8086 22cc - PCIe Root Port 3 + device pci 1c.3 on end # 8086 22ce - PCIe Root Port 4 + device pci 1e.0 on end # 8086 2286 - SIO - DMA + device pci 1e.3 off end # 8086 228a - HSUART 1 + device pci 1e.4 off end # 8086 228c - HSUART 2 + device pci 1f.0 on # 8086 229c - LPC bridge + chip superio/ite/it8613e + device pnp 2e.0 off end + device pnp 2e.1 on # COM 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 off # Environment Controller + end + device pnp 2e.5 off # Keyboard + end + device pnp 2e.6 off # Mouse + end + device pnp 2e.7 off # GPIO + end + device pnp 2e.a off # CIR + end + end + end + device pci 1f.3 on end # 8086 2292 - SMBus 0 + end +end diff --git a/src/mainboard/protectli/vault/variants/fw4b/devicetree.cb b/src/mainboard/protectli/vault/variants/fw4b/devicetree.cb new file mode 100644 index 0000000..1fd5c0c --- /dev/null +++ b/src/mainboard/protectli/vault/variants/fw4b/devicetree.cb @@ -0,0 +1,146 @@ +chip soc/intel/braswell + + ############################################################ + # Set the parameters for MemoryInit + ############################################################ + + register "PcdMrcInitTsegSize" = "8" # SMM Region size in MiB + + register "PcdMrcInitMmioSize" = "0x0800" + register "PcdMrcInitSpdAddr1" = "0xa0" + register "PcdMrcInitSpdAddr2" = "0xa2" + register "PcdIgdDvmt50PreAlloc" = "1" + register "PcdApertureSize" = "2" + register "PcdGttSize" = "1" + register "PcdDvfsEnable" = "0" + register "PcdCaMirrorEn" = "1" + + ############################################################ + # Set the parameters for SiliconInit + ############################################################ + + register "PcdSdcardMode" = "PCH_DISABLED" + register "PcdEnableHsuart0" = "0" + register "PcdEnableHsuart1" = "0" + register "PcdEnableAzalia" = "1" + register "PcdEnableXhci" = "1" + register "PcdEnableLpe" = "1" + register "PcdEnableDma0" = "1" + register "PcdEnableDma1" = "1" + register "PcdEnableI2C0" = "1" + register "PcdEnableI2C1" = "1" + register "PcdEnableI2C2" = "0" + register "PcdEnableI2C3" = "0" + register "PcdEnableI2C4" = "0" + register "PcdEnableI2C5" = "0" + register "PcdEnableI2C6" = "0" + register "PunitPwrConfigDisable" = "0" # Enable SVID + register "ChvSvidConfig" = "3" + register "PcdEmmcMode" = "PCH_DISABLED" + register "PcdUsb3ClkSsc" = "1" + register "PcdDispClkSsc" = "1" + register "PcdSataClkSsc" = "1" + register "PcdEnableSata" = "1" + register "Usb2Port0PerPortPeTxiSet" = "7" + register "Usb2Port0PerPortTxiSet" = "6" + register "Usb2Port0IUsbTxEmphasisEn" = "3" + register "Usb2Port0PerPortTxPeHalf" = "1" + register "Usb2Port1PerPortPeTxiSet" = "7" + register "Usb2Port1PerPortTxiSet" = "6" + register "Usb2Port1IUsbTxEmphasisEn" = "3" + register "Usb2Port1PerPortTxPeHalf" = "1" + register "Usb2Port2PerPortPeTxiSet" = "7" + register "Usb2Port2PerPortTxiSet" = "6" + register "Usb2Port2IUsbTxEmphasisEn" = "3" + register "Usb2Port2PerPortTxPeHalf" = "1" + register "Usb2Port3PerPortPeTxiSet" = "7" + register "Usb2Port3PerPortTxiSet" = "6" + register "Usb2Port3IUsbTxEmphasisEn" = "3" + register "Usb2Port3PerPortTxPeHalf" = "1" + register "Usb2Port4PerPortPeTxiSet" = "7" + register "Usb2Port4PerPortTxiSet" = "6" + register "Usb2Port4IUsbTxEmphasisEn" = "3" + register "Usb2Port4PerPortTxPeHalf" = "1" + register "Usb3Lane0Ow2tapgen2deemph3p5" = "0x3a" + register "Usb3Lane1Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane2Ow2tapgen2deemph3p5" = "0x64" + register "Usb3Lane3Ow2tapgen2deemph3p5" = "0x3a" + register "PcdSataInterfaceSpeed" = "3" + register "PcdPchSsicEnable" = "0" + register "PcdPchUsbSsicPort" = "0" + register "PcdPchUsbHsicPort" = "0" + register "PcdRtcLock" = "0" # Disable RTC access locking to NVRAM + register "PMIC_I2CBus" = "0" + register "ISPEnable" = "0" # Disable IUNIT + register "ISPPciDevConfig" = "3" + register "PcdSdDetectChk" = "0" # Disable SD card detect + register "DptfDisable" = "1" + + # LPE audio codec settings + register "lpe_codec_clk_src" = "LPE_CLK_SRC_PLL" # 19.2MHz clock + + # Disable devices in ACPI mode + register "lpss_acpi_mode" = "0" + register "emmc_acpi_mode" = "0" + register "sd_acpi_mode" = "0" + register "lpe_acpi_mode" = "0" + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # 8086 2280 - SoC transaction router + device pci 02.0 on end # 8086 22b0/22b1 - B1/C0 stepping Graphics and Display + device pci 03.0 off end # 8086 22b8 - Camera and Image Processor + device pci 0b.0 off end # 8086 22dc - PUNIT/DPTF + device pci 10.0 off end # 8086 2294 - MMC Port + device pci 12.0 off end # 8086 2296 - SD Port + device pci 13.0 on end # 8086 22a3 - Sata controller + device pci 14.0 on end # 8086 22b5 - USB XHCI + device pci 15.0 on end # 8086 22a8 - LP Engine Audio + device pci 16.0 off end # 8086 22b7 - USB device + device pci 18.0 on end # 8086 22c0 - SIO - DMA + device pci 18.1 on end # 8086 22c1 - I2C Port 1 + device pci 18.2 on end # 8086 22c2 - I2C Port 2 + device pci 18.3 off end # 8086 22c3 - I2C Port 3 + device pci 18.4 off end # 8086 22c4 - I2C Port 4 + device pci 18.5 off end # 8086 22c5 - I2C Port 5 + device pci 18.6 off end # 8086 22c6 - I2C Port 6 + device pci 18.7 off end # 8086 22c7 - I2C Port 7 + device pci 1a.0 on end # 8086 2298 - Trusted Execution Engine + device pci 1b.0 on end # 8086 2284 - HD Audio + device pci 1c.0 on end # 8086 22c8 - PCIe Root Port 1 + device pci 1c.1 on end # 8086 22ca - PCIe Root Port 2 + device pci 1c.2 on end # 8086 22cc - PCIe Root Port 3 + device pci 1c.3 on end # 8086 22ce - PCIe Root Port 4 + device pci 1e.0 on end # 8086 2286 - SIO - DMA + device pci 1e.3 off end # 8086 228a - HSUART 1 + device pci 1e.4 off end # 8086 228c - HSUART 2 + device pci 1f.0 on # 8086 229c - LPC bridge + chip superio/ite/it8613e + device pnp 2e.0 off end + device pnp 2e.1 on # COM 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 off # Environment Controller + end + device pnp 2e.5 off # Keyboard + end + device pnp 2e.6 off # Mouse + end + device pnp 2e.7 off # GPIO + end + device pnp 2e.a off # CIR + end + end + end + device pci 1f.3 on end # 8086 2292 - SMBus 0 + end +end -- To view, visit https://review.coreboot.org/c/coreboot/+/32076 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I553fd3a89299314a855f055014ca7645100e12e7 Gerrit-Change-Number: 32076 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

8 51

Change in ...coreboot[master]: mb/lenovo/*: Add support for VBOOT on 12MiB devices
by Patrick Rudolph (Code Review) 06 Mar '20

06 Mar '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32617 Change subject: mb/lenovo/*: Add support for VBOOT on 12MiB devices ...................................................................... mb/lenovo/*: Add support for VBOOT on 12MiB devices Enable VBOOT support on all devices that have a 8 MiB flash, using a single RW_MAIN_A partition, allowing the use of tianocore payload in both RW_MAIN_A and WP_RO. * Add VBNV section to cmos.layout * Add FMAP for VBOOT and regular boot * Select Kconfigs for VBOOT * Enable VBOOT_SLOTS_RW_A by default Untested. Change-Id: I8a35a06ece1e9d57a2ef23970e61ae26fafce543 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/lenovo/t430/Kconfig A src/mainboard/lenovo/t430/board.fmd M src/mainboard/lenovo/t430/cmos.layout A src/mainboard/lenovo/t430/vboot-rwa.fmd M src/mainboard/lenovo/t430s/Kconfig A src/mainboard/lenovo/t430s/board.fmd M src/mainboard/lenovo/t430s/cmos.layout A src/mainboard/lenovo/t430s/vboot-rwa.fmd M src/mainboard/lenovo/t530/Kconfig A src/mainboard/lenovo/t530/board.fmd M src/mainboard/lenovo/t530/cmos.layout A src/mainboard/lenovo/t530/vboot-rwa.fmd M src/mainboard/lenovo/x131e/Kconfig A src/mainboard/lenovo/x131e/board.fmd M src/mainboard/lenovo/x131e/cmos.layout A src/mainboard/lenovo/x131e/vboot-rwa.fmd M src/mainboard/lenovo/x1_carbon_gen1/Kconfig A src/mainboard/lenovo/x1_carbon_gen1/board.fmd M src/mainboard/lenovo/x1_carbon_gen1/cmos.layout A src/mainboard/lenovo/x1_carbon_gen1/vboot-rwa.fmd M src/mainboard/lenovo/x230/Kconfig A src/mainboard/lenovo/x230/board.fmd M src/mainboard/lenovo/x230/cmos.layout A src/mainboard/lenovo/x230/vboot-rwa.fmd 24 files changed, 408 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/32617/1 diff --git a/src/mainboard/lenovo/t430/Kconfig b/src/mainboard/lenovo/t430/Kconfig index dbeaadb..fdccd66 100644 --- a/src/mainboard/lenovo/t430/Kconfig +++ b/src/mainboard/lenovo/t430/Kconfig @@ -26,6 +26,21 @@ select INTEL_GMA_HAVE_VBT select MAINBOARD_USES_IFD_GBE_REGION +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_AB + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + config MAINBOARD_DIR string default lenovo/t430 diff --git a/src/mainboard/lenovo/t430/board.fmd b/src/mainboard/lenovo/t430/board.fmd new file mode 100644 index 0000000..9180e12 --- /dev/null +++ b/src/mainboard/lenovo/t430/board.fmd @@ -0,0 +1,16 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_MRC_CACHE@0 0x10000 + SMMSTORE(PRESERVE)@0x10000 0x40000 + + WP_RO@0x50000 0x6a0000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x1000 0x69f000 + } + } +} diff --git a/src/mainboard/lenovo/t430/cmos.layout b/src/mainboard/lenovo/t430/cmos.layout index 1b50e7f..f9757f0 100644 --- a/src/mainboard/lenovo/t430/cmos.layout +++ b/src/mainboard/lenovo/t430/cmos.layout @@ -80,6 +80,9 @@ #437 3 r 0 unused 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/t430/vboot-rwa.fmd b/src/mainboard/lenovo/t430/vboot-rwa.fmd new file mode 100644 index 0000000..58eb9e3 --- /dev/null +++ b/src/mainboard/lenovo/t430/vboot-rwa.fmd @@ -0,0 +1,34 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_SECTION_A@0x00000 0x280000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x16ffc0 + RW_FWID_A@0x17ffc0 0x40 + } + RW_SECTION_B@0x280000 0x280000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x16ffc0 + RW_FWID_B@0x17ffc0 0x40 + } + UNIFIED_MRC_CACHE@0x500000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x520000 0x1000 + SMMSTORE(PRESERVE)@0x521000 0x40000 + + WP_RO@0x581000 0x17f000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_PADDING@0x840 0x7c0 + RO_VPD(PRESERVE)@0x1000 0x1000 + GBB@0x2000 0x1e000 + COREBOOT(CBFS)@0x20000 0x15f000 + } + } +} diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index bad1837..a56f577 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -26,6 +26,21 @@ # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_AB + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + config MAINBOARD_DIR string default lenovo/t430s diff --git a/src/mainboard/lenovo/t430s/board.fmd b/src/mainboard/lenovo/t430s/board.fmd new file mode 100644 index 0000000..9180e12 --- /dev/null +++ b/src/mainboard/lenovo/t430s/board.fmd @@ -0,0 +1,16 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_MRC_CACHE@0 0x10000 + SMMSTORE(PRESERVE)@0x10000 0x40000 + + WP_RO@0x50000 0x6a0000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x1000 0x69f000 + } + } +} diff --git a/src/mainboard/lenovo/t430s/cmos.layout b/src/mainboard/lenovo/t430s/cmos.layout index 97d97ed..891a294 100644 --- a/src/mainboard/lenovo/t430s/cmos.layout +++ b/src/mainboard/lenovo/t430s/cmos.layout @@ -80,6 +80,9 @@ #436 4 r 0 unused 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/t430s/vboot-rwa.fmd b/src/mainboard/lenovo/t430s/vboot-rwa.fmd new file mode 100644 index 0000000..58eb9e3 --- /dev/null +++ b/src/mainboard/lenovo/t430s/vboot-rwa.fmd @@ -0,0 +1,34 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_SECTION_A@0x00000 0x280000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x16ffc0 + RW_FWID_A@0x17ffc0 0x40 + } + RW_SECTION_B@0x280000 0x280000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x16ffc0 + RW_FWID_B@0x17ffc0 0x40 + } + UNIFIED_MRC_CACHE@0x500000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x520000 0x1000 + SMMSTORE(PRESERVE)@0x521000 0x40000 + + WP_RO@0x581000 0x17f000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_PADDING@0x840 0x7c0 + RO_VPD(PRESERVE)@0x1000 0x1000 + GBB@0x2000 0x1e000 + COREBOOT(CBFS)@0x20000 0x15f000 + } + } +} diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index b36460d..df011e4 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -27,6 +27,21 @@ if BOARD_LENOVO_BASEBOARD_T530 +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_AB + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + config VARIANT_DIR string default "t530" if BOARD_LENOVO_T530 diff --git a/src/mainboard/lenovo/t530/board.fmd b/src/mainboard/lenovo/t530/board.fmd new file mode 100644 index 0000000..9180e12 --- /dev/null +++ b/src/mainboard/lenovo/t530/board.fmd @@ -0,0 +1,16 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_MRC_CACHE@0 0x10000 + SMMSTORE(PRESERVE)@0x10000 0x40000 + + WP_RO@0x50000 0x6a0000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x1000 0x69f000 + } + } +} diff --git a/src/mainboard/lenovo/t530/cmos.layout b/src/mainboard/lenovo/t530/cmos.layout index 3400a4d..0c8c546 100644 --- a/src/mainboard/lenovo/t530/cmos.layout +++ b/src/mainboard/lenovo/t530/cmos.layout @@ -81,6 +81,9 @@ 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/t530/vboot-rwa.fmd b/src/mainboard/lenovo/t530/vboot-rwa.fmd new file mode 100644 index 0000000..58eb9e3 --- /dev/null +++ b/src/mainboard/lenovo/t530/vboot-rwa.fmd @@ -0,0 +1,34 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_SECTION_A@0x00000 0x280000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x16ffc0 + RW_FWID_A@0x17ffc0 0x40 + } + RW_SECTION_B@0x280000 0x280000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x16ffc0 + RW_FWID_B@0x17ffc0 0x40 + } + UNIFIED_MRC_CACHE@0x500000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x520000 0x1000 + SMMSTORE(PRESERVE)@0x521000 0x40000 + + WP_RO@0x581000 0x17f000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_PADDING@0x840 0x7c0 + RO_VPD(PRESERVE)@0x1000 0x1000 + GBB@0x2000 0x1e000 + COREBOOT(CBFS)@0x20000 0x15f000 + } + } +} diff --git a/src/mainboard/lenovo/x131e/Kconfig b/src/mainboard/lenovo/x131e/Kconfig index e7da8d0..3da7b3b 100644 --- a/src/mainboard/lenovo/x131e/Kconfig +++ b/src/mainboard/lenovo/x131e/Kconfig @@ -21,6 +21,21 @@ select SERIRQ_CONTINUOUS_MODE select INTEL_GMA_HAVE_VBT +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_AB + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + config MAINBOARD_DIR string default lenovo/x131e diff --git a/src/mainboard/lenovo/x131e/board.fmd b/src/mainboard/lenovo/x131e/board.fmd new file mode 100644 index 0000000..9180e12 --- /dev/null +++ b/src/mainboard/lenovo/x131e/board.fmd @@ -0,0 +1,16 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_MRC_CACHE@0 0x10000 + SMMSTORE(PRESERVE)@0x10000 0x40000 + + WP_RO@0x50000 0x6a0000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x1000 0x69f000 + } + } +} diff --git a/src/mainboard/lenovo/x131e/cmos.layout b/src/mainboard/lenovo/x131e/cmos.layout index 93c74fb..41b8354 100644 --- a/src/mainboard/lenovo/x131e/cmos.layout +++ b/src/mainboard/lenovo/x131e/cmos.layout @@ -79,6 +79,9 @@ 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/x131e/vboot-rwa.fmd b/src/mainboard/lenovo/x131e/vboot-rwa.fmd new file mode 100644 index 0000000..58eb9e3 --- /dev/null +++ b/src/mainboard/lenovo/x131e/vboot-rwa.fmd @@ -0,0 +1,34 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_SECTION_A@0x00000 0x280000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x16ffc0 + RW_FWID_A@0x17ffc0 0x40 + } + RW_SECTION_B@0x280000 0x280000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x16ffc0 + RW_FWID_B@0x17ffc0 0x40 + } + UNIFIED_MRC_CACHE@0x500000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x520000 0x1000 + SMMSTORE(PRESERVE)@0x521000 0x40000 + + WP_RO@0x581000 0x17f000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_PADDING@0x840 0x7c0 + RO_VPD(PRESERVE)@0x1000 0x1000 + GBB@0x2000 0x1e000 + COREBOOT(CBFS)@0x20000 0x15f000 + } + } +} diff --git a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig index 520853c..29060d9 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/Kconfig +++ b/src/mainboard/lenovo/x1_carbon_gen1/Kconfig @@ -26,6 +26,21 @@ # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_AB + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + config MAINBOARD_DIR string default lenovo/x1_carbon_gen1 diff --git a/src/mainboard/lenovo/x1_carbon_gen1/board.fmd b/src/mainboard/lenovo/x1_carbon_gen1/board.fmd new file mode 100644 index 0000000..9180e12 --- /dev/null +++ b/src/mainboard/lenovo/x1_carbon_gen1/board.fmd @@ -0,0 +1,16 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_MRC_CACHE@0 0x10000 + SMMSTORE(PRESERVE)@0x10000 0x40000 + + WP_RO@0x50000 0x6a0000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x1000 0x69f000 + } + } +} diff --git a/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout b/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout index bb25261..55a8a58 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout +++ b/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout @@ -80,6 +80,9 @@ 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/x1_carbon_gen1/vboot-rwa.fmd b/src/mainboard/lenovo/x1_carbon_gen1/vboot-rwa.fmd new file mode 100644 index 0000000..58eb9e3 --- /dev/null +++ b/src/mainboard/lenovo/x1_carbon_gen1/vboot-rwa.fmd @@ -0,0 +1,34 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_SECTION_A@0x00000 0x280000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x16ffc0 + RW_FWID_A@0x17ffc0 0x40 + } + RW_SECTION_B@0x280000 0x280000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x16ffc0 + RW_FWID_B@0x17ffc0 0x40 + } + UNIFIED_MRC_CACHE@0x500000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x520000 0x1000 + SMMSTORE(PRESERVE)@0x521000 0x40000 + + WP_RO@0x581000 0x17f000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_PADDING@0x840 0x7c0 + RO_VPD(PRESERVE)@0x1000 0x1000 + GBB@0x2000 0x1e000 + COREBOOT(CBFS)@0x20000 0x15f000 + } + } +} diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 5b34b83..e7d7720 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -27,6 +27,21 @@ # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE +config VBOOT + select VBOOT_VBNV_CMOS + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select HAS_RECOVERY_MRC_CACHE + +config VBOOT_SLOTS_RW_AB + default y + +config VBOOT_VBNV_OFFSET + hex + default 0x2a + config MAINBOARD_DIR string default lenovo/x230 diff --git a/src/mainboard/lenovo/x230/board.fmd b/src/mainboard/lenovo/x230/board.fmd new file mode 100644 index 0000000..9180e12 --- /dev/null +++ b/src/mainboard/lenovo/x230/board.fmd @@ -0,0 +1,16 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_MRC_CACHE@0 0x10000 + SMMSTORE(PRESERVE)@0x10000 0x40000 + + WP_RO@0x50000 0x6a0000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x1000 0x69f000 + } + } +} diff --git a/src/mainboard/lenovo/x230/cmos.layout b/src/mainboard/lenovo/x230/cmos.layout index 27197fb..9903400 100644 --- a/src/mainboard/lenovo/x230/cmos.layout +++ b/src/mainboard/lenovo/x230/cmos.layout @@ -80,6 +80,9 @@ 440 8 h 0 volume +# VBOOT +448 128 r 0 vbnv + # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 diff --git a/src/mainboard/lenovo/x230/vboot-rwa.fmd b/src/mainboard/lenovo/x230/vboot-rwa.fmd new file mode 100644 index 0000000..58eb9e3 --- /dev/null +++ b/src/mainboard/lenovo/x230/vboot-rwa.fmd @@ -0,0 +1,34 @@ +FLASH@0xff400000 0xc00000 { + SI_ALL@0x0 0x500000 { + SI_DESC@0x0 0x1000 + SI_GBE@0x1000 0x2000 + SI_ME@0x3000 0x4ed000 + } + SI_BIOS@0x500000 0x700000 { + RW_SECTION_A@0x00000 0x280000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x16ffc0 + RW_FWID_A@0x17ffc0 0x40 + } + RW_SECTION_B@0x280000 0x280000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x16ffc0 + RW_FWID_B@0x17ffc0 0x40 + } + UNIFIED_MRC_CACHE@0x500000 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_VPD(PRESERVE)@0x520000 0x1000 + SMMSTORE(PRESERVE)@0x521000 0x40000 + + WP_RO@0x581000 0x17f000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_PADDING@0x840 0x7c0 + RO_VPD(PRESERVE)@0x1000 0x1000 + GBB@0x2000 0x1e000 + COREBOOT(CBFS)@0x20000 0x15f000 + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32617 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a35a06ece1e9d57a2ef23970e61ae26fafce543 Gerrit-Change-Number: 32617 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

10 32

Change in ...coreboot[master]: soc/intel/denverton_ns: Allow using FSP repo
by Felix Singer (Code Review) 04 Mar '20

04 Mar '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30931 Change subject: soc/intel/denverton_ns: Allow using FSP repo ...................................................................... soc/intel/denverton_ns: Allow using FSP repo Change-Id: I615305da5865bef305f560f5c90482cf0937b25a Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M src/drivers/intel/fsp2_0/Kconfig M src/soc/intel/denverton_ns/Kconfig 2 files changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/30931/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 8156d18..6f5ed2a 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -85,7 +85,8 @@ bool "Use the IntelFSP based binaries" depends on ADD_FSP_BINARIES depends on SOC_INTEL_APOLLOLAKE || SOC_INTEL_SKYLAKE || \ - SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE + SOC_INTEL_KABYLAKE || SOC_INTEL_COFFEELAKE || \ + SOC_INTEL_DENVERTON_NS help When selecting this option, the SoC must set FSP_HEADER_PATH and FSP_FD_PATH correctly so FSP splitting works. diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 1096549..dfb5c37 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -78,6 +78,16 @@ help The memory location of the Intel FSP-S binary for this platform. +config FSP_HEADER_PATH + string "Location of FSP headers" + depends on MAINBOARD_USES_FSP2_0 + default "3rdparty/fsp/DenvertonNSFspBinPkg/Include/" + +config FSP_FD_PATH + string + depends on FSP_USE_REPO + default "3rdparty/fsp/DenvertonNSFspBinPkg/FspBin/DenvertonNSFsp.fd" + # CAR memory layout on DENVERTON_NS hardware: ## CAR base address - 0xfef00000 ## CAR size 1MB - 0x100 (0xfff00) -- To view, visit https://review.coreboot.org/c/coreboot/+/30931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I615305da5865bef305f560f5c90482cf0937b25a Gerrit-Change-Number: 30931 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <migy(a)darmstadt.ccc.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: README: Spell Web site with one space
by Paul Menzel (Code Review) 03 Mar '20

03 Mar '20

Paul Menzel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31384 Change subject: README: Spell Web site with one space ...................................................................... README: Spell Web site with one space Change-Id: I4119ae6df01dbafb60b2a132c887844739839de6 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- M payloads/libpayload/README 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/31384/1 diff --git a/payloads/libpayload/README b/payloads/libpayload/README index fdf9b18..7348934 100644 --- a/payloads/libpayload/README +++ b/payloads/libpayload/README @@ -49,10 +49,10 @@ Please see the sample/ directory for details. -Website and Mailing List +Web site and Mailing List ------------------------ -The main website is https://www.coreboot.org/Libpayload. +The main web site is https://www.coreboot.org/Libpayload. For additional information, patches, and discussions, please join the coreboot mailing list at https://www.coreboot.org/Mailinglist, where most -- To view, visit https://review.coreboot.org/c/coreboot/+/31384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4119ae6df01dbafb60b2a132c887844739839de6 Gerrit-Change-Number: 31384 Gerrit-PatchSet: 1 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/chromeos: Add unzip as a dependency
by Mete Balci (Code Review) 03 Mar '20

03 Mar '20

Mete Balci has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31821 Change subject: util/chromeos: Add unzip as a dependency ...................................................................... util/chromeos: Add unzip as a dependency unzip might not be installed by default, so it is added as a dependency in crosfirmware script. Change-Id: I420067b3e8ed26e6a7dccb863aae1272a3c7acbc Signed-off-by: Mete Balci <metebalci(a)gmail.com> --- M util/chromeos/crosfirmware.sh 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/31821/1 diff --git a/util/chromeos/crosfirmware.sh b/util/chromeos/crosfirmware.sh index 9d2ca84..0564106 100755 --- a/util/chromeos/crosfirmware.sh +++ b/util/chromeos/crosfirmware.sh @@ -37,6 +37,7 @@ exit_if_uninstalled "debugfs" "e2fsprogs" exit_if_uninstalled "parted" "parted" exit_if_uninstalled "curl" "curl" + exit_if_uninstalled "unzip" "unzip" } get_inventory() -- To view, visit https://review.coreboot.org/c/coreboot/+/31821 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I420067b3e8ed26e6a7dccb863aae1272a3c7acbc Gerrit-Change-Number: 31821 Gerrit-PatchSet: 1 Gerrit-Owner: Mete Balci <metebalci(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: clang-format: set to 80 chars per line
by Philipp Deppenwiese (Code Review) 03 Mar '20

03 Mar '20

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31947 Change subject: clang-format: set to 80 chars per line ...................................................................... clang-format: set to 80 chars per line Change-Id: If785ff5eb5cbadab92b0c2fed67a202b6d0ed5d4 Signed-off-by: zaolin <zaolin.daisuki(a)gmail.com> --- M .clang-format 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/31947/1 diff --git a/.clang-format b/.clang-format index d853f50..c292e2f 100644 --- a/.clang-format +++ b/.clang-format @@ -7,7 +7,7 @@ IndentCaseLabels: false SortIncludes: false ContinuationIndentWidth: 8 -ColumnLimit: 0 +ColumnLimit: 80 AlwaysBreakBeforeMultilineStrings: true AllowShortLoopsOnASingleLine: false AllowShortFunctionsOnASingleLine: false -- To view, visit https://review.coreboot.org/c/coreboot/+/31947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If785ff5eb5cbadab92b0c2fed67a202b6d0ed5d4 Gerrit-Change-Number: 31947 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newchange

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