coreboot-gerrit May 2019

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Change in ...coreboot[master]: src/soc/intel/fsp_baytrail/smm.c: add bootstate entry for locking SMI
by Michał Żygowski (Code Review) 14 Oct '19

14 Oct '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30753 Change subject: src/soc/intel/fsp_baytrail/smm.c: add bootstate entry for locking SMI ...................................................................... src/soc/intel/fsp_baytrail/smm.c: add bootstate entry for locking SMI Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: Ia296a680217a38136c063cae6ed619df0c497795 --- M src/soc/intel/fsp_baytrail/smm.c 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/30753/1 diff --git a/src/soc/intel/fsp_baytrail/smm.c b/src/soc/intel/fsp_baytrail/smm.c index 84f8d28..149272d 100644 --- a/src/soc/intel/fsp_baytrail/smm.c +++ b/src/soc/intel/fsp_baytrail/smm.c @@ -20,6 +20,7 @@ #include <arch/io.h> #include <cpu/x86/smm.h> #include <string.h> +#include <bootstate.h> #include <soc/iomap.h> #include <soc/pmc.h> @@ -124,3 +125,16 @@ "d" (APM_CNT) ); } + +static void finalize_chipset(void *unused) +{ + printk(BIOS_DEBUG, "Finalizing SMM.\n"); + /* Lock sleep stretching policy and set SMI lock. */ + write32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2), + read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2)) + | SLPSX_STR_POL_LOCK | SMI_LOCK); + outb(APM_CNT_FINALIZE, APM_CNT); +} + +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, finalize_chipset, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/30753 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia296a680217a38136c063cae6ed619df0c497795 Gerrit-Change-Number: 30753 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/skylake: Use common cpu/intel/car romstage entry
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33019 Change subject: soc/intel/skylake: Use common cpu/intel/car romstage entry ...................................................................... soc/intel/skylake: Use common cpu/intel/car romstage entry Change-Id: I2575bf325e94755921cc9caa6118cd92847f944a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/skylake/romstage/Makefile.inc M src/soc/intel/skylake/romstage/romstage_fsp20.c 2 files changed, 10 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/33019/1 diff --git a/src/soc/intel/skylake/romstage/Makefile.inc b/src/soc/intel/skylake/romstage/Makefile.inc index e929eba..7bb9d4b 100644 --- a/src/soc/intel/skylake/romstage/Makefile.inc +++ b/src/soc/intel/skylake/romstage/Makefile.inc @@ -1,4 +1,4 @@ -romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += ../../../../cpu/intel/car/romstage.c +romstage-y += ../../../../cpu/intel/car/romstage.c romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += romstage.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage_fsp20.c romstage-y += systemagent.c diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 96937d6..7eebc3a 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -17,6 +17,7 @@ #include <arch/early_variables.h> #include <arch/symbols.h> #include <assert.h> +#include <cpu/intel/romstage.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cbmem.h> @@ -135,25 +136,27 @@ printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); } -asmlinkage void car_stage_entry(void) +void mainboard_romstage_entry(unsigned long bist) { bool s3wake; - struct postcar_frame pcf; - uintptr_t top_of_ram; struct chipset_power_state *ps; - console_init(); - /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); ps = pmc_get_power_state(); - timestamp_add_now(TS_START_ROMSTAGE); s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); pmc_set_disb(); if (!s3wake) save_dimm_info(); +} + +void platform_enter_postcar(void) +{ + uintptr_t top_of_ram; + struct postcar_frame pcf; + if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/33019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2575bf325e94755921cc9caa6118cd92847f944a Gerrit-Change-Number: 33019 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [UNTESTED]drivers/pc80/rtc: Cache CMOS option table in CBMEM
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33058 Change subject: [UNTESTED]drivers/pc80/rtc: Cache CMOS option table in CBMEM ...................................................................... [UNTESTED]drivers/pc80/rtc: Cache CMOS option table in CBMEM Fetching the option table from cbfs each time is slowing things down and adds a vulnerability during S3 resume. Change-Id: I9f9001fd0090fd1b56ee518d426aa3d3025dba59 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/commonlib/include/commonlib/cbmem_id.h M src/drivers/pc80/rtc/mc146818rtc.c 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/33058/1 diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 535ba33..5ef8506 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -25,6 +25,7 @@ #define CBMEM_ID_CAR_GLOBALS 0xcac4e6a3 #define CBMEM_ID_CBTABLE 0x43425442 #define CBMEM_ID_CBTABLE_FWD 0x43425443 +#define CBMEM_ID_CMOS_TABLE 0x366f1abb #define CBMEM_ID_CONSOLE 0x434f4e53 #define CBMEM_ID_COVERAGE 0x47434f56 #define CBMEM_ID_EHCI_DEBUG 0xe4c1deb9 @@ -88,6 +89,7 @@ { CBMEM_ID_CAR_GLOBALS, "CAR GLOBALS" }, \ { CBMEM_ID_CBTABLE, "COREBOOT " }, \ { CBMEM_ID_CBTABLE_FWD, "COREBOOTFWD" }, \ + { CBMEM_ID_CMOS_TABLE, "CMOS " }, \ { CBMEM_ID_CONSOLE, "CONSOLE " }, \ { CBMEM_ID_COVERAGE, "COVERAGE " }, \ { CBMEM_ID_EHCI_DEBUG, "USBDEBUG " }, \ diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 3667354..ee16cf1 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -18,6 +18,7 @@ #include <arch/acpi.h> #include <arch/io.h> #include <bcd.h> +#include <cbmem.h> #include <fallback.h> #include <stdint.h> #include <version.h> @@ -272,6 +273,15 @@ static enum cb_err get_layout(struct cmos_option_table *ct) { +#if !(defined(__PRE_RAM__) || ENV_SMM) + struct cmos_option_table *table; + table = cbmem_find(CBMEM_ID_CMOS_TABLE); + if (table) { + ct = table; + return CB_SUCCESS; + } +#endif + LOCK_NVRAM_CBFS_SPINLOCK(); if (locate_cmos_layout(&rdev) != CB_SUCCESS) { @@ -286,6 +296,14 @@ UNLOCK_NVRAM_CBFS_SPINLOCK(); return CB_CMOS_LAYOUT_NOT_FOUND; } +#if !(defined(__PRE_RAM__) || ENV_SMM) + table = cbmem_add(CBMEM_ID_CMOS_TABLE, region_device_sz(&rdev)); + if (table) { + memcpy(table, ct, region_device_sz(&rdev)); + ct = table; + } +#endif + return CB_SUCCESS; } -- To view, visit https://review.coreboot.org/c/coreboot/+/33058 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f9001fd0090fd1b56ee518d426aa3d3025dba59 Gerrit-Change-Number: 33058 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/pc80/rtc: Move fetching and cleaning up the layout
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33057 Change subject: drivers/pc80/rtc: Move fetching and cleaning up the layout ...................................................................... drivers/pc80/rtc: Move fetching and cleaning up the layout Both get_option and set_option need to fetch the layout and clean up afterwards. Do this in a common location. Change-Id: I0623738838c62f49e9a8d93a34f01a509ef1f9cb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/drivers/pc80/rtc/mc146818rtc.c 1 file changed, 39 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/33057/1 diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 6e37cd2..3667354 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -268,22 +268,12 @@ return CB_SUCCESS; } -enum cb_err get_option(void *dest, const char *name) +struct region_device rdev; + +static enum cb_err get_layout(struct cmos_option_table *ct) { - struct cmos_option_table *ct; - struct region_device rdev; - struct cmos_entries *ce; - size_t namelen; - int found = 0; - - if (!CONFIG(USE_OPTION_TABLE)) - return CB_CMOS_OTABLE_DISABLED; - LOCK_NVRAM_CBFS_SPINLOCK(); - /* Figure out how long name is */ - namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - if (locate_cmos_layout(&rdev) != CB_SUCCESS) { UNLOCK_NVRAM_CBFS_SPINLOCK(); return CB_CMOS_LAYOUT_NOT_FOUND; @@ -296,6 +286,32 @@ UNLOCK_NVRAM_CBFS_SPINLOCK(); return CB_CMOS_LAYOUT_NOT_FOUND; } + return CB_SUCCESS; +} + +static void clean_up_layout(struct cmos_option_table *ct) +{ + rdev_munmap(&rdev, ct); + UNLOCK_NVRAM_CBFS_SPINLOCK(); +} + +enum cb_err get_option(void *dest, const char *name) +{ + struct cmos_option_table *ct = NULL;; + struct cmos_entries *ce; + size_t namelen; + int found = 0; + + if (!CONFIG(USE_OPTION_TABLE)) + return CB_CMOS_OTABLE_DISABLED; + + LOCK_NVRAM_CBFS_SPINLOCK(); + + /* Figure out how long name is */ + namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); + + if (get_layout(ct) != CB_SUCCESS) + return CB_CMOS_LAYOUT_NOT_FOUND; /* find the requested entry record */ ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); @@ -308,23 +324,19 @@ } if (!found) { printk(BIOS_DEBUG, "No CMOS option '%s'.\n", name); - rdev_munmap(&rdev, ct); - UNLOCK_NVRAM_CBFS_SPINLOCK(); + clean_up_layout(ct); return CB_CMOS_OPTION_NOT_FOUND; } if (!cmos_checksum_valid(LB_CKS_RANGE_START, LB_CKS_RANGE_END, LB_CKS_LOC)) { - rdev_munmap(&rdev, ct); - UNLOCK_NVRAM_CBFS_SPINLOCK(); + clean_up_layout(ct); return CB_CMOS_CHECKSUM_INVALID; } if (get_cmos_value(ce->bit, ce->length, dest) != CB_SUCCESS) { - rdev_munmap(&rdev, ct); - UNLOCK_NVRAM_CBFS_SPINLOCK(); + clean_up_layout(ct); return CB_CMOS_ACCESS_ERROR; } - rdev_munmap(&rdev, ct); - UNLOCK_NVRAM_CBFS_SPINLOCK(); + clean_up_layout(ct); return CB_SUCCESS; } @@ -383,8 +395,7 @@ enum cb_err set_option(const char *name, void *value) { - struct cmos_option_table *ct; - struct region_device rdev; + struct cmos_option_table *ct = NULL; struct cmos_entries *ce; unsigned long length; size_t namelen; @@ -396,18 +407,8 @@ /* Figure out how long name is */ namelen = strnlen(name, CMOS_MAX_NAME_LENGTH); - if (locate_cmos_layout(&rdev) != CB_SUCCESS) { - UNLOCK_NVRAM_CBFS_SPINLOCK(); + if (get_layout(ct) != CB_SUCCESS) return CB_CMOS_LAYOUT_NOT_FOUND; - } - ct = rdev_mmap_full(&rdev); - if (!ct) { - printk(BIOS_ERR, "RTC: cmos_layout.bin could not be mapped. " - "Options are disabled\n"); - - UNLOCK_NVRAM_CBFS_SPINLOCK(); - return CB_CMOS_LAYOUT_NOT_FOUND; - } /* find the requested entry record */ ce = (struct cmos_entries *)((unsigned char *)ct + ct->header_length); @@ -420,7 +421,7 @@ } if (!found) { printk(BIOS_DEBUG, "WARNING: No CMOS option '%s'.\n", name); - rdev_munmap(&rdev, ct); + clean_up_layout(ct); return CB_CMOS_OPTION_NOT_FOUND; } @@ -430,17 +431,17 @@ /* make sure the string is null terminated */ if (set_cmos_value(ce->bit + ce->length - 8, 8, &(u8[]){0}) != CB_SUCCESS) { - rdev_munmap(&rdev, ct); + clean_up_layout(ct); return CB_CMOS_ACCESS_ERROR; } } if (set_cmos_value(ce->bit, length, value) != CB_SUCCESS) { - rdev_munmap(&rdev, ct); + clean_up_layout(ct); return CB_CMOS_ACCESS_ERROR; } - rdev_munmap(&rdev, ct); + clean_up_layout(ct); return CB_SUCCESS; } -- To view, visit https://review.coreboot.org/c/coreboot/+/33057 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0623738838c62f49e9a8d93a34f01a509ef1f9cb Gerrit-Change-Number: 33057 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/baytrail: Use cpu/intel/car/romstage.c entry point
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32969 Change subject: soc/intel/baytrail: Use cpu/intel/car/romstage.c entry point ...................................................................... soc/intel/baytrail: Use cpu/intel/car/romstage.c entry point This moves some boilerplate like setting up timestamps and entering postcar to a common location. Change-Id: I256b4149163245697fe1c2d4406bd6229a45b556 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/baytrail/romstage/Makefile.inc M src/soc/intel/baytrail/romstage/romstage.c 2 files changed, 4 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/32969/1 diff --git a/src/soc/intel/baytrail/romstage/Makefile.inc b/src/soc/intel/baytrail/romstage/Makefile.inc index f1a3463..8f009bd 100644 --- a/src/soc/intel/baytrail/romstage/Makefile.inc +++ b/src/soc/intel/baytrail/romstage/Makefile.inc @@ -1,5 +1,6 @@ cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S cpu_incs-y += $(obj)/fmap_config.h +romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += raminit.c romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += uart.c diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index cc3bcd9..2a530b4 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -21,6 +21,7 @@ #include <bootblock_common.h> #include <console/console.h> #include <cbmem.h> +#include <cpu/intel/romstage.h> #include <cpu/x86/mtrr.h> #if CONFIG(EC_GOOGLE_CHROMEEC) #include <ec/google/chromeec/ec.h> @@ -49,8 +50,6 @@ * Because we can't use global variables the stack is used for allocations -- * thus the need to call back and forth. */ -static void platform_enter_postcar(void); - static void program_base_addresses(void) { uint32_t reg; @@ -166,18 +165,12 @@ } /* Entry from cache-as-ram.inc. */ -static void romstage_main(uint64_t tsc, uint32_t bist) +void mainboard_romstage_entry(unsigned long bist) { struct mrc_params mrc_params; struct chipset_power_state *ps; int prev_sleep_state; - /* Save initial timestamp from bootblock. */ - timestamp_init(tsc); - - /* Save romstage begin */ - timestamp_add_now(TS_START_ROMSTAGE); - program_base_addresses(); tco_disable(); @@ -215,25 +208,13 @@ timestamp_add_now(TS_AFTER_INITRAM); romstage_handoff_init(prev_sleep_state == ACPI_S3); - - platform_enter_postcar(); - - /* We don't return here */ -} - -/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK, - * keeping changes in cache_as_ram.S easy to manage. - */ -asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) -{ - romstage_main(base_timestamp, bist); } #define ROMSTAGE_RAM_STACK_SIZE 0x5000 /* setup_stack_and_mtrrs() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ -static void platform_enter_postcar(void) +void platform_enter_postcar(void) { struct postcar_frame pcf; uintptr_t top_of_ram; -- To view, visit https://review.coreboot.org/c/coreboot/+/32969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I256b4149163245697fe1c2d4406bd6229a45b556 Gerrit-Change-Number: 32969 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/baytrail: Place the raminit in a common location
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32968 Change subject: soc/intel/baytrail: Place the raminit in a common location ...................................................................... soc/intel/baytrail: Place the raminit in a common location Change-Id: I784382d5c5251fac7039f991f8a6ad123a0b4f83 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/rambi/romstage.c M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/romstage/romstage.c 3 files changed, 43 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/32968/1 diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index c244c83..93b6ba4 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -58,7 +58,7 @@ return spd_ptr; } -void mainboard_romstage_entry(struct mrc_params *mrc_params) +void mainboard_pre_raminit(struct mrc_params *mrc_params) { void *spd_content; int dual_channel = 0; @@ -80,6 +80,4 @@ mrc_params->mainboard.dram_data[0] = spd_content; if (dual_channel) mrc_params->mainboard.dram_data[1] = spd_content; - - romstage_common(mrc_params); } diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index ea6298b..7730893 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -24,8 +24,7 @@ #include <arch/cpu.h> #include <soc/mrc_wrapper.h> -void mainboard_romstage_entry(struct mrc_params *mrc_params); -void romstage_common(struct mrc_params *mrc_params); +void mainboard_pre_raminit(struct mrc_params *mrc_params); void raminit(struct mrc_params *mp, int prev_sleep_state); void gfx_init(void); void tco_disable(void); diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 73991df..cc3bcd9 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -96,49 +96,6 @@ write32(bcr, reg); } -/* Entry from cache-as-ram.inc. */ -static void romstage_main(uint64_t tsc, uint32_t bist) -{ - struct mrc_params mrc_params; - - /* Save initial timestamp from bootblock. */ - timestamp_init(tsc); - - /* Save romstage begin */ - timestamp_add_now(TS_START_ROMSTAGE); - - program_base_addresses(); - - tco_disable(); - - byt_config_com1_and_enable(); - - console_init(); - - spi_init(); - - set_max_freq(); - - punit_init(); - - gfx_init(); - - /* Call into mainboard. */ - mainboard_romstage_entry(&mrc_params); - - platform_enter_postcar(); - - /* We don't return here */ -} - -/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK, - * keeping changes in cache_as_ram.S easy to manage. - */ -asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) -{ - romstage_main(base_timestamp, bist); -} - static struct chipset_power_state power_state; static void migrate_power_state(int is_recovery) @@ -208,12 +165,38 @@ return prev_sleep_state; } -/* Entry from the mainboard. */ -void romstage_common(struct mrc_params *mrc_params) +/* Entry from cache-as-ram.inc. */ +static void romstage_main(uint64_t tsc, uint32_t bist) { + struct mrc_params mrc_params; struct chipset_power_state *ps; int prev_sleep_state; + /* Save initial timestamp from bootblock. */ + timestamp_init(tsc); + + /* Save romstage begin */ + timestamp_add_now(TS_START_ROMSTAGE); + + program_base_addresses(); + + tco_disable(); + + byt_config_com1_and_enable(); + + console_init(); + + spi_init(); + + set_max_freq(); + + punit_init(); + + gfx_init(); + + /* Call into mainboard. */ + mainboard_pre_raminit(&mrc_params); + timestamp_add_now(TS_BEFORE_INITRAM); ps = fill_power_state(); @@ -226,13 +209,24 @@ boot_count_increment(); #endif - /* Initialize RAM */ - raminit(mrc_params, prev_sleep_state); + raminit(&mrc_params, prev_sleep_state); timestamp_add_now(TS_AFTER_INITRAM); romstage_handoff_init(prev_sleep_state == ACPI_S3); + + platform_enter_postcar(); + + /* We don't return here */ +} + +/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK, + * keeping changes in cache_as_ram.S easy to manage. + */ +asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) +{ + romstage_main(base_timestamp, bist); } #define ROMSTAGE_RAM_STACK_SIZE 0x5000 -- To view, visit https://review.coreboot.org/c/coreboot/+/32968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I784382d5c5251fac7039f991f8a6ad123a0b4f83 Gerrit-Change-Number: 32968 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/baytrail: Extend the scope of the mrc_params
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32967 Change subject: soc/intel/baytrail: Extend the scope of the mrc_params ...................................................................... soc/intel/baytrail: Extend the scope of the mrc_params This makes it easier to call the common_romstage code in a common place. Change-Id: I58c5c376c51b48a7cb9b3bc79dd77e417c98d8ae Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/rambi/romstage.c M src/soc/intel/baytrail/include/soc/romstage.h 2 files changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/32967/1 diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index eba8beb..c244c83 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -21,6 +21,8 @@ #include <soc/romstage.h> #include <variant/variant.h> +static void *spd_ptr; + static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) { int ram_id = 0; @@ -52,7 +54,8 @@ if (dual_channel_config & (1 << ram_id)) *dual = 1; - return &spd_file_content[SPD_SIZE * ram_id]; + spd_ptr = &spd_file_content[SPD_SIZE * ram_id]; + return spd_ptr; } void mainboard_romstage_entry(struct mrc_params *mrc_params) @@ -73,6 +76,7 @@ spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE, &dual_channel); + mrc_params->mainboard.dram_data[0] = spd_content; if (dual_channel) mrc_params->mainboard.dram_data[1] = spd_content; diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index 4fceefb..ea6298b 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -26,7 +26,6 @@ void mainboard_romstage_entry(struct mrc_params *mrc_params); void romstage_common(struct mrc_params *mrc_params); - void raminit(struct mrc_params *mp, int prev_sleep_state); void gfx_init(void); void tco_disable(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/32967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58c5c376c51b48a7cb9b3bc79dd77e417c98d8ae Gerrit-Change-Number: 32967 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/baytrail: Get rid of struct romstage_params
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32966 Change subject: soc/intel/baytrail: Get rid of struct romstage_params ...................................................................... soc/intel/baytrail: Get rid of struct romstage_params struct romstage_params holds the BIST and a struct mrc_params pointer. The BIST information is unused. It is easier to just use a mrc_params struct variable. Change-Id: I54b7c6af2f47e85f66e67c81b7a0510488ca8da2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/rambi/romstage.c M src/soc/intel/baytrail/include/soc/romstage.h M src/soc/intel/baytrail/romstage/romstage.c 3 files changed, 13 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/32966/1 diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index 5322267..eba8beb 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -55,20 +55,16 @@ return &spd_file_content[SPD_SIZE * ram_id]; } -void mainboard_romstage_entry(struct romstage_params *rp) +void mainboard_romstage_entry(struct mrc_params *mrc_params) { void *spd_content; int dual_channel = 0; void *spd_file; size_t spd_fsize; - struct mrc_params mp = { - .mainboard = { - .dram_type = DRAM_DDR3L, - .dram_info_location = DRAM_INFO_SPD_MEM, - .weaker_odt_settings = 1, - }, - }; + mrc_params->mainboard.dram_type = DRAM_DDR3L; + mrc_params->mainboard.dram_info_location = DRAM_INFO_SPD_MEM; + mrc_params->mainboard.weaker_odt_settings = 1; spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, &spd_fsize); @@ -77,10 +73,9 @@ spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE, &dual_channel); - mp.mainboard.dram_data[0] = spd_content; + mrc_params->mainboard.dram_data[0] = spd_content; if (dual_channel) - mp.mainboard.dram_data[1] = spd_content; + mrc_params->mainboard.dram_data[1] = spd_content; - rp->mrc_params = &mp; - romstage_common(rp); + romstage_common(mrc_params); } diff --git a/src/soc/intel/baytrail/include/soc/romstage.h b/src/soc/intel/baytrail/include/soc/romstage.h index 3e8b6a2..4fceefb 100644 --- a/src/soc/intel/baytrail/include/soc/romstage.h +++ b/src/soc/intel/baytrail/include/soc/romstage.h @@ -24,13 +24,8 @@ #include <arch/cpu.h> #include <soc/mrc_wrapper.h> -struct romstage_params { - unsigned long bist; - struct mrc_params *mrc_params; -}; - -void mainboard_romstage_entry(struct romstage_params *params); -void romstage_common(struct romstage_params *params); +void mainboard_romstage_entry(struct mrc_params *mrc_params); +void romstage_common(struct mrc_params *mrc_params); void raminit(struct mrc_params *mp, int prev_sleep_state); void gfx_init(void); diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 5621dd1..73991df 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -99,10 +99,7 @@ /* Entry from cache-as-ram.inc. */ static void romstage_main(uint64_t tsc, uint32_t bist) { - struct romstage_params rp = { - .bist = bist, - .mrc_params = NULL, - }; + struct mrc_params mrc_params; /* Save initial timestamp from bootblock. */ timestamp_init(tsc); @@ -127,7 +124,7 @@ gfx_init(); /* Call into mainboard. */ - mainboard_romstage_entry(&rp); + mainboard_romstage_entry(&mrc_params); platform_enter_postcar(); @@ -212,7 +209,7 @@ } /* Entry from the mainboard. */ -void romstage_common(struct romstage_params *params) +void romstage_common(struct mrc_params *mrc_params) { struct chipset_power_state *ps; int prev_sleep_state; @@ -231,7 +228,7 @@ /* Initialize RAM */ - raminit(params->mrc_params, prev_sleep_state); + raminit(mrc_params, prev_sleep_state); timestamp_add_now(TS_AFTER_INITRAM); -- To view, visit https://review.coreboot.org/c/coreboot/+/32966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54b7c6af2f47e85f66e67c81b7a0510488ca8da2 Gerrit-Change-Number: 32966 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [UNTESTED]cpu/intel/model_1067x/mp_init: Implement get_microcode_info
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31600 Change subject: [UNTESTED]cpu/intel/model_1067x/mp_init: Implement get_microcode_info ...................................................................... [UNTESTED]cpu/intel/model_1067x/mp_init: Implement get_microcode_info Fixes microcode not being updated. Change-Id: Iee7a3897362b63bc6d7b9827da47c1cb24135278 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_1067x/mp_init.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/31600/1 diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c index acd56c8..1a6110b 100644 --- a/src/cpu/intel/model_1067x/mp_init.c +++ b/src/cpu/intel/model_1067x/mp_init.c @@ -49,6 +49,13 @@ smm_initialize(); } +static void get_microcode_info(const void **microcode, int *parallel) +{ + microcode_patch = intel_microcode_find(); + *microcode = microcode_patch; + *parallel = 1; +} + #define SMRR_SUPPORTED (1 << 11) static void per_cpu_smm_trigger(void) @@ -98,6 +105,7 @@ .pre_mp_init = pre_mp_init, .get_cpu_count = get_cpu_count, .get_smm_info = smm_info, + .get_microcode_info = get_microcode_info, .pre_mp_smm_init = pre_mp_smm_init, .per_cpu_smm_trigger = per_cpu_smm_trigger, .relocation_handler = smm_relocation_handler, -- To view, visit https://review.coreboot.org/c/coreboot/+/31600 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iee7a3897362b63bc6d7b9827da47c1cb24135278 Gerrit-Change-Number: 31600 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: cpu/intel/common: Compute the TSC tick freq based on FSB
by Arthur Heymans (Code Review) 13 Oct '19

13 Oct '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31203 Change subject: cpu/intel/common: Compute the TSC tick freq based on FSB ...................................................................... cpu/intel/common: Compute the TSC tick freq based on FSB This allows the cbmem utility to compute timestamps based on coreboot tables without relying on other userspace components. Change-Id: Ie87adec950dc51f4f873c0d852a325b3ff9b18bf Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/common/fsb.c 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31203/1 diff --git a/src/cpu/intel/common/fsb.c b/src/cpu/intel/common/fsb.c index 1f7c391..cf258bd 100644 --- a/src/cpu/intel/common/fsb.c +++ b/src/cpu/intel/common/fsb.c @@ -11,7 +11,9 @@ * GNU General Public License for more details. */ +#include <console/console.h> #include <cpu/cpu.h> +#include <cpu/x86/tsc.h> #include <cpu/x86/msr.h> #include <cpu/intel/speedstep.h> #include <cpu/intel/fsb.h> @@ -83,3 +85,27 @@ printk(BIOS_ERR, "FSB not supported or not found\n"); return -1; } + +unsigned long tsc_freq_mhz(void) +{ + msr_t msr; + unsigned long multiplier; + struct cpuinfo_x86 c; + + get_fms(&c, cpuid_eax(1)); + + msr = rdmsr(IA32_PLATFORM_ID); + multiplier = (msr.lo & SPEEDSTEP_RATIO_VALUE_MASK) + >> SPEEDSTEP_RATIO_SHIFT; + if ((c.x86 == 6 && c.x86_model == 0xe) || (c.x86 == 0xf)) { + /* Looks like Yonah CPUs don't have the frequency ratio in + IA32_PLATFORM_ID. Use IA32_PERF_STATUS instead, the reading + should be reliable as those CPUs don't have turbo mode. */ + msr = rdmsr(IA32_PERF_STATUS); + multiplier = (msr.hi & SPEEDSTEP_RATIO_VALUE_MASK) + >> SPEEDSTEP_RATIO_SHIFT; + } + + printk(BIOS_DEBUG, "CPU freq %ld\n", multiplier * get_ia32_fsb()); + return multiplier * get_ia32_fsb(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/31203 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie87adec950dc51f4f873c0d852a325b3ff9b18bf Gerrit-Change-Number: 31203 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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