coreboot-gerrit May 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: [WIP] sb/intel: Fix flashconsole on older architectures
by Matt DeVillier (Code Review) 15 May '19

15 May '19

Matt DeVillier has uploaded a new patch set (#13) to the change originally created by Nicola Corna. ( https://review.coreboot.org/c/coreboot/+/21107 ) Change subject: [WIP] sb/intel: Fix flashconsole on older architectures ...................................................................... [WIP] sb/intel: Fix flashconsole on older architectures Building coreboot with CONSOLE_SPI_FLASH on Sandybridge (and others) fails with the following errors: build/romstage/drivers/spi/spi-generic.o: In function `spi_setup_slave': src/drivers/spi/spi-generic.c:119: undefined reference to `spi_ctrlr_bus_map' src/drivers/spi/spi-generic.c:121: undefined reference to `spi_ctrlr_bus_map_count' src/drivers/spi/spi-generic.c:124: undefined reference to `spi_ctrlr_bus_map' This is due to the fact that sb/intel/common/spi.c is currently not built in romstage, but drivers/spi/spi-generic.c requires it. In this commit sb/intel/common/spi.c is adapted to the romstage and it is added to it. The qemu-q35 mainboard also had to have the LAPIC_MONOTONIC_TIMER config selected because its southbridge now selects the common/spi which selects SPI_FLASH, and the drivers/spi/spi_flash.c uses timer_monotonic_get. Other boards will usually have the LAPIC_MONOTONIC_TIMER config enabled from their northbridge, but qemu-q35 has no config for a northbridge, so it had to be added manually for compilation to succeed. In this commit, the broadwell monotonic_timer was also modified to be simpler and not reset to 0 at every stage (based on a now deprecated/removed change in the skylake implementation). Change-Id: Ifd3e8621fa4cb349b7e0e07118cab0380f24ff55 Signed-off-by: Nicola Corna <nicola(a)corna.info> Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/emulation/qemu-q35/Kconfig M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/baytrail/spi.c M src/soc/intel/braswell/Makefile.inc M src/soc/intel/braswell/spi.c M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/broadwell/monotonic_timer.c M src/soc/intel/broadwell/spi.c M src/soc/intel/fsp_baytrail/Makefile.inc M src/soc/intel/fsp_baytrail/spi.c M src/southbridge/intel/common/spi.c M src/southbridge/intel/i82801ix/Kconfig 12 files changed, 213 insertions(+), 206 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/21107/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/21107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd3e8621fa4cb349b7e0e07118cab0380f24ff55 Gerrit-Change-Number: 21107 Gerrit-PatchSet: 13 Gerrit-Owner: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: [WIP] sb/intel: Fix flashconsole on older architectures
by Furquan Shaikh (Code Review) 15 May '19

15 May '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21107 ) Change subject: [WIP] sb/intel: Fix flashconsole on older architectures ...................................................................... Patch Set 12: (1 comment) https://review.coreboot.org/#/c/21107/12/src/mainboard/emulation/qemu-q35/K… File src/mainboard/emulation/qemu-q35/Kconfig: https://review.coreboot.org/#/c/21107/12/src/mainboard/emulation/qemu-q35/K… PS12, Line 7: UDELAY_LAPIC CPU_QEMU_X86 already selects UDELAY_TSC. Shouldn't that also set TSC_MONOTONIC_TIMER? -- To view, visit https://review.coreboot.org/c/coreboot/+/21107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd3e8621fa4cb349b7e0e07118cab0380f24ff55 Gerrit-Change-Number: 21107 Gerrit-PatchSet: 12 Gerrit-Owner: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 15 May 2019 03:57:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: [WIP] sb/intel: Fix flashconsole on older architectures
by Aaron Durbin (Code Review) 15 May '19

15 May '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21107 ) Change subject: [WIP] sb/intel: Fix flashconsole on older architectures ...................................................................... Patch Set 12: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/21107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd3e8621fa4cb349b7e0e07118cab0380f24ff55 Gerrit-Change-Number: 21107 Gerrit-PatchSet: 12 Gerrit-Owner: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 15 May 2019 03:39:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: [WIP] sb/intel: Fix flashconsole on older architectures
by Matt DeVillier (Code Review) 15 May '19

15 May '19

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21107 ) Change subject: [WIP] sb/intel: Fix flashconsole on older architectures ...................................................................... Patch Set 12: Rebased this since it had become a bit stale and needed some massaging. Tested on Broadwell (google/lulu) and Broadwell-DE (out of tree board) -- To view, visit https://review.coreboot.org/c/coreboot/+/21107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd3e8621fa4cb349b7e0e07118cab0380f24ff55 Gerrit-Change-Number: 21107 Gerrit-PatchSet: 12 Gerrit-Owner: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 15 May 2019 03:26:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: [WIP] sb/intel: Fix flashconsole on older architectures
by Matt DeVillier (Code Review) 15 May '19

15 May '19

Matt DeVillier has uploaded a new patch set (#12) to the change originally created by Nicola Corna. ( https://review.coreboot.org/c/coreboot/+/21107 ) Change subject: [WIP] sb/intel: Fix flashconsole on older architectures ...................................................................... [WIP] sb/intel: Fix flashconsole on older architectures Building coreboot with CONSOLE_SPI_FLASH on Sandybridge (and others) fails with the following errors: build/romstage/drivers/spi/spi-generic.o: In function `spi_setup_slave': src/drivers/spi/spi-generic.c:119: undefined reference to `spi_ctrlr_bus_map' src/drivers/spi/spi-generic.c:121: undefined reference to `spi_ctrlr_bus_map_count' src/drivers/spi/spi-generic.c:124: undefined reference to `spi_ctrlr_bus_map' This is due to the fact that sb/intel/common/spi.c is currently not built in romstage, but drivers/spi/spi-generic.c requires it. In this commit sb/intel/common/spi.c is adapted to the romstage and it is added to it. The qemu-q35 mainboard also had to have the LAPIC_MONOTONIC_TIMER config selected because its southbridge now selects the common/spi which selects SPI_FLASH, and the drivers/spi/spi_flash.c uses timer_monotonic_get. Other boards will usually have the LAPIC_MONOTONIC_TIMER config enabled from their northbridge, but qemu-q35 has no config for a northbridge, so it had to be added manually for compilation to succeed. In this commit, the broadwell monotonic_timer was also modified to be simpler and not reset to 0 at every stage (based on a now deprecated/removed change in the skylake implementation). Change-Id: Ifd3e8621fa4cb349b7e0e07118cab0380f24ff55 Signed-off-by: Nicola Corna <nicola(a)corna.info> Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/emulation/qemu-q35/Kconfig M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/baytrail/spi.c M src/soc/intel/braswell/Makefile.inc M src/soc/intel/braswell/spi.c M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/broadwell/monotonic_timer.c M src/soc/intel/broadwell/spi.c M src/soc/intel/fsp_baytrail/Makefile.inc M src/soc/intel/fsp_baytrail/spi.c M src/southbridge/intel/common/spi.c M src/southbridge/intel/i82801ix/Kconfig 12 files changed, 214 insertions(+), 206 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/21107/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/21107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd3e8621fa4cb349b7e0e07118cab0380f24ff55 Gerrit-Change-Number: 21107 Gerrit-PatchSet: 12 Gerrit-Owner: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK
by Matt DeVillier (Code Review) 15 May '19

15 May '19

Matt DeVillier has uploaded a new patch set (#49) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/30383 ) Change subject: soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK ...................................................................... soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK This puts the cache-as-ram init in the bootblock. Before setting up cache as ram the microcode updates are applied. This removes the possibility for a normal/fallback setup although implementing this should be quite easy. Setting up LPC in the bootblock to output console on SuperIOs is not done in this patch, therefore BOOTBLOCK_CONSOLE is not yet selected. Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/broadwell/bootblock/cpu.c M src/soc/intel/broadwell/bootblock/pch.c M src/soc/intel/broadwell/bootblock/systemagent.c M src/soc/intel/broadwell/romstage/Makefile.inc M src/soc/intel/broadwell/romstage/romstage.c 7 files changed, 26 insertions(+), 78 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/30383/49 -- To view, visit https://review.coreboot.org/c/coreboot/+/30383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935 Gerrit-Change-Number: 30383 Gerrit-PatchSet: 49 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/broadwell: Enable LPC/SIO setup in bootblock
by Matt DeVillier (Code Review) 15 May '19

15 May '19

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30385 ) Change subject: soc/intel/broadwell: Enable LPC/SIO setup in bootblock ...................................................................... Patch Set 54: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/30385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7746e4f819486d6142c96bc4c7480076fbfdfbde Gerrit-Change-Number: 30385 Gerrit-PatchSet: 54 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 15 May 2019 03:09:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/broadwell: Add an option for where verstage starts
by Matt DeVillier (Code Review) 15 May '19

15 May '19

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30384 ) Change subject: nb/intel/broadwell: Add an option for where verstage starts ...................................................................... Patch Set 52: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/30384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I900233cadb3c76da329fb98f93917570e633365f Gerrit-Change-Number: 30384 Gerrit-PatchSet: 52 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 15 May 2019 03:09:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK
by Matt DeVillier (Code Review) 15 May '19

15 May '19

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30383 ) Change subject: soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK ...................................................................... Patch Set 48: (1 comment) https://review.coreboot.org/#/c/30383/48/src/soc/intel/broadwell/romstage/r… File src/soc/intel/broadwell/romstage/romstage.c: https://review.coreboot.org/#/c/30383/48/src/soc/intel/broadwell/romstage/r… PS48, Line 72: > Losing the initialization of `pei_data` here. Maybe memset() the […] nice catch, that seems to have been the issue :) -- To view, visit https://review.coreboot.org/c/coreboot/+/30383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935 Gerrit-Change-Number: 30383 Gerrit-PatchSet: 48 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 15 May 2019 03:04:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/poppy/variant/atlas: Add SPDs for Samsung D-die chips
by Furquan Shaikh (Code Review) 15 May '19

15 May '19

Furquan Shaikh has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32780 ) Change subject: mb/google/poppy/variant/atlas: Add SPDs for Samsung D-die chips ...................................................................... mb/google/poppy/variant/atlas: Add SPDs for Samsung D-die chips This adds the SPDs for Samsung D-die 16Gbit and 32Gbit LPDDR3-2133 chips. BUG=b:132206809 TEST=boots on atlas with C-die and D-die memory chips localhost ~ # mosys memory spd print all 0 | LPDDR3 | SO-DIMM 1 | LPDDR3 | SO-DIMM 0 | 1-78: Samsung | 00000000 | K4EBE304ED-EGCG 1 | 1-78: Samsung | 00000000 | K4EBE304ED-EGCG 0 | 8192 | 2 | 64 1 | 8192 | 2 | 64 0 | LPDDR3-800, LPDDR3-1066, LPDDR3-1333, LPDDR3-1600, LPDDR3-1866, LPDDR3-2133 1 | LPDDR3-800, LPDDR3-1066, LPDDR3-1333, LPDDR3-1600, LPDDR3-1866, LPDDR3-2133 localhost ~ # Change-Id: I8ba000aeeb77f07d7f18bda86b3c07f5b50478b8 Signed-off-by: Caveh Jalali <caveh(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32780 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- A src/mainboard/google/poppy/spd/samsung_dimm_K4E6E304ED-EGCG.spd.hex A src/mainboard/google/poppy/spd/samsung_dimm_K4EBE304ED-EGCG.spd.hex M src/mainboard/google/poppy/variants/atlas/Makefile.inc 3 files changed, 34 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/poppy/spd/samsung_dimm_K4E6E304ED-EGCG.spd.hex b/src/mainboard/google/poppy/spd/samsung_dimm_K4E6E304ED-EGCG.spd.hex new file mode 100644 index 0000000..a1dc212 --- /dev/null +++ b/src/mainboard/google/poppy/spd/samsung_dimm_K4E6E304ED-EGCG.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 19 05 0B 03 11 01 08 08 00 40 55 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 00 C2 00 00 00 00 A8 00 08 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 00 00 00 00 00 00 00 00 00 +4B 34 45 36 45 33 30 34 45 44 2D 45 47 43 47 20 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/spd/samsung_dimm_K4EBE304ED-EGCG.spd.hex b/src/mainboard/google/poppy/spd/samsung_dimm_K4EBE304ED-EGCG.spd.hex new file mode 100644 index 0000000..e59d828 --- /dev/null +++ b/src/mainboard/google/poppy/spd/samsung_dimm_K4EBE304ED-EGCG.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 1A 05 0A 03 11 01 08 08 00 40 55 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 00 C2 00 00 00 00 A8 00 08 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 00 00 00 00 00 00 00 00 00 +4B 34 45 42 45 33 30 34 45 44 2D 45 47 43 47 20 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/variants/atlas/Makefile.inc b/src/mainboard/google/poppy/variants/atlas/Makefile.inc index 06776ff..397ef68 100644 --- a/src/mainboard/google/poppy/variants/atlas/Makefile.inc +++ b/src/mainboard/google/poppy/variants/atlas/Makefile.inc @@ -12,6 +12,8 @@ SPD_SOURCES += samsung_dimm_K4E6E304EC-EGCF # 0b1010 SPD_SOURCES += samsung_dimm_K4EBE304EC-EGCF # 0b1011 SPD_SOURCES += nayna_dimm_NT6CL256T32CM-H1 # 0b1100 +SPD_SOURCES += samsung_dimm_K4E6E304ED-EGCG # 0b1101 +SPD_SOURCES += samsung_dimm_K4EBE304ED-EGCG # 0b1110 bootblock-y += gpio.c -- To view, visit https://review.coreboot.org/c/coreboot/+/32780 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8ba000aeeb77f07d7f18bda86b3c07f5b50478b8 Gerrit-Change-Number: 32780 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Tim Chen <Tim-Chen(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-MessageType: merged

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coreboot-gerrit May 2019