coreboot-gerrit May 2019

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Change in ...coreboot[master]: libpayload: ahci: Prevent memory leaks when failing on init
by Jacob Garber (Code Review) 15 May '19

15 May '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32778 Change subject: libpayload: ahci: Prevent memory leaks when failing on init ...................................................................... libpayload: ahci: Prevent memory leaks when failing on init Free several resources when AHCI initialization fails. Note that it is only safe to free resources when the command engine has stopped, since otherwise they may still be used for DMA. Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Change-Id: I6826d79338b26ff9696ab6ac9eb4c59f734687d8 --- M payloads/libpayload/drivers/storage/ahci.c 1 file changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/32778/1 diff --git a/payloads/libpayload/drivers/storage/ahci.c b/payloads/libpayload/drivers/storage/ahci.c index 40e1008..0aa499f 100644 --- a/payloads/libpayload/drivers/storage/ahci.c +++ b/payloads/libpayload/drivers/storage/ahci.c @@ -108,6 +108,10 @@ const int ncs = HBA_CAPS_DECODE_NCS(ctrl->caps); + /* Set command list base and received FIS base. */ + if (ahci_cmdengine_stop(port)) + return 1; + /* Allocate command list, one command table and received FIS. */ cmd_t *const cmdlist = memalign(1024, ncs * sizeof(cmd_t)); cmdtable_t *const cmdtable = memalign(128, sizeof(cmdtable_t)); @@ -120,13 +124,10 @@ memset((void *)cmdtable, '\0', sizeof(*cmdtable)); memset((void *)rcvd_fis, '\0', sizeof(*rcvd_fis)); - /* Set command list base and received FIS base. */ - if (ahci_cmdengine_stop(port)) - return 1; port->cmdlist_base = virt_to_phys(cmdlist); port->frameinfo_base = virt_to_phys(rcvd_fis); if (ahci_cmdengine_start(port)) - return 1; + goto _cleanup_ret; /* Put port into active state. */ port->cmd_stat |= HBA_PxCMD_ICC_ACTIVE; @@ -178,6 +179,8 @@ /* Clean up (not reached for initialized devices). */ if (dev) free(dev); + /* Only free if stopping succeeds, since otherwise the controller may + * still use the resources for DMA. */ if (!ahci_cmdengine_stop(port)) { port->cmdlist_base = 0; port->frameinfo_base = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/32778 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6826d79338b26ff9696ab6ac9eb4c59f734687d8 Gerrit-Change-Number: 32778 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: vboot: remove OPROM-related code
by Joel Kitching (Code Review) 15 May '19

15 May '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32723 Change subject: vboot: remove OPROM-related code ...................................................................... vboot: remove OPROM-related code As of CL:1605641, vboot2 code should be used for setting and checking display init state. Remove all vboot1 OPROM-related code, and use the vboot2 display init code which has already been added in previous commits. coreboot should not be reading vboot NVRAM flags directly. Remove the function vboot_wants_oprom(), and instead rely on display_init_required(), which uses the VBOOT_WD_FLAG_DISPLAY_INIT value stored in vboot_working_data.flags, initialized during verstage. Note that this means in the case of CONFIG_VBOOT=y, the return value of display_init_required() can only be trusted after verstage has been executed. This should not be a problem assuming that all display initialization occurs in ramstage. BUG=b:124141368, b:124192753, chromium:948529 TEST=Build locally TEST=make clean && make test-abuild BRANCH=none Change-Id: Ic8f9dc5a3c7f1546a8fed82bde02be4d04568f8d Signed-off-by: Joel Kitching <kitching(a)google.com> Cq-Depend: chromium:1605641, chromium:1605525 --- M src/device/pci_device.c M src/security/vboot/vbnv.c M src/security/vboot/vbnv.h M src/security/vboot/vboot_handoff.c M src/soc/intel/broadwell/igd.c 5 files changed, 1 insertion(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/32723/1 diff --git a/src/device/pci_device.c b/src/device/pci_device.c index b5453c7..31c35dc 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -780,9 +780,6 @@ */ should_run = display_init_required(); - if (!should_run && CONFIG(VBOOT)) - should_run = vboot_wants_oprom(); - if (!should_run) printk(BIOS_DEBUG, "Not running VGA Option ROM\n"); return should_run; diff --git a/src/security/vboot/vbnv.c b/src/security/vboot/vbnv.c index 78502f7..0c4f33b 100644 --- a/src/security/vboot/vbnv.c +++ b/src/security/vboot/vbnv.c @@ -140,13 +140,6 @@ return vbnv_data(RECOVERY_OFFSET); } -/* Read the BOOT_DISPLAY_REQUEST flag from VBNV. */ -int vboot_wants_oprom(void) -{ - vbnv_setup(); - return (vbnv_data(BOOT_OFFSET) & BOOT_DISPLAY_REQUEST) ? 1 : 0; -} - /* Read the USB Device Controller(UDC) enable flag from VBNV. */ int vbnv_udc_enable_flag(void) { diff --git a/src/security/vboot/vbnv.h b/src/security/vboot/vbnv.h index c8e689f..a2f0b4c 100644 --- a/src/security/vboot/vbnv.h +++ b/src/security/vboot/vbnv.h @@ -25,7 +25,6 @@ void regen_vbnv_crc(uint8_t *vbnv_copy); int get_recovery_mode_from_vbnv(void); void set_recovery_mode_into_vbnv(int recovery_reason); -int vboot_wants_oprom(void); /* Read the USB Device Controller(UDC) enable flag from VBNV. */ int vbnv_udc_enable_flag(void); diff --git a/src/security/vboot/vboot_handoff.c b/src/security/vboot/vboot_handoff.c index fccbdfc..8a6b3d6 100644 --- a/src/security/vboot/vboot_handoff.c +++ b/src/security/vboot/vboot_handoff.c @@ -68,13 +68,6 @@ vb_sd->flags |= VBSD_BOOT_DEV_SWITCH_ON; vb_sd->flags |= VBSD_LF_DEV_SWITCH_ON; } - /* TODO(chromium:948529): Remove these two flags after downstream - vboot code longer reads them. */ - if (vboot_wants_oprom() || vb2_sd->recovery_reason || - vb2_sd->flags & VB2_SD_FLAG_DEV_MODE_ENABLED) - vb_sd->flags |= VBSD_OPROM_LOADED; - if (CONFIG(VBOOT_MUST_REQUEST_DISPLAY)) - vb_sd->flags |= VBSD_OPROM_MATTERS; /* In vboot1, VBSD_FWB_TRIED is * set only if B is booted as explicitly requested. Therefore, if B is diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index 319549d..b9b4281 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -513,7 +513,7 @@ /* Wait for any configured pre-graphics delay */ if (!acpi_is_wakeup_s3()) { #if CONFIG(CHROMEOS) - if (display_init_required() || vboot_wants_oprom()) + if (display_init_required()) mdelay(CONFIG_PRE_GRAPHICS_DELAY); #else mdelay(CONFIG_PRE_GRAPHICS_DELAY); -- To view, visit https://review.coreboot.org/c/coreboot/+/32723 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8f9dc5a3c7f1546a8fed82bde02be4d04568f8d Gerrit-Change-Number: 32723 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: vboot: rename BOOT_OPROM_NEEDED
by Joel Kitching (Code Review) 15 May '19

15 May '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32720 Change subject: vboot: rename BOOT_OPROM_NEEDED ...................................................................... vboot: rename BOOT_OPROM_NEEDED Verified Boot OPROM code is being refactored. OPROM is being generalized into "display initialization". As such, the NVRAM request flag is being renamed from OPROM_NEEDED to DISPLAY_REQUEST. BUG=b:124141368, b:124192753, chromium:948529 TEST=make clean && make test-abuild BRANCH=none Change-Id: I74374abf7d1deb594c073f7a4a76c9de46092143 Signed-off-by: Joel Kitching <kitching(a)google.com> Cq-Depend: chromium:1605640 --- M src/security/vboot/vbnv.c M src/security/vboot/vbnv_layout.h 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/32720/1 diff --git a/src/security/vboot/vbnv.c b/src/security/vboot/vbnv.c index b999418..2449328 100644 --- a/src/security/vboot/vbnv.c +++ b/src/security/vboot/vbnv.c @@ -140,11 +140,11 @@ return vbnv_data(RECOVERY_OFFSET); } -/* Read the BOOT_OPROM_NEEDED flag from VBNV. */ +/* Read the BOOT_DISPLAY_REQUEST flag from VBNV. */ int vboot_wants_oprom(void) { vbnv_setup(); - return (vbnv_data(BOOT_OFFSET) & BOOT_OPROM_NEEDED) ? 1 : 0; + return (vbnv_data(BOOT_OFFSET) & BOOT_DIPLAY_REQUEST) ? 1 : 0; } /* Read the USB Device Controller(UDC) enable flag from VBNV. */ diff --git a/src/security/vboot/vbnv_layout.h b/src/security/vboot/vbnv_layout.h index a9326e4..a3c2490 100644 --- a/src/security/vboot/vbnv_layout.h +++ b/src/security/vboot/vbnv_layout.h @@ -31,7 +31,7 @@ #define BOOT_OFFSET 1 #define BOOT_DEBUG_RESET_MODE 0x80 #define BOOT_DISABLE_DEV_REQUEST 0x40 -#define BOOT_OPROM_NEEDED 0x20 +#define BOOT_DISPLAY_REQUEST 0x20 #define BOOT_TRY_B_COUNT_MASK 0x0F #define RECOVERY_OFFSET 2 -- To view, visit https://review.coreboot.org/c/coreboot/+/32720 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74374abf7d1deb594c073f7a4a76c9de46092143 Gerrit-Change-Number: 32720 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/packardbell/ms2290/acpi: Serialize Control Method
by HAOUAS Elyes (Code Review) 15 May '19

15 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32769 Change subject: mb/packardbell/ms2290/acpi: Serialize Control Method ...................................................................... mb/packardbell/ms2290/acpi: Serialize Control Method IASL reports warning 'Control Method should be made Serialized'. Change-Id: I5606c6e435da17f7d4732148f6ddcedb1fde4ab0 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/packardbell/ms2290/acpi/battery.asl M src/mainboard/packardbell/ms2290/acpi/ec.asl 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/32769/1 diff --git a/src/mainboard/packardbell/ms2290/acpi/battery.asl b/src/mainboard/packardbell/ms2290/acpi/battery.asl index 716c3a6..d341ab4 100644 --- a/src/mainboard/packardbell/ms2290/acpi/battery.asl +++ b/src/mainboard/packardbell/ms2290/acpi/battery.asl @@ -52,7 +52,7 @@ Return (Arg1) } -Method(BINF, 2, NotSerialized) +Method(BINF, 2, Serialized) { Acquire(ECLK, 0xffff) Store(0, PAGE) diff --git a/src/mainboard/packardbell/ms2290/acpi/ec.asl b/src/mainboard/packardbell/ms2290/acpi/ec.asl index 5fb2498..4f3e5b6 100644 --- a/src/mainboard/packardbell/ms2290/acpi/ec.asl +++ b/src/mainboard/packardbell/ms2290/acpi/ec.asl @@ -101,7 +101,7 @@ BAOE, 128, /* Battery OEM info */ } - Method (_CRS, 0) + Method (_CRS, 0, Serialized) { Name (ECMD, ResourceTemplate() { -- To view, visit https://review.coreboot.org/c/coreboot/+/32769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5606c6e435da17f7d4732148f6ddcedb1fde4ab0 Gerrit-Change-Number: 32769 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/poppy/variants/atlas: Remove B0D4 _PSV
by Puthikorn Voravootivat (Code Review) 15 May '19

15 May '19

Puthikorn Voravootivat has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32779 Change subject: mb/google/poppy/variants/atlas: Remove B0D4 _PSV ...................................................................... mb/google/poppy/variants/atlas: Remove B0D4 _PSV Per Intel, the internal thermal protection is working better than putting B0D4 _PSV in dptf. BUG=b:131251533 TEST=Get ~10% better Octane score. Correct TCC and TCC offset in MSR register. Change-Id: If85afdc673687477ec85a47efcb264a7e5d6ae45 Signed-off-by: Puthikorn Voravootivat <puthik(a)chromium.org> --- M src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/32779/1 diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl index 29c1d3f..570fbbb 100644 --- a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl @@ -49,9 +49,6 @@ }) Name (DTRT, Package () { - /* CPU Throttle Effect on CPU */ - Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, - /* CPU Throttle Effect on Ambient */ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 200, 0, 0, 0, 0 }, -- To view, visit https://review.coreboot.org/c/coreboot/+/32779 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If85afdc673687477ec85a47efcb264a7e5d6ae45 Gerrit-Change-Number: 32779 Gerrit-PatchSet: 1 Gerrit-Owner: Puthikorn Voravootivat <puthik(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/poppy/variants/rammus: Support new onboard Hynix memory
by Patrick Georgi (Code Review) 15 May '19

15 May '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32674 ) Change subject: mb/google/poppy/variants/rammus: Support new onboard Hynix memory ...................................................................... mb/google/poppy/variants/rammus: Support new onboard Hynix memory Add hynix_dimm_H9CCNNNCLGALAR-NVD for new onboard memory support. BUG=b:130337306 BRANCH=firmware-rammus-11275.B TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Signed-off-by: YanRu Chen <kane_chen(a)pegatron.corp-partner.google.com> Change-Id: Ibd02953d0c6ac62fa4d7751fd8b103b74433aa73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32674 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- A src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCLGALAR-NVD.spd.hex M src/mainboard/google/poppy/variants/rammus/Makefile.inc 2 files changed, 17 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCLGALAR-NVD.spd.hex b/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCLGALAR-NVD.spd.hex new file mode 100644 index 0000000..ada67c9 --- /dev/null +++ b/src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCLGALAR-NVD.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 05 1A 05 0A 03 11 01 08 08 00 00 15 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 00 C2 00 00 00 00 A8 00 88 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 01 00 00 00 00 00 00 00 00 +48 39 43 43 4E 4E 4E 43 4C 47 41 4C 41 52 2D 4E +56 44 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/variants/rammus/Makefile.inc b/src/mainboard/google/poppy/variants/rammus/Makefile.inc index 44dd07b..0d835cb 100644 --- a/src/mainboard/google/poppy/variants/rammus/Makefile.inc +++ b/src/mainboard/google/poppy/variants/rammus/Makefile.inc @@ -3,6 +3,7 @@ SPD_SOURCES += micron_dimm_MT52L256M32D1PF-093 # 0b0010 SPD_SOURCES += samsung_dimm_K4E6E304EC-EGCF # 0b0011 SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107 # 0b0100 +SPD_SOURCES += hynix_dimm_H9CCNNNCLGALAR-NVD # 0b0101 bootblock-y += gpio.c -- To view, visit https://review.coreboot.org/c/coreboot/+/32674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd02953d0c6ac62fa4d7751fd8b103b74433aa73 Gerrit-Change-Number: 32674 Gerrit-PatchSet: 5 Gerrit-Owner: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: merged

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Change in ...coreboot[master]: soc/intel/cannonlake: Clean up cannonlake_memcfg_init
by Philip Chen (Code Review) 15 May '19

15 May '19

Philip Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32513 Change subject: soc/intel/cannonlake: Clean up cannonlake_memcfg_init ...................................................................... soc/intel/cannonlake: Clean up cannonlake_memcfg_init The major changes include: (1) Add enum 'mem_info_read_type' to spd_info. (2) Add spd_into into cnl_mb_cfg. (3) Squash meminit_memcfg_spd(). BUG=b:124990009 TEST=build Change-Id: I686a85996858204c20fd05ef24787a0487817c34 --- M src/mainboard/google/hatch/romstage.c M src/mainboard/google/hatch/variants/baseboard/memory.c M src/mainboard/google/sarien/romstage.c M src/mainboard/intel/coffeelake_rvp/memory.c M src/mainboard/intel/coffeelake_rvp/romstage.c M src/soc/intel/cannonlake/cnl_memcfg_init.c M src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h 7 files changed, 90 insertions(+), 84 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/32513/1 diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c index bdf951b..95db576 100644 --- a/src/mainboard/google/hatch/romstage.c +++ b/src/mainboard/google/hatch/romstage.c @@ -25,14 +25,8 @@ { struct cnl_mb_cfg memcfg; - const struct spd_info spd = { - .spd_by_index = true, - .spd_spec.spd_index = variant_memory_sku(), - }; - variant_memory_params(&memcfg); - cannonlake_memcfg_init(&memupd->FspmConfig, - &memcfg, &spd); + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); } void mainboard_get_dram_part_num(const char **part_num, size_t *len) diff --git a/src/mainboard/google/hatch/variants/baseboard/memory.c b/src/mainboard/google/hatch/variants/baseboard/memory.c index b6a6615..8706332 100644 --- a/src/mainboard/google/hatch/variants/baseboard/memory.c +++ b/src/mainboard/google/hatch/variants/baseboard/memory.c @@ -20,6 +20,9 @@ #include <string.h> static const struct cnl_mb_cfg baseboard_memcfg = { + .spd = { + .read_type = READ_SPD_CBFS}, + /* * The dqs_map arrays map the ddr4 pins to the SoC pins * for both channels. @@ -27,14 +30,14 @@ * the index = pin number on ddr4 part * the value = pin number on SoC */ - .dqs_map[DDR_CH0] = { 0, 1, 4, 5, 2, 3, 6, 7 }, - .dqs_map[DDR_CH1] = { 0, 1, 4, 5, 2, 3, 6, 7 }, + .dqs_map[DDR_CH0] = {0, 1, 4, 5, 2, 3, 6, 7}, + .dqs_map[DDR_CH1] = {0, 1, 4, 5, 2, 3, 6, 7}, /* Baseboard uses 121, 81 and 100 rcomp resistors */ - .rcomp_resistor = { 121, 81, 100 }, + .rcomp_resistor = {121, 81, 100}, /* Baseboard Rcomp target values */ - .rcomp_targets = { 100, 40, 20, 20, 26 }, + .rcomp_targets = {100, 40, 20, 20, 26}, /* Set CaVref config to 2 */ .vref_ca_config = 2, @@ -46,6 +49,7 @@ void __weak variant_memory_params(struct cnl_mb_cfg *bcfg) { memcpy(bcfg, &baseboard_memcfg, sizeof(baseboard_memcfg)); + bcfg->spd.spd_spec.spd_index = variant_memory_sku(); /* * GPP_F2 is the MEM_CH_SEL gpio, which is set to 1 for single * channel skus and 0 for dual channel skus. diff --git a/src/mainboard/google/sarien/romstage.c b/src/mainboard/google/sarien/romstage.c index e83cd4a..b66fd70 100644 --- a/src/mainboard/google/sarien/romstage.c +++ b/src/mainboard/google/sarien/romstage.c @@ -18,6 +18,14 @@ #include <soc/romstage.h> static const struct cnl_mb_cfg memcfg = { + .spd = { + .read_type = READ_SMBUS, + .spd_spec = { + .spd_smbus_address[0] = 0xa0, + .spd_smbus_address[2] = 0xa4, + }, + }, + /* * The dqs_map arrays map the ddr4 pins to the SoC pins * for both channels. @@ -25,16 +33,16 @@ * the index = pin number on ddr4 part * the value = pin number on SoC */ - .dqs_map[DDR_CH0] = { 0, 1, 4, 5, 2, 3, 6, 7 }, - .dqs_map[DDR_CH1] = { 0, 1, 4, 5, 2, 3, 6, 7 }, + .dqs_map[DDR_CH0] = {0, 1, 4, 5, 2, 3, 6, 7}, + .dqs_map[DDR_CH1] = {0, 1, 4, 5, 2, 3, 6, 7}, /* Baseboard uses 121, 81 and 100 rcomp resistors */ - .rcomp_resistor = { 121, 81, 100 }, + .rcomp_resistor = {121, 81, 100}, /* * Baseboard Rcomp target values. */ - .rcomp_targets = { 100, 40, 20, 20, 26 }, + .rcomp_targets = {100, 40, 20, 20, 26}, /* Disable Early Command Training */ .ect = 0, @@ -45,12 +53,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { - const struct spd_info spd = { - .spd_smbus_address[0] = 0xa0, - .spd_smbus_address[2] = 0xa4 - }; - wilco_ec_romstage_init(); - cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg, &spd); + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); } diff --git a/src/mainboard/intel/coffeelake_rvp/memory.c b/src/mainboard/intel/coffeelake_rvp/memory.c index a13000c..a9695e8 100644 --- a/src/mainboard/intel/coffeelake_rvp/memory.c +++ b/src/mainboard/intel/coffeelake_rvp/memory.c @@ -20,23 +20,32 @@ #include <soc/cnl_memcfg_init.h> static const struct cnl_mb_cfg baseboard_memcfg_cfg = { - /* + .spd = { + .read_type = READ_SMBUS, + .spd_spec = { + .spd_smbus_address[0] = 0xA0, + .spd_smbus_address[1] = 0xA2, + .spd_smbus_address[2] = 0xA4, + .spd_smbus_address[3] = 0xA6, + }, + }; +/* * The dqs_map arrays map the ddr4 pins to the SoC pins * for both channels. * * the index = pin number on ddr4 part * the value = pin number on SoC */ - .dqs_map[DDR_CH0] = { 0, 1, 3, 2, 4, 5, 6, 7 }, - .dqs_map[DDR_CH1] = { 1, 0, 4, 5, 2, 3, 6, 7 }, +.dqs_map[DDR_CH0] = {0, 1, 3, 2, 4, 5, 6, 7}, + .dqs_map[DDR_CH1] = {1, 0, 4, 5, 2, 3, 6, 7}, /* Baseboard uses 121, 81 and 100 rcomp resistors */ - .rcomp_resistor = { 121, 81, 100 }, + .rcomp_resistor = {121, 81, 100}, /* * Baseboard Rcomp target values. */ - .rcomp_targets = { 100, 40, 20, 20, 26 }, + .rcomp_targets = {100, 40, 20, 20, 26}, /* Baseboard is an interleaved design */ .dq_pins_interleaved = 1, @@ -46,7 +55,8 @@ /* Disable Early Command Training */ .ect = 0, -}; +} +; const struct cnl_mb_cfg *__weak variant_memcfg_config(void) { diff --git a/src/mainboard/intel/coffeelake_rvp/romstage.c b/src/mainboard/intel/coffeelake_rvp/romstage.c index 1ab2d78..09ef148 100644 --- a/src/mainboard/intel/coffeelake_rvp/romstage.c +++ b/src/mainboard/intel/coffeelake_rvp/romstage.c @@ -20,13 +20,5 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) { - const struct spd_info spd = { - .spd_smbus_address[0] = 0xA0, - .spd_smbus_address[1] = 0xA2, - .spd_smbus_address[2] = 0xA4, - .spd_smbus_address[3] = 0xA6, - }; - - cannonlake_memcfg_init(&memupd->FspmConfig, - variant_memcfg_config(), &spd); + cannonlake_memcfg_init(&memupd->FspmConfig, variant_memcfg_config()); } diff --git a/src/soc/intel/cannonlake/cnl_memcfg_init.c b/src/soc/intel/cannonlake/cnl_memcfg_init.c index db001b8..ad7a71c 100644 --- a/src/soc/intel/cannonlake/cnl_memcfg_init.c +++ b/src/soc/intel/cannonlake/cnl_memcfg_init.c @@ -20,7 +20,7 @@ #include <string.h> static void meminit_memcfg(FSP_M_CONFIG *mem_cfg, - const struct cnl_mb_cfg *board_cfg) + const struct cnl_mb_cfg *board_cfg) { /* * DqByteMapChx expects 12 bytes of data, but the last 6 bytes @@ -29,29 +29,34 @@ */ memset(&mem_cfg->DqByteMapCh0, 0, sizeof(mem_cfg->DqByteMapCh0)); memcpy(&mem_cfg->DqByteMapCh0, &board_cfg->dq_map[DDR_CH0], - sizeof(board_cfg->dq_map[DDR_CH0])); + sizeof(board_cfg->dq_map[DDR_CH0])); memset(&mem_cfg->DqByteMapCh1, 0, sizeof(mem_cfg->DqByteMapCh1)); memcpy(&mem_cfg->DqByteMapCh1, &board_cfg->dq_map[DDR_CH1], - sizeof(board_cfg->dq_map[DDR_CH1])); + sizeof(board_cfg->dq_map[DDR_CH1])); memcpy(&mem_cfg->DqsMapCpu2DramCh0, &board_cfg->dqs_map[DDR_CH0], - sizeof(board_cfg->dqs_map[DDR_CH0])); + sizeof(board_cfg->dqs_map[DDR_CH0])); memcpy(&mem_cfg->DqsMapCpu2DramCh1, &board_cfg->dqs_map[DDR_CH1], - sizeof(board_cfg->dqs_map[DDR_CH1])); + sizeof(board_cfg->dqs_map[DDR_CH1])); memcpy(&mem_cfg->RcompResistor, &board_cfg->rcomp_resistor, - sizeof(mem_cfg->RcompResistor)); + sizeof(mem_cfg->RcompResistor)); /* Early cannonlake requires rcomp targets to be 0 */ memcpy(&mem_cfg->RcompTarget, &board_cfg->rcomp_targets, - sizeof(mem_cfg->RcompTarget)); + sizeof(mem_cfg->RcompTarget)); } -static void meminit_memcfg_spd(FSP_M_CONFIG *mem_cfg, - const struct cnl_mb_cfg *cnl_cfg, - size_t spd_data_len, uintptr_t spd_data_ptr) +/* + * Initialize default memory settings using spd data contained in a buffer. + */ +static void meminit_spd_data(FSP_M_CONFIG *mem_cfg, + const struct cnl_mb_cfg *cnl_cfg, + size_t spd_data_len, uintptr_t spd_data_ptr) { + assert(spd_data_ptr && spd_data_len); + mem_cfg->MemorySpdDataLen = spd_data_len; if (cnl_cfg->channel_empty[0] == 0) @@ -62,31 +67,20 @@ } /* - * Initialize default memory settings using spd data contained in a buffer. - */ -static void meminit_spd_data(FSP_M_CONFIG *mem_cfg, - const struct cnl_mb_cfg *cnl_cfg, - size_t spd_data_len, uintptr_t spd_data_ptr) -{ - assert(spd_data_ptr && spd_data_len); - meminit_memcfg_spd(mem_cfg, cnl_cfg, spd_data_len, spd_data_ptr); -} - -/* * Initialize default memory settings using the spd file specified by * spd_index. The spd_index is an index into the SPD_SOURCES array defined * in spd/Makefile.inc. */ static void meminit_cbfs_spd_index(FSP_M_CONFIG *mem_cfg, - const struct cnl_mb_cfg *cnl_cfg, - int spd_index) + const struct cnl_mb_cfg *cnl_cfg) { size_t spd_data_len; uintptr_t spd_data_ptr; struct region_device spd_rdev; - printk(BIOS_DEBUG, "SPD INDEX = %d\n", spd_index); - if (get_spd_cbfs_rdev(&spd_rdev, spd_index) < 0) + printk(BIOS_DEBUG, "SPD INDEX = %d\n", + cnl_cfg->spd.spd_spec.spd_index); + if (get_spd_cbfs_rdev(&spd_rdev, cnl_cfg->spd.spd_spec.spd_index) < 0) die("spd.bin not found or incorrect index\n"); spd_data_len = region_device_sz(&spd_rdev); /* Memory leak is ok since we have memory mapped boot media */ @@ -97,10 +91,8 @@ /* Initialize onboard memory configurations for CannonLake */ void cannonlake_memcfg_init(FSP_M_CONFIG *mem_cfg, - const struct cnl_mb_cfg *cnl_cfg, - const struct spd_info *spd) + const struct cnl_mb_cfg *cnl_cfg) { - bool OnModuleSpd = false; /* Early Command Training Enabled */ mem_cfg->ECT = cnl_cfg->ect; mem_cfg->DqPinsInterleaved = cnl_cfg->dq_pins_interleaved; @@ -108,24 +100,26 @@ /* Spd pointer will only be used if all smbus slave address of memory * sockets on the platform is empty */ - for (int i = 0; i < ARRAY_SIZE(mem_cfg->SpdAddressTable); i++) { - if (spd->spd_smbus_address[i] != 0) { - mem_cfg->SpdAddressTable[i] = spd->spd_smbus_address[i]; - OnModuleSpd = true; + switch (cnl_cfg->spd.read_type) { + case READ_SMBUS: + for (int i = 0; i < ARRAY_SIZE(mem_cfg->SpdAddressTable); i++) { + if (cnl_cfg->spd.spd_spec.spd_smbus_address[i]) { + mem_cfg->SpdAddressTable[i] = cnl_cfg->spd. + spd_spec.spd_smbus_address[i]; + } } - } - - if (!OnModuleSpd) { - if (spd->spd_by_index) { - meminit_cbfs_spd_index(mem_cfg, cnl_cfg, - spd->spd_spec.spd_index); - } else { - meminit_spd_data(mem_cfg, cnl_cfg, - spd->spd_spec.spd_data_ptr_info.spd_data_len, - spd->spd_spec.spd_data_ptr_info.spd_data_ptr); - } + break; + case READ_SPD_CBFS: + meminit_cbfs_spd_index(mem_cfg, cnl_cfg); + break; + case READ_SPD_MEMPTR: + meminit_spd_data(mem_cfg, cnl_cfg, + cnl_cfg->spd.spd_spec.spd_data_ptr_info.spd_data_len, + cnl_cfg->spd.spd_spec.spd_data_ptr_info.spd_data_ptr); + break; + default: + printk(BIOS_DEBUG, "No valid way to read mem info."); } meminit_memcfg(mem_cfg, cnl_cfg); - } diff --git a/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h b/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h index c602180..42d67a5 100644 --- a/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h +++ b/src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h @@ -40,17 +40,27 @@ uintptr_t spd_data_ptr; }; +enum mem_info_read_type { + NOT_EXISTING, + READ_SMBUS, + READ_SPD_CBFS, + READ_SPD_MEMPTR +}; + struct spd_info { - bool spd_by_index; + enum mem_info_read_type read_type; union spd_data_by { int spd_index; struct spd_by_pointer spd_data_ptr_info; + uint8_t spd_smbus_address[4]; } spd_spec; - uint8_t spd_smbus_address[4]; }; /* Board-specific memory dq mapping information */ struct cnl_mb_cfg { + /* Parameters required to access DRAM info. */ + struct spd_info spd; + /* * For each channel, there are 3 sets of DQ byte mappings, * where each set has a package 0 and a package 1 value (package 0 @@ -122,7 +132,6 @@ * Initialize default memory configurations for CannonLake. */ void cannonlake_memcfg_init(FSP_M_CONFIG *mem_cfg, - const struct cnl_mb_cfg *cnl_cfg, - const struct spd_info *spd); + const struct cnl_mb_cfg *cnl_cfg); #endif /* _SOC_CANNONLAKE_MEMCFG_INIT_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32513 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I686a85996858204c20fd05ef24787a0487817c34 Gerrit-Change-Number: 32513 Gerrit-PatchSet: 1 Gerrit-Owner: Philip Chen <philipchen(a)google.com> Gerrit-MessageType: newchange

7 53

Change in ...coreboot[master]: superio/ite: Add IT8786E-I
by Patrick Georgi (Code Review) 15 May '19

15 May '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30335 ) Change subject: superio/ite: Add IT8786E-I ...................................................................... superio/ite: Add IT8786E-I Based on IT8786E-I V0.4.1 datasheet with following remark: "Please note that the IT8786E-I V0.4.1 is applicable only to the D version." Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I7317da6a72db64f95f9a790ef96ed7a5f93b3aea Reviewed-on: https://review.coreboot.org/c/coreboot/+/30335 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/superio/ite/Makefile.inc A src/superio/ite/it8786e/Kconfig A src/superio/ite/it8786e/Makefile.inc A src/superio/ite/it8786e/acpi/superio.asl A src/superio/ite/it8786e/chip.h A src/superio/ite/it8786e/it8786e.h A src/superio/ite/it8786e/superio.c 7 files changed, 395 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc index 551abe9..8388c7a 100644 --- a/src/superio/ite/Makefile.inc +++ b/src/superio/ite/Makefile.inc @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2018 Libretrend LDA ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -31,3 +32,4 @@ subdirs-y += it8728f subdirs-y += it8772f subdirs-y += it8783ef +subdirs-y += it8786e diff --git a/src/superio/ite/it8786e/Kconfig b/src/superio/ite/it8786e/Kconfig new file mode 100644 index 0000000..9d3f258 --- /dev/null +++ b/src/superio/ite/it8786e/Kconfig @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 secunet Security Networks AG +## Copyright (C) 2018 Libretrend LDA +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SUPERIO_ITE_IT8786E + bool + select SUPERIO_ITE_COMMON_PRE_RAM + select SUPERIO_ITE_ENV_CTRL + select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 + select SUPERIO_ITE_ENV_CTRL_8BIT_PWM + select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG diff --git a/src/superio/ite/it8786e/Makefile.inc b/src/superio/ite/it8786e/Makefile.inc new file mode 100644 index 0000000..560957f --- /dev/null +++ b/src/superio/ite/it8786e/Makefile.inc @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 secunet Security Networks AG +## Copyright (C) 2018 Libretrend LDA +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_ITE_IT8786E) += superio.c diff --git a/src/superio/ite/it8786e/acpi/superio.asl b/src/superio/ite/it8786e/acpi/superio.asl new file mode 100644 index 0000000..f860da6 --- /dev/null +++ b/src/superio/ite/it8786e/acpi/superio.asl @@ -0,0 +1,171 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Christoph Grenz <christophg+cb(a)grenz-bonn.de> + * Copyright (C) 2013, 2016 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Include this file into a mainboard's DSDT _SB device tree and it will + * expose the IT8786E SuperIO and some of its functionality. + * + * It allows the change of IO ports, IRQs and DMA settings on logical + * devices, disabling and reenabling logical devices. + * + * LDN State + * 0x1 UARTA Implemented, untested + * 0x2 UARTB Implemented, untested + * 0x3 PP Not implemented + * 0x4 EC Not implemented + * 0x5 KBC Implemented, untested + * 0x6 MOUSE Implemented, untested + * 0x7 GPIO Not implemented + * 0x8 UARTC Implemented, untested + * 0x9 UARTD Implemented, untested + * 0xa UARTE Not implemented + * 0xb UARTF Not implemented + * 0xc CIR Not implemented + * + * Controllable through preprocessor defines: + * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) + * SUPERIO_PNP_BASE I/O address of the first PnP configuration register + * IT8786E_SHOW_UARTA If defined, UARTA will be exposed. + * IT8786E_SHOW_UARTB If defined, UARTB will be exposed. + * IT8786E_SHOW_UARTC If defined, UARTC will be exposed. + * IT8786E_SHOW_UARTD If defined, UARTD will be exposed. + * IT8786E_SHOW_KBC If defined, the KBC will be exposed. + * IT8786E_SHOW_PS2M If defined, PS/2 mouse support will be exposed. + */ + +#undef SUPERIO_CHIP_NAME +#define SUPERIO_CHIP_NAME IT8786E +#include <superio/acpi/pnp.asl> + +#undef PNP_DEFAULT_PSC +#define PNP_DEFAULT_PSC Return (0) /* no power management */ + +#define CONFIGURE_CONTROL CCTL + +Device (SUPERIO_DEV) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("ITE IT8786E Super I/O")) + Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) + + /* Mutex for accesses to the configuration ports */ + Mutex (CRMX, 1) + + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + PNP_ADDR_REG, 8, + PNP_DATA_REG, 8 + } + IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve) + { + Offset (0x02), + CONFIGURE_CONTROL, 8, /* Global configure control */ + + Offset (0x07), + PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ + + Offset (0x30), + PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ + + Offset (0x60), + PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ + PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ + Offset (0x62), + PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ + PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ + + Offset (0x70), + PNP_IRQ0, 8, /* First IRQ */ + } + + Method (_CRS) + { + /* Announce the used i/o ports to the OS */ + Return (ResourceTemplate () { + IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, + 0x01, 0x02) + }) + } + + #undef PNP_ENTER_MAGIC_1ST + #undef PNP_ENTER_MAGIC_2ND + #undef PNP_ENTER_MAGIC_3RD + #undef PNP_ENTER_MAGIC_4TH + #undef PNP_EXIT_MAGIC_1ST + #define PNP_ENTER_MAGIC_1ST 0x87 + #define PNP_ENTER_MAGIC_2ND 0x01 + #define PNP_ENTER_MAGIC_3RD 0x55 +#if SUPERIO_PNP_BASE == 0x2e + #define PNP_ENTER_MAGIC_4TH 0x55 +#else + #define PNP_ENTER_MAGIC_4TH 0xaa +#endif + #define PNP_EXIT_SPECIAL_REG CONFIGURE_CONTROL + #define PNP_EXIT_SPECIAL_VAL 0x02 + #include <superio/acpi/pnp_config.asl> + +#ifdef IT8786E_SHOW_UARTA + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 1 + #include <superio/acpi/pnp_uart.asl> +#endif + +#ifdef IT8786E_SHOW_UARTB + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 2 + #include <superio/acpi/pnp_uart.asl> +#endif + +#ifdef IT8786E_SHOW_KBC + #undef SUPERIO_KBC_LDN + #undef SUPERIO_KBC_PS2M + #undef SUPERIO_KBC_PS2LDN + #define SUPERIO_KBC_LDN 5 +#ifdef IT8786E_SHOW_PS2M + #define SUPERIO_KBC_PS2LDN 6 +#endif + #include <superio/acpi/pnp_kbc.asl> +#endif + +#ifdef IT8786E_SHOW_UARTC + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 8 + #include <superio/acpi/pnp_uart.asl> +#endif + +#ifdef IT8786E_SHOW_UARTD + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 9 + #include <superio/acpi/pnp_uart.asl> +#endif +} diff --git a/src/superio/ite/it8786e/chip.h b/src/superio/ite/it8786e/chip.h new file mode 100644 index 0000000..4b2e811 --- /dev/null +++ b/src/superio/ite/it8786e/chip.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 secunet Security Networks AG + * Copyright (C) 2019 Libretrend LDA + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ITE_IT8786E_CHIP_H +#define SUPERIO_ITE_IT8786E_CHIP_H + +#include <superio/ite/common/env_ctrl_chip.h> + +struct superio_ite_it8786e_config { + struct ite_ec_config ec; +}; + +#endif /* SUPERIO_ITE_IT8786E_CHIP_H */ diff --git a/src/superio/ite/it8786e/it8786e.h b/src/superio/ite/it8786e/it8786e.h new file mode 100644 index 0000000..5f11b63 --- /dev/null +++ b/src/superio/ite/it8786e/it8786e.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 secunet Security Networks AG + * Copyright (C) 2019 Libretrend LDA + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_ITE_IT8786E_H +#define SUPERIO_ITE_IT8786E_H + +#define IT8786E_SP1 0x01 /* COM1 */ +#define IT8786E_SP2 0x02 /* COM2 */ +#define IT8786E_PP 0x03 /* Printer port */ +#define IT8786E_EC 0x04 /* Environment controller */ +#define IT8786E_KBCK 0x05 /* Keyboard */ +#define IT8786E_KBCM 0x06 /* Mouse */ +#define IT8786E_GPIO 0x07 /* GPIO */ +#define IT8786E_SP3 0x08 /* COM3 */ +#define IT8786E_SP4 0x09 /* COM4 */ +#define IT8786E_CIR 0x0a /* Consumer IR */ +#define IT8786E_SP5 0x0b /* COM5 */ +#define IT8786E_SP6 0x0c /* COM6 */ + +#include <stdint.h> + +#endif /* SUPERIO_ITE_IT8786E_H */ diff --git a/src/superio/ite/it8786e/superio.c b/src/superio/ite/it8786e/superio.c new file mode 100644 index 0000000..ac9dc4b --- /dev/null +++ b/src/superio/ite/it8786e/superio.c @@ -0,0 +1,118 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 secunet Security Networks AG + * Copyright (C) 2019 Libretrend LDA + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> +#include <superio/conf_mode.h> +#include <superio/ite/common/env_ctrl.h> + +#include "it8786e.h" +#include "chip.h" + +static void it8786e_init(struct device *const dev) +{ + const struct superio_ite_it8786e_config *conf; + const struct resource *res; + + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + case IT8786E_EC: + conf = dev->chip_info; + res = find_resource(dev, PNP_IDX_IO0); + if (!conf || !res) + break; + ite_ec_init(res->base, &conf->ec); + break; + case IT8786E_KBCK: + pc_keyboard_init(NO_AUX_DEVICE); + break; + default: + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = it8786e_init, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + /* Serial Port 1 */ + { NULL, IT8786E_SP1, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | + PNP_MSC2, + 0x0ff8, }, + /* Serial Port 2 */ + { NULL, IT8786E_SP2, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | + PNP_MSC2, + 0x0ff8, }, + /* Printer Port */ + { NULL, IT8786E_PP, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_DRQ0 | + PNP_MSC0, + 0x0ff8, 0x0ffc, }, + /* Environmental Controller */ + { NULL, IT8786E_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0 | + PNP_MSC1 | PNP_MSC2 | PNP_MSC3 | PNP_MSC4 | + PNP_MSC5 | PNP_MSC6 | PNP_MSCA | PNP_MSCB | + PNP_MSCC, + 0x0ff8, 0x0ffc, }, + /* KBC Keyboard */ + { NULL, IT8786E_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, + 0x0fff, 0x0fff, }, + /* KBC Mouse */ + { NULL, IT8786E_KBCM, PNP_IRQ0 | PNP_MSC0, }, + /* GPIO */ + { NULL, IT8786E_GPIO, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | + PNP_MSC0 | PNP_MSC1 | PNP_MSC2 | PNP_MSC3 | + PNP_MSC4 | PNP_MSC5 | PNP_MSC6 | PNP_MSC7 | + PNP_MSC8 | PNP_MSC9 | PNP_MSCA | PNP_MSCB, + 0x0ffc, 0x0fff, }, + /* Serial Port 3 */ + { NULL, IT8786E_SP3, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | + PNP_MSC2, + 0x0ff8, }, + /* Serial Port 4 */ + { NULL, IT8786E_SP4, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | + PNP_MSC2, + 0x0ff8, }, + /* Consumer Infrared */ + { NULL, IT8786E_CIR, PNP_IO0 | PNP_IRQ0 | PNP_MSC0, 0x0ff8, }, + /* Serial Port 5 */ + { NULL, IT8786E_SP5, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | + PNP_MSC2, + 0x0ff8, }, + /* Serial Port 6 */ + { NULL, IT8786E_SP6, PNP_IO0 | PNP_IRQ0 | PNP_MSC0 | PNP_MSC1 | + PNP_MSC2, + 0x0ff8, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8786e_ops = { + CHIP_NAME("ITE IT8786E Super I/O") + .enable_dev = enable_dev, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/30335 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7317da6a72db64f95f9a790ef96ed7a5f93b3aea Gerrit-Change-Number: 30335 Gerrit-PatchSet: 8 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: src/superio/ite/common: Prepare for new SuperIO
by Michał Żygowski (Code Review) 15 May '19

15 May '19

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30553 Change subject: src/superio/ite/common: Prepare for new SuperIO ...................................................................... src/superio/ite/common: Prepare for new SuperIO Introduce 7bit Slope PWM registers. New ITE SuperIO may have contiguous 7bit values for PWM slope. Add option to enable External Sensor SMBus Host. Allow early SuperIO serial init in bootblock for platforms supporting C_ENVIRONMENT_BOOTBLOCK. Update/add registers macros for IT8786E-F which are not backwards compatible. Change-Id: I68fbfe62dfa05d0c166abaefbdc2ab873114b236 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/superio/ite/Makefile.inc M src/superio/ite/common/Kconfig M src/superio/ite/common/env_ctrl.c M src/superio/ite/common/env_ctrl.h M src/superio/ite/common/env_ctrl_chip.h 5 files changed, 53 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/30553/1 diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc index 382dbd7..a54db6f 100644 --- a/src/superio/ite/Makefile.inc +++ b/src/superio/ite/Makefile.inc @@ -14,7 +14,11 @@ ## ## include generic ite pre-ram stage driver -romstage-$(CONFIG_SUPERIO_ITE_COMMON_ROMSTAGE) += common/early_serial.c + +ifeq ($(CONFIG_SUPERIO_ITE_COMMON_ROMSTAGE),y) +bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += common/early_serial.c +romstage-y += common/early_serial.c +endif ## include generic ite environment controller driver ramstage-$(CONFIG_SUPERIO_ITE_ENV_CTRL) += common/env_ctrl.c diff --git a/src/superio/ite/common/Kconfig b/src/superio/ite/common/Kconfig index 162b7f1..fd6a699 100644 --- a/src/superio/ite/common/Kconfig +++ b/src/superio/ite/common/Kconfig @@ -41,4 +41,10 @@ help The second FAN controller has a separate frequency setting. +config SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG + bool + help + Slope PWM registers have no separate BIT6 and are set directly by + 7-bit values instead. + endif diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c index 1dc5bb6..fb347de 100644 --- a/src/superio/ite/common/env_ctrl.c +++ b/src/superio/ite/common/env_ctrl.c @@ -3,6 +3,7 @@ * * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * Copyright (C) 2016 secunet Security Networks AG + * Copyright (C) 2018 Libretrend LDA * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -164,9 +165,14 @@ pwm_ctrl |= ITE_EC_FAN_CTL_TEMPIN(conf->tmpin); pwm_start = ITE_EC_FAN_CTL_PWM_START_DUTY(conf->pwm_start); - pwm_start |= ITE_EC_FAN_CTL_PWM_SLOPE_BIT6(conf->slope); - pwm_auto = ITE_EC_FAN_CTL_PWM_SLOPE_LOWER(conf->slope); + if (IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG)) { + pwm_auto = conf->slope & 0x7f; + } else { + pwm_start |= ITE_EC_FAN_CTL_PWM_SLOPE_BIT6(conf->slope); + pwm_auto = ITE_EC_FAN_CTL_PWM_SLOPE_LOWER(conf->slope); + } + if (conf->smoothing) pwm_auto |= ITE_EC_FAN_CTL_AUTO_SMOOTHING_EN; @@ -213,7 +219,7 @@ ite_ec_write(base, ITE_EC_FAN_CTL_MODE, reg); } - if (IS_ENABLED(SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG) + if (IS_ENABLED(CONFIG_SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG) && conf->mode >= FAN_MODE_ON) { reg = ite_ec_read(base, ITE_EC_FAN_TAC_COUNTER_ENABLE); reg |= ITE_EC_FAN_TAC_16BIT_ENABLE(fan); @@ -271,6 +277,13 @@ for (i = 0; i < ITE_EC_TMPIN_CNT; ++i) enable_tmpin(base, i + 1, &conf->tmpin[i]); + /* Enable External Sensor SMBus Host if configured */ + if (conf->smbus_en) { + ite_ec_write(base, ITE_EC_INTERFACE_SELECT, + ite_ec_read(base, ITE_EC_INTERFACE_SELECT) | + ITE_EC_INTERFACE_SMB_ENABLE); + } + /* Enable reading of voltage pins */ ite_ec_write(base, ITE_EC_ADC_VOLTAGE_CHANNEL_ENABLE, conf->vin_mask); diff --git a/src/superio/ite/common/env_ctrl.h b/src/superio/ite/common/env_ctrl.h index 11316db..06a41a5 100644 --- a/src/superio/ite/common/env_ctrl.h +++ b/src/superio/ite/common/env_ctrl.h @@ -3,6 +3,7 @@ * * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * Copyright (C) 2016 secunet Security Networks AG + * Copyright (C) 2018 Libretrend LDA * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -48,13 +49,34 @@ #define ITE_EC_FAN_PWM_SMOOTHING_1KHZ (0 << 6) #define ITE_EC_FAN_PWM_SMOOTHING_256HZ (1 << 6) #define ITE_EC_FAN_PWM_SMOOTHING_64HZ (2 << 6) +#if IS_ENABLED(CONFIG_SUPERIO_ITE_IT8786E) +#define ITE_EC_FAN_PWM_SMOOTHING_16HZ (1 << 6) +#else #define ITE_EC_FAN_PWM_SMOOTHING_16HZ (3 << 6) +#endif +/* SUPERIO_ITE_IT8786E PWM_SMOOTHING_FREQ contents */ +#define ITE_EC_FAN_PWM_SMOOTHING_1HZ (0 << 6) +#define ITE_EC_FAN_PWM_SMOOTHING_8HZ (2 << 6) +#define ITE_EC_FAN_PWM_SMOOTHING_4HZ (3 << 6) +#define ITE_EC_FAN_CTL5_SEL(x) ((((x)-1) & 3) << 2) +#define ITE_EC_FAN_CTL5_SEL_NONE (3 << 2) +#define ITE_EC_FAN_CTL4_SEL(x) (((x)-1) & 3) +#define ITE_EC_FAN_CTL4_SEL_NONE (3 << 0) #define ITE_EC_FAN_TAC_COUNTER_ENABLE 0x0c #define ITE_EC_FAN_TAC_16BIT_ENABLE(x) (1 << ((x)-1)) #define ITE_EC_FAN_TAC_LIMIT(x) (0x10 + ((x)-1)) #define ITE_EC_FAN_TAC_EXT_LIMIT(x) (0x1b + ((x)-1)) +/* SUPERIO_ITE_IT8786E FAN_TAC_CNTRL register content */ +#define ITE_EC_FAN_TAC_CNTRL 0x0c +#define ITE_EC_TMPIN3_ENHANCED_INT_MODE (1 << 7) +#define ITE_EC_TMPIN2_ENHANCED_INT_MODE (1 << 6) +#define ITE_EC_FAN_TAC5_EN (1 << 5) +#define ITE_EC_FAN_TAC4_EN (1 << 4) +#define ITE_EC_TMPIN1_ENHANCED_INT_MODE (1 << 3) +#define ITE_EC_AMDTSI_ERR_EN (1 << 0) + #define ITE_EC_FAN_MAIN_CTL 0x13 #define ITE_EC_FAN_MAIN_CTL_TAC_EN(x) (1 << ((x)+3)) #define ITE_EC_FAN_MAIN_CTL_COLL_FULL_SPEED (1 << 3) @@ -130,6 +152,8 @@ #define ITE_EC_FAN_CTL_PWM_SLOPE_LOWER(s) ((s) & 0x3f) #define ITE_EC_FAN_CTL_DELTA_TEMP(x) (0x65 + ((x)-1) * 8) #define ITE_EC_FAN_CTL_DELTA_TEMP_INTRVL(c) ((c) & 0x1f) +#define ITE_EC_FAN_CTL_TARGET_ZONE(x) (0x66 + ((x)-1) * 8) +#define ITE_EC_FAN_CTL_TARGET_ZONE_MASK 0x0f #define ITE_EC_EXTEMP_STATUS 0x88 #define ITE_EC_EXTEMP_STATUS_HOST_BUSY (1 << 0) diff --git a/src/superio/ite/common/env_ctrl_chip.h b/src/superio/ite/common/env_ctrl_chip.h index f8f2e1e..4df9b01 100644 --- a/src/superio/ite/common/env_ctrl_chip.h +++ b/src/superio/ite/common/env_ctrl_chip.h @@ -3,6 +3,7 @@ * * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. * Copyright (C) 2016 secunet Security Networks AG + * Copyright (C) 2018 Libretrend LDA * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -95,6 +96,7 @@ bool tmpin_beep; bool fan_beep; bool vin_beep; + bool smbus_en; }; /* Some shorthands for device trees */ -- To view, visit https://review.coreboot.org/c/coreboot/+/30553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I68fbfe62dfa05d0c166abaefbdc2ab873114b236 Gerrit-Change-Number: 30553 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

4 7

Change in ...coreboot[master]: util/inteltool: Add Kabylake E3-1200 MSRs
by Christian Walter (Code Review) 15 May '19

15 May '19

Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32619 Change subject: util/inteltool: Add Kabylake E3-1200 MSRs ...................................................................... util/inteltool: Add Kabylake E3-1200 MSRs Signed-off-by: Christian Walter <christian.walter(a)9elements.com> Change-Id: I5c55102d7ce15dbb708e9433500ebd1ed53179ad --- M util/inteltool/cpu.c 1 file changed, 349 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/32619/1 diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index c40a3bd..e985df7 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -1529,6 +1529,354 @@ { 0x416, "MSR_MC5_ADDR" }, }; +/* + * Intel 64 and IA-32 Architectures Software Developers Manual Conbined Volumes + * Page 4668 + * + * The following two tables are for the Kaby Lake processors + * 06_9EH. + * + */ + + static const msr_entry_t model96ex_global_msrs[] = { + { 0x0000, "IA32_PLATFORM_ID"}, + { 0x0080, "MSR_TRACE_HUB_STH_ACPIBAR_BASE"}, + { 0x00CE, "MSR_PLATFORM_INFO"}, + { 0x0198, "IA32_PERF_STATUS"}, + { 0x01A2, "MSR_TEMPERATURE_TARGET"}, + { 0x01AD, "MSR_TURBO_RATIO_LIMIT"}, + { 0x0180, "IA32_ENERGY_PERF_BIAS"}, + { 0x0181, "IA32_PACKAGE_THERM_STATUS"}, + { 0x0182, "IA32_PACKAGE_THERM_INTERRUPT"}, + { 0x0284, "IA32_MC4_CTL2"}, + { 0x02F4, "MSR_UNCORE_PRMRR_PHYS_BASE"}, + { 0x02F5, "MSR_UNCORE_PRMRR_PHYS_MASK"}, + { 0x0300, "MSR_SFXOWNEREPOCH0"}, + { 0x0301, "MSR_SGXOWNEREPOCH1"}, + { 0x0394, "MSR_UNC_PERF_FIXED_CTRL"}, + { 0x0395, "MSR_UNC_PERF_FIXED_CTR"}, + /*{ 0x03F8, "MSR_PKG_C3_RESIDENCY"}, + { 0x03F9, "MSR_PKG_C6_RESIDENCY"}, + { 0x03FA, "MSR_PKG_C7_RESIDENCY"}, + { 0x0606, "MSR_RAPL_POWER_UNIT"}, */ + { 0x060A, "MSR_PKGC3_IRTL"}, + { 0x060B, "MSR_PKGC6_IRTL"}, + { 0x060D, "MSR_PKG_C2_RESIDENCY"}, + { 0x0610, "MSR_PKG_POWER_LIMIT"}, + { 0x0614, "MSR_PKG_POWER_INFO"}, + { 0x0620, "MSR_RING_RATIO_LIMIT"}, + { 0x0638, "MSR_PP0_POWER_LIMIT"}, + /*{ 0x0639, "MSR_PKG_ENERGY_STATUS"}, + { 0x064D, "MSR_PLATFORM_ENERGY_COUNTER"}*/ + { 0x064F, "MSR_CORE_PERF_LIMIT_REASONS"}, + { 0x0652, "MSR_PKG_HDC_CONFIG"}, + /*{ 0x0653, "MSR_CORE_HDC_RESIDENCY"}, + { 0x0655, "MSR_PKG_HDC_SHALLOW_RESIDENCY"}, + { 0x0656, "MSR_PKG_HDC_DEEP_RESIDENCY"}, + { 0x0658, "MSR_WEIGHTED_CORE_C0"}, + { 0x0659, "MSR_ANY_CORE_C0"}, + { 0x065A, "MSR_ANY_GFXE_C0"}, + { 0x065B, "MSR_CORE_GFXE_OVERLAP_C0"}, */ + { 0x065C, "MSR_PLATFORM_POWER_LIMIT"}, + { 0x06B0, "MSR_GRAPHICS_PERF_LIMIT_REASONS"}, + { 0x06B1, "MSR_RING_PERF_LIMIT_REASONS"}, + { 0x0770, "IA32_PM_ENABLE"}, + { 0x0772, "IA32_HWP_REQUEST_PKG"}, + { 0x0DB0, "IA32_PKG_HDC_CTL"}, + { 0x03B0, "MSR_UNC_ARB_PERFCTR0"}, + { 0x03B1, "MSR_UNC_ARB_PERFCTR1"}, + { 0x03B2, "MSR_UNC_ARB_PERFEVTSEL0"}, + { 0x03B3, "MSR_UNC_ARB_PERFEVTSEL1"}, + { 0x0700, "MSR_UNC_CBO_0_PERFCTR0"}, + { 0x0701, "MSR_UNC_CBO_0_PERFCTR1"}, + { 0x0706, "MSR_UNC_CBO_0_PERFEVTSEL0"}, + { 0x0707, "MSR_UNC_CBO_0_PERFEVTSEL1"}, + { 0x0710, "MSR_UNC_CBO_1_PERFCTR0"}, + { 0x0711, "MSR_UNC_CBO_1_PERFCTR1"}, + { 0x0716, "MSR_UNC_CBO_1_PERFEVTSEL0"}, + { 0x0717, "MSR_UNC_CBO_1_PERFEVTSEL1"}, + { 0x0720, "MSR_UNC_CBO_2_PERFCTR0"}, + { 0x0721, "MSR_UNC_CBO_2_PERFCTR1"}, + { 0x0726, "MSR_UNC_CBO_2_PERFEVTSEL0"}, + { 0x0727, "MSR_UNC_CBO_2_PERFEVTSEL1"}, + { 0x0730, "MSR_UNC_CBO_3_PERFCTR0"}, + { 0x0731, "MSR_UNC_CBO_3_PERFCTR1"}, + { 0x0736, "MSR_UNC_CBO_3_PERFEVTSEL0"}, + { 0x0737, "MSR_UNC_CBO_3_PERFEVTSEL1"}, + { 0x0E01, "MSR_UNC_PERF_GLOBAL_CTRL"}, + { 0x0E02, "MSR_UNC_PERF_GLOBAL_STATUS"}, + }; + + static const msr_entry_t model96ex_per_core_msrs[] = { + /* Per core MSRs for Sandy Bridge and above */ + { 0x0000, "IA32_P5_MC_ADDR"}, + { 0x0001, "IA32_P5_MC_TYPE"}, + { 0x0006, "IA32_MONITOR_FILTER_SIZE"}, + { 0x0010, "IA32_TIME_STAMP_COUNTER"}, + { 0x0018, "IA32_APIC_BASE"}, + { 0x0034, "MSR_SMI_COUNT"}, + { 0x003A, "IA32_FEATURE_CONTROL"}, + { 0x008B, "IA32_BIOS_SIGN_ID"}, + { 0x00C1, "IA32_PMC0" }, + { 0x00C2, "IA32_PMC1" }, + { 0x00C3, "IA32_PMC2" }, + { 0x00C4, "IA32_PMC3" }, + { 0x00C5, "IA32_PMC4" }, + { 0x00C6, "IA32_PMC5" }, + { 0x00C7, "IA32_PMC6" }, + { 0x00C8, "IA32_PMC7" }, + { 0x00E2, "MSR_PKG_CST_CONFIG_CONTROL" }, + { 0x00E4, "MSR_PMG_IO_CAPTURE_BASE"}, + { 0x00E7, "IA32_MPERF"}, + { 0x00E8, "IA32_APERF"}, + { 0x00FE, "IA32_MTRRCAP"}, + { 0x013C, "MSR_FEATURE_CONFIG"}, + { 0x0174, "IA32_SYSENTER_CS"}, + { 0x0175, "IA32_SYSENTER_ESP"}, + { 0x0176, "IA32_SYSENTER_EIP"}, + { 0x0179, "IA32_MCG_CAP"}, + { 0x017A, "IA32_MCG_STATUS"}, + { 0x0186, "IA32_PERFEVTSEL0"}, + { 0x0187, "IA32_PERFEVTSEL1"}, + { 0x0188, "IA32_PERFEVTSEL2"}, + { 0x0189, "IA32_PERFEVTSEL3"}, + { 0x018A, "IA32_PERFEVTSEL4"}, + { 0x018B, "IA32_PERFEVTSEL5"}, + { 0x018C, "IA32_PERFEVTSEL6"}, + { 0x018D, "IA32_PERFEVTSEL7"}, + { 0x0199, "IA32_PERF_CTL"}, + { 0x019A, "IA32_CLOCK_MODULATION"}, + { 0x019B, "IA32_THERM_INTERRUPT"}, + { 0x019C, "IA32_THERM_STATUS"}, + { 0x01A0, "IA32_MISC_ENABLE"}, + { 0x01A4, "IA32_MISC_FEATURE_CONTROL"}, + { 0x01A6, "MSR_OFFCORE_RSP_0"}, + { 0x01A7, "MSR_OFFCORE_RSP_1"}, + { 0x01C8, "MSR_LBR_SELECT"}, + { 0x01C9, "MSR_LASTBRANCH_TOS"}, + { 0x01D9, "IA32_DEBUGCTL"}, + { 0x01DD, "MSR_LER_FROM_LIP"}, + { 0x01DE, "MSR_LER_TO_LIP"}, + { 0x01F2, "IA32_SMRR_PHYSBASE"}, + { 0x01F3, "IA32_SMRR_PHYSMASK"}, + { 0x01F4, "MSR_PRMRR_PHYS_BASE"}, + { 0x01F5, "MSR_PRMRR_PHYS_MASK"}, + { 0x01F4, "MSR_PRMRR_PHYS_BASE"}, + { 0x01FB, "MSR_PRMRR_VALID_CONFIG"}, + { 0x01FC, "MSR_POWER_CTL"}, + { 0x0200, "IA32_MTRR_PHYSBASE0"}, + { 0x0201, "IA32_MTRR_PHYSBASE0"}, + { 0x0202, "IA32_MTRR_PHYSBASE1"}, + { 0x0203, "IA32_MTRR_PHYSBASE1"}, + { 0x0204, "IA32_MTRR_PHYSBASE2"}, + { 0x0205, "IA32_MTRR_PHYSBASE2"}, + { 0x0206, "IA32_MTRR_PHYSBASE3"}, + { 0x0207, "IA32_MTRR_PHYSBASE3"}, + { 0x0208, "IA32_MTRR_PHYSBASE4"}, + { 0x0209, "IA32_MTRR_PHYSBASE4"}, + { 0x020A, "IA32_MTRR_PHYSBASE5"}, + { 0x020B, "IA32_MTRR_PHYSBASE5"}, + { 0x020C, "IA32_MTRR_PHYSBASE6"}, + { 0x020D, "IA32_MTRR_PHYSBASE6"}, + { 0x020E, "IA32_MTRR_PHYSBASE7"}, + { 0x020F, "IA32_MTRR_PHYSBASE7"}, + { 0x0210, "IA32_MTRR_PHYSBASE8"}, + { 0x0211, "IA32_MTRR_PHYSBASE8"}, + { 0x0212, "IA32_MTRR_PHYSBASE9"}, + { 0x0213, "IA32_MTRR_PHYSBASE9"}, + { 0x0250, "IA32_MTRR_FIX64K_00000"}, + { 0x0258, "IA32_MTRR_FIX16K_80000"}, + { 0x0259, "IA32_MTRR_FIX16K_A0000"}, + { 0x0268, "IA32_MTRR_FIX4K_C0000"}, + { 0x0269, "IA32_MTRR_FIX4K_C8000"}, + { 0x026A, "IA32_MTRR_FIX4K_D0000"}, + { 0x026B, "IA32_MTRR_FIX4K_D8000"}, + { 0x026C, "IA32_MTRR_FIX4K_E0000"}, + { 0x026D, "IA32_MTRR_FIX4K_E8000"}, + { 0x026E, "IA32_MTRR_FIX4K_F0000"}, + { 0x026F, "IA32_MTRR_FIX4K_F8000"}, + { 0x0277, "IA32_PAT"}, + { 0x0280, "IA32_MC0_CTL2"}, + { 0x0281, "IA32_MC1_CTL2"}, + { 0x0282, "IA32_MC2_CTL2"}, + { 0x0283, "IA32_MC3_CTL2"}, + { 0x02FF, "IA32_MTRR_DEF_TYPE"}, + { 0x0309, "IA32_FIXED_CTR0"}, + { 0x030A, "IA32_FIXED_CTR1"}, + { 0x030B, "IA32_FIXED_CTR2"}, + { 0x0345, "IA32_PERF_CAPABILITIES"}, + { 0x038D, "IA32_FIXED_CTR_CTRL"}, + { 0x038E, "IA32_PERF_GLOBAL_STATUS"}, + { 0x038F, "IA32_PERF_GLOBAL_CTRL"}, + { 0x0390, "IA32_PERF_GLOBAL_STATUS_RESET"}, + { 0x0391, "IA32_PERF_GLOBAL_STATUS_SET"}, + { 0x03F1, "MSR_PEBS_ENABLE"}, + { 0x03F6, "MSR_PEBS_LD_LAT"}, + { 0x03F7, "MSR_PEBS_FRONTEND"}, + { 0x03FC, "MSR_CORE_C3_RESIDENCY"}, + { 0x03FD, "MSR_CORE_C6_RESIDENCY"}, + { 0x03FE, "MSR_CORE_C7_RESIDENCY"}, + { 0x0400, "IA32_MC0_CTL" }, + { 0x0401, "IA32_MC0_STATUS" }, + { 0x0402, "IA32_MC0_ADDR" }, + { 0x0403, "IA32_MC0_MISC" }, + { 0x0404, "IA32_MC1_CTL" }, + { 0x0405, "IA32_MC1_STATUS" }, + { 0x0406, "IA32_MC1_ADDR" }, + { 0x0407, "IA32_MC1_MISC" }, + { 0x0408, "IA32_MC2_CTL" }, + { 0x0409, "IA32_MC2_STATUS" }, + { 0x040a, "IA32_MC2_ADDR" }, + { 0x040c, "IA32_MC3_CTL" }, + { 0x040d, "IA32_MC3_STATUS" }, + { 0x040e, "IA32_MC3_ADDR" }, + { 0x0410, "IA32_MC4_CTL" }, + { 0x0411, "IA32_MC4_STATUS" }, + { 0x0480, "IA32_VMX_BASIC" }, + { 0x0481, "IA32_VMX_PINBASED_CTLS" }, + { 0x0482, "IA32_VMX_PROCBASED_CTLS" }, + { 0x0483, "IA32_VMX_EXIT_CTLS" }, + { 0x0484, "IA32_VMX_ENTRY_CTLS" }, + { 0x0485, "IA32_VMX_MISC" }, + { 0x0486, "IA32_VMX_CR0_FIXED0" }, + { 0x0487, "IA32_VMX_CR0_FIXED1" }, + { 0x0488, "IA32_VMX_CR4_FIXED0" }, + { 0x0489, "IA32_VMX_CR4_FIXED1" }, + { 0x048a, "IA32_VMX_VMCS_ENUM" }, + { 0x048b, "IA32_VMX_PROCBASED_CTLS2" }, + { 0x048c, "IA32_VMX_EPT_VPID_ENUM" }, + { 0x048d, "IA32_VMX_TRUE_PINBASED_CTLS" }, + { 0x048e, "IA32_VMX_TRUE_PROCBASED_CTLS" }, + { 0x048f, "IA32_VMX_TRUE_EXIT_CTLS" }, + { 0x0490, "IA32_VMX_TRUE_ENTRY_CTLS" }, + { 0x04C1, "IA32_A_PMC0"}, + { 0x04C2, "IA32_A_PMC1"}, + { 0x04C3, "IA32_A_PMC2"}, + { 0x04C4, "IA32_A_PMC3"}, + { 0x04C5, "IA32_A_PMC4"}, + { 0x04C6, "IA32_A_PMC5"}, + { 0x04C7, "IA32_A_PMC6"}, + { 0x04C8, "IA32_A_PMC7"}, + { 0x0500, "IA32_SGX_SVN_STATUS"}, + { 0x0560, "IA32_RTIT_OUTPUT_BASE"}, + { 0x0561, "IA32_RTIT_OUTPUT_MASK_PTRS"}, + { 0x0570, "IA32_RTIT_CTL"}, + { 0x0571, "IA32_RTIT_STATUS"}, + { 0x0572, "IA32_RTIT_CR3_MATCH"}, + { 0x0580, "IA32_RTIT_ADDR0_A"}, + { 0x0581, "IA32_RTIT_ADDR0_B"}, + { 0x0582, "IA32_RTIT_ADDR1_A"}, + { 0x0583, "IA32_RTIT_ADDR1_B"}, + { 0x0600, "IA32_DS_AREA" }, + { 0x064E, "MSR_PPERF"}, + { 0x0653, "MSR_CORE_HDC_RESIDENCY"}, + { 0x0680, "MSR_LASTBRANCH_0_FROM_IP" }, + { 0x0681, "MSR_LASTBRANCH_1_FROM_IP" }, + { 0x0682, "MSR_LASTBRANCH_2_FROM_IP" }, + { 0x0683, "MSR_LASTBRANCH_3_FROM_IP" }, + { 0x0684, "MSR_LASTBRANCH_4_FROM_IP" }, + { 0x0685, "MSR_LASTBRANCH_5_FROM_IP" }, + { 0x0686, "MSR_LASTBRANCH_6_FROM_IP" }, + { 0x0687, "MSR_LASTBRANCH_7_FROM_IP" }, + { 0x0688, "MSR_LASTBRANCH_8_FROM_IP" }, + { 0x0689, "MSR_LASTBRANCH_9_FROM_IP" }, + { 0x068a, "MSR_LASTBRANCH_10_FROM_IP" }, + { 0x068b, "MSR_LASTBRANCH_11_FROM_IP" }, + { 0x068c, "MSR_LASTBRANCH_12_FROM_IP" }, + { 0x068d, "MSR_LASTBRANCH_13_FROM_IP" }, + { 0x068e, "MSR_LASTBRANCH_14_FROM_IP" }, + { 0x068f, "MSR_LASTBRANCH_15_FROM_IP" }, + { 0x0690, "MSR_LASTBRANCH_16_FROM_IP" }, + { 0x0691, "MSR_LASTBRANCH_17_FROM_IP" }, + { 0x0692, "MSR_LASTBRANCH_18_FROM_IP" }, + { 0x0693, "MSR_LASTBRANCH_19_FROM_IP" }, + { 0x0694, "MSR_LASTBRANCH_20_FROM_IP" }, + { 0x0695, "MSR_LASTBRANCH_21_FROM_IP" }, + { 0x0696, "MSR_LASTBRANCH_22_FROM_IP" }, + { 0x0697, "MSR_LASTBRANCH_23_FROM_IP" }, + { 0x0698, "MSR_LASTBRANCH_24_FROM_IP" }, + { 0x0699, "MSR_LASTBRANCH_25_FROM_IP" }, + { 0x069A, "MSR_LASTBRANCH_26_FROM_IP" }, + { 0x069B, "MSR_LASTBRANCH_27_FROM_IP" }, + { 0x069C, "MSR_LASTBRANCH_28_FROM_IP" }, + { 0x069D, "MSR_LASTBRANCH_29_FROM_IP" }, + { 0x069E, "MSR_LASTBRANCH_30_FROM_IP" }, + { 0x069F, "MSR_LASTBRANCH_31_FROM_IP" }, + { 0x06c0, "MSR_LASTBRANCH_0_TO_IP" }, + { 0x06c1, "MSR_LASTBRANCH_1_TO_IP" }, + { 0x06c2, "MSR_LASTBRANCH_2_TO_IP" }, + { 0x06c3, "MSR_LASTBRANCH_3_TO_IP" }, + { 0x06c4, "MSR_LASTBRANCH_4_TO_IP" }, + { 0x06c5, "MSR_LASTBRANCH_5_TO_IP" }, + { 0x06c6, "MSR_LASTBRANCH_6_TO_IP" }, + { 0x06c7, "MSR_LASTBRANCH_7_TO_IP" }, + { 0x06c8, "MSR_LASTBRANCH_8_TO_IP" }, + { 0x06c9, "MSR_LASTBRANCH_9_TO_IP" }, + { 0x06ca, "MSR_LASTBRANCH_10_TO_IP" }, + { 0x06cb, "MSR_LASTBRANCH_11_TO_IP" }, + { 0x06cc, "MSR_LASTBRANCH_12_TO_IP" }, + { 0x06cd, "MSR_LASTBRANCH_13_TO_IP" }, + { 0x06ce, "MSR_LASTBRANCH_14_TO_IP" }, + { 0x06cf, "MSR_LASTBRANCH_15_TO_IP" }, + { 0x06d0, "MSR_LASTBRANCH_16_FROM_IP" }, + { 0x06d1, "MSR_LASTBRANCH_17_FROM_IP" }, + { 0x06d2, "MSR_LASTBRANCH_18_FROM_IP" }, + { 0x06d3, "MSR_LASTBRANCH_19_FROM_IP" }, + { 0x06d4, "MSR_LASTBRANCH_20_FROM_IP" }, + { 0x06d5, "MSR_LASTBRANCH_21_FROM_IP" }, + { 0x06d6, "MSR_LASTBRANCH_22_FROM_IP" }, + { 0x06d7, "MSR_LASTBRANCH_23_FROM_IP" }, + { 0x06d8, "MSR_LASTBRANCH_24_FROM_IP" }, + { 0x06d9, "MSR_LASTBRANCH_25_FROM_IP" }, + { 0x06da, "MSR_LASTBRANCH_26_FROM_IP" }, + { 0x06db, "MSR_LASTBRANCH_27_FROM_IP" }, + { 0x06dc, "MSR_LASTBRANCH_28_FROM_IP" }, + { 0x06dd, "MSR_LASTBRANCH_29_FROM_IP" }, + { 0x06de, "MSR_LASTBRANCH_30_FROM_IP" }, + { 0x06df, "MSR_LASTBRANCH_31_FROM_IP" }, + { 0x06E0, "IA32_TSC_DEADLINE"}, + { 0x0771, "IA32_HWP_CAPABILITIES"}, + { 0x0773, "IA32_HWP_INTERRUPT"}, + { 0x0774, "IA32_HWP_REQUEST"}, + { 0x0777, "IA32_HWP_STATUS"}, + { 0x0D90, "IA32_BNDCFGS"}, + { 0x0DA0, "IA32_XSS"}, + { 0x0DB1, "IA32_PM_CTL1"}, + { 0x0DB2, "IA32_THREAD_STALL"}, + { 0x0DC0, "IA32_LBR_INFO_0"}, + { 0x0DC1, "IA32_LBR_INFO_1"}, + { 0x0DC2, "IA32_LBR_INFO_2"}, + { 0x0DC3, "IA32_LBR_INFO_3"}, + { 0x0DC4, "IA32_LBR_INFO_4"}, + { 0x0DC5, "IA32_LBR_INFO_5"}, + { 0x0DC6, "IA32_LBR_INFO_6"}, + { 0x0DC7, "IA32_LBR_INFO_7"}, + { 0x0DC8, "IA32_LBR_INFO_8"}, + { 0x0DC9, "IA32_LBR_INFO_9"}, + { 0x0DCA, "IA32_LBR_INFO_10"}, + { 0x0DCB, "IA32_LBR_INFO_11"}, + { 0x0DCC, "IA32_LBR_INFO_12"}, + { 0x0DCD, "IA32_LBR_INFO_13"}, + { 0x0DCE, "IA32_LBR_INFO_14"}, + { 0x0DCF, "IA32_LBR_INFO_15"}, + { 0x0DD0, "IA32_LBR_INFO_16"}, + { 0x0DD1, "IA32_LBR_INFO_17"}, + { 0x0DD2, "IA32_LBR_INFO_18"}, + { 0x0DD3, "IA32_LBR_INFO_19"}, + { 0x0DD4, "IA32_LBR_INFO_20"}, + { 0x0DD5, "IA32_LBR_INFO_21"}, + { 0x0DD6, "IA32_LBR_INFO_22"}, + { 0x0DD7, "IA32_LBR_INFO_23"}, + { 0x0DD8, "IA32_LBR_INFO_24"}, + { 0x0DD9, "IA32_LBR_INFO_25"}, + { 0x0DDA, "IA32_LBR_INFO_26"}, + { 0x0DDB, "IA32_LBR_INFO_27"}, + { 0x0DDC, "IA32_LBR_INFO_28"}, + { 0x0DDD, "IA32_LBR_INFO_29"}, + { 0x0DDE, "IA32_LBR_INFO_30"}, + { 0x0DDF, "IA32_LBR_INFO_31"}, + }; + typedef struct { unsigned int model; const msr_entry_t *global_msrs; @@ -1547,6 +1895,7 @@ { 0x00f60, modelf6x_global_msrs, ARRAY_SIZE(modelf6x_global_msrs), modelf6x_per_core_msrs, ARRAY_SIZE(modelf6x_per_core_msrs) }, { 0x106c0, model6_atom_global_msrs, ARRAY_SIZE(model6_atom_global_msrs), model6_atom_per_core_msrs, ARRAY_SIZE(model6_atom_per_core_msrs) }, { 0x20650, model20650_global_msrs, ARRAY_SIZE(model20650_global_msrs), model20650_per_core_msrs, ARRAY_SIZE(model20650_per_core_msrs) }, + { 0x906e0, model96ex_global_msrs, ARRAY_SIZE(model96ex_global_msrs), model96ex_per_core_msrs, ARRAY_SIZE(model96ex_per_core_msrs) }, { CPUID_BAYTRAIL, silvermont_global_msrs, ARRAY_SIZE(silvermont_global_msrs), silvermont_per_core_msrs, ARRAY_SIZE(silvermont_per_core_msrs) }, /* Baytrail */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32619 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5c55102d7ce15dbb708e9433500ebd1ed53179ad Gerrit-Change-Number: 32619 Gerrit-PatchSet: 1 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-MessageType: newchange

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coreboot-gerrit May 2019