coreboot-gerrit May 2019

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Change in ...coreboot[master]: Documentation/lessons/lesson2.md: Add reminder to check username set
by Alan Green (Code Review) 15 May '19

15 May '19

Alan Green has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32540 Change subject: Documentation/lessons/lesson2.md: Add reminder to check username set ...................................................................... Documentation/lessons/lesson2.md: Add reminder to check username set If username is not set, then the ssh option is not available. This was initially confusing for me. Signed-off-by: Alan Green <avg(a)google.com> Change-Id: I731c29a1daa9f8c298710471c7d1fe758b059d08 --- M Documentation/lessons/lesson2.md 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/32540/1 diff --git a/Documentation/lessons/lesson2.md b/Documentation/lessons/lesson2.md index d6f800c..6a2dd29 100644 --- a/Documentation/lessons/lesson2.md +++ b/Documentation/lessons/lesson2.md @@ -68,6 +68,10 @@ coreboot" and run the "clone with commit-msg hook" command that's provided. This should prompt you for your id_rsa passphrase, if you previously set one. +**Note:** if the **ssh** option is not showing, check that you have a username +set. Click the profile picture at the top right and select **User Setttings**, +then set your username in the **Profile** section. + If you are using HTTP, instead, select **http** from the tabs under "Project coreboot" and run the command that appears -- To view, visit https://review.coreboot.org/c/coreboot/+/32540 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I731c29a1daa9f8c298710471c7d1fe758b059d08 Gerrit-Change-Number: 32540 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/stoneyridge: Add ACPI D3Cold support for SD Controller
by Raul Rangel (Code Review) 15 May '19

15 May '19

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32433 Change subject: soc/amd/stoneyridge: Add ACPI D3Cold support for SD Controller ...................................................................... soc/amd/stoneyridge: Add ACPI D3Cold support for SD Controller We need to support entering D3Cold from the OS to workaround a bug in the SDHC where the data lines get stuck always reading zeros. BUG=b:122749418 TEST=Verified the linux kernel can transition between D3 and D0 Change-Id: Ifbf48f20c03a752ce3ff773296b536e92db16a62 Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> --- M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl 1 file changed, 34 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/32433/1 diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 15e4d2f..2139f8d 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -56,6 +56,16 @@ /* 0:14.7 - SD Controller */ Device(SDCN) { Name(_ADR, 0x00140007) + + Method(_PS0) { + FDDC(24, 0) + } + Method(_PS3) { + FDDC(24, 3) + } + Method(_PSC) { + Return(SDTD) + } } /* end SDCN */ Name(CRES, ResourceTemplate() { @@ -286,8 +296,9 @@ offset (0x1e70), /* SD D3 Control */ SDTD, 2, , 1, + SDPD, 1, , 1, - , 2, + , 1, SDRT, 1, SDSC, 1, @@ -433,7 +444,17 @@ /* todo Case(15) { STD0()} */ /* SATA */ Case(18) { U2D0()} /* EHCI */ Case(23) { U3D0()} /* XHCI */ -/* todo Case(24) { SDD0()} */ /* SD */ + Case(24) { + /* Enable Power */ + Store(One, SDPD) + Store(SDDS, Local0) + while(LNotEqual(Local0,0x7)) { + Store(SDDS, Local0) + } + + /* D0-uninitialized */ + Store(0x00, SDTD) + } } } else { /* put device into D3cold */ @@ -489,7 +510,17 @@ /* todo Case(15) { STD3()} */ /* SATA */ Case(18) { U2D3()} /* EHCI */ Case(23) { U3D3()} /* XHCI */ -/* todo Case(24) { SDD3()} */ /* SD */ + Case(24) { + /* Disable power */ + Store(Zero, SDPD) + Store(SDDS, Local0) + while(LNotEqual(Local0,0x0)) { + Store(SDDS, Local0) + } + + /* D3 */ + Store(0x03, SDTD) + } } /* Turn off Power */ if(LEqual(I0TD, 3)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/32433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbf48f20c03a752ce3ff773296b536e92db16a62 Gerrit-Change-Number: 32433 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Use !ENV_PAYLOAD_LOADER to select __SIMPLE_DEVICE__
by Subrata Banik (Code Review) 15 May '19

15 May '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32765 Change subject: Use !ENV_PAYLOAD_LOADER to select __SIMPLE_DEVICE__ ...................................................................... Use !ENV_PAYLOAD_LOADER to select __SIMPLE_DEVICE__ This patch removes multiple(defined(__PRE_RAM__) || ENV_SMM || ENV_POSTCAR) checks to enable __SIMPLE_DEVICE__. Change-Id: Ide61ec2c908758ba96c61ca9ed7278e7d11d1ee5 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/include/rules.h 1 file changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/32765/1 diff --git a/src/include/rules.h b/src/include/rules.h index ce968f0..1effe3f 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -262,17 +262,16 @@ #define ENV_PAYLOAD_LOADER ENV_RAMSTAGE /** - * For pre-DRAM stages and post-CAR always build with simple device model, ie. - * PCI, PNP and CPU functions operate without use of devicetree. The reason - * post-CAR utilizes __SIMPLE_DEVICE__ is for simplicity. Currently there's - * no known requirement that devicetree would be needed during that stage. + * !ENV_PAYLOAD_LOADER enable stages always build with simple device model, + * ie. PCI, PNP and CPU functions operate without use of devicetree. The reason + * post-CAR utilizes __SIMPLE_DEVICE__ is for simplicity. * * For ramstage individual source file may define __SIMPLE_DEVICE__ * before including any header files to force that particular source * be built with simple device model. */ -#if (defined(__PRE_RAM__) || ENV_SMM || ENV_POSTCAR) +#if !ENV_PAYLOAD_LOADER #define __SIMPLE_DEVICE__ #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/32765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide61ec2c908758ba96c61ca9ed7278e7d11d1ee5 Gerrit-Change-Number: 32765 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: libpayload: Add UART for qcs405
by Patrick Georgi (Code Review) 15 May '19

15 May '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29957 ) Change subject: libpayload: Add UART for qcs405 ...................................................................... Patch Set 23: (1 comment) https://review.coreboot.org/#/c/29957/20/payloads/libpayload/drivers/serial… File payloads/libpayload/drivers/serial/qcs405.c: https://review.coreboot.org/#/c/29957/20/payloads/libpayload/drivers/serial… PS20, Line 544: /* For simplicity sake let's rely on coreboot initalizing the UART. */ > We are seeing issues if we remove the initialization (line #552). […] It would be worth investigating what's going on there, but feel free to leave line 552 in, but then remove this comment, or add a TODO comment to denote that this is still being pursued. -- To view, visit https://review.coreboot.org/c/coreboot/+/29957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43164cf9eacc844af1d048f7b6ebbda96fc9d202 Gerrit-Change-Number: 29957 Gerrit-PatchSet: 23 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Prudhvi Yarlagadda <pyarlaga(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Wed, 15 May 2019 14:43:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Prudhvi Yarlagadda <pyarlaga(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405: util/qualcomm: Add T32 debug scripts
by Patrick Georgi (Code Review) 15 May '19

15 May '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29951 ) Change subject: qcs405: util/qualcomm: Add T32 debug scripts ...................................................................... Patch Set 23: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/29951 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e792a2806e5ebd3b4075c7bb69c43587920deae Gerrit-Change-Number: 29951 Gerrit-PatchSet: 23 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Wed, 15 May 2019 14:40:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405: Enable SPI-NOR
by Patrick Georgi (Code Review) 15 May '19

15 May '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29968 ) Change subject: qcs405: Enable SPI-NOR ...................................................................... Patch Set 24: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/29968/24//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29968/24//COMMIT_MSG@9 PS24, Line 9: WINBOND Nit: also Gigadevice -- To view, visit https://review.coreboot.org/c/coreboot/+/29968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I340eb3bf77b25fe3502d4b29ef4bf7c06b282c02 Gerrit-Change-Number: 29968 Gerrit-PatchSet: 24 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 15 May 2019 14:39:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb,soc/intel: Fix flashconsole on older architectures
by Matt DeVillier (Code Review) 15 May '19

15 May '19

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21107 ) Change subject: sb,soc/intel: Fix flashconsole on older architectures ...................................................................... Patch Set 14: I just pushed a working rebase, I didn't look to closely at what was/wasn't needed any longer. I'll try to clean things up a bit better in the next few days -- To view, visit https://review.coreboot.org/c/coreboot/+/21107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd3e8621fa4cb349b7e0e07118cab0380f24ff55 Gerrit-Change-Number: 21107 Gerrit-PatchSet: 14 Gerrit-Owner: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 15 May 2019 14:17:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb,soc/intel: Fix flashconsole on older architectures
by Patrick Rudolph (Code Review) 15 May '19

15 May '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21107 ) Change subject: sb,soc/intel: Fix flashconsole on older architectures ...................................................................... Patch Set 14: Was partly fixed here: I4671653c0b07ab5c4bf91128f18f142ce4f893cf -- To view, visit https://review.coreboot.org/c/coreboot/+/21107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd3e8621fa4cb349b7e0e07118cab0380f24ff55 Gerrit-Change-Number: 21107 Gerrit-PatchSet: 14 Gerrit-Owner: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 15 May 2019 11:49:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb,soc/intel: Fix flashconsole on older architectures
by Patrick Rudolph (Code Review) 15 May '19

15 May '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/21107 ) Change subject: sb,soc/intel: Fix flashconsole on older architectures ...................................................................... Patch Set 14: Code-Review-1 (3 comments) https://review.coreboot.org/#/c/21107/14//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/21107/14//COMMIT_MSG@12 PS14, Line 12: build/romstage/drivers/spi/spi-generic.o: In function `spi_setup_slave': I don't have this error at master https://review.coreboot.org/#/c/21107/14//COMMIT_MSG@17 PS14, Line 17: This is due to the fact that sb/intel/common/spi.c is currently not built not true https://review.coreboot.org/#/c/21107/14/src/southbridge/intel/common/spi.c File src/southbridge/intel/common/spi.c: https://review.coreboot.org/#/c/21107/14/src/southbridge/intel/common/spi.c… PS14, Line 19: #include <arch/early_variables.h> why? -- To view, visit https://review.coreboot.org/c/coreboot/+/21107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd3e8621fa4cb349b7e0e07118cab0380f24ff55 Gerrit-Change-Number: 21107 Gerrit-PatchSet: 14 Gerrit-Owner: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 15 May 2019 11:48:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK
by Nico Huber (Code Review) 15 May '19

15 May '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30383 ) Change subject: soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK ...................................................................... Patch Set 49: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935 Gerrit-Change-Number: 30383 Gerrit-PatchSet: 49 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 15 May 2019 10:08:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit May 2019