coreboot-gerrit May 2019

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Change in ...coreboot[master]: mb/google/poppy/vr/atlas: Add a W/A for Samsung memory init error
by Gaggery Tsai (Code Review) 15 May '19

15 May '19

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32695 Change subject: mb/google/poppy/vr/atlas: Add a W/A for Samsung memory init error ...................................................................... mb/google/poppy/vr/atlas: Add a W/A for Samsung memory init error This patch adds a workaround for Samsung C-die 2G/4G memory chips. For unknown reasons, some boards with Samsung LP3 memory chips could not pass early CS/CMD training. MRC has to change the granularity from 16 ticks to 8 ticks, which implies bad margin with this memory chip. Another way is to enhance the drive strength for CS. This patch is to enhance the drive strength for CS. Root cause needs to be further investigated with memory vendor. BUG=b:131177542 BRANCH=None TEST=USE=fw_debug emerge-atlas chromeos-mrc coreboot chromeos-bootimage & check the MRC log to ensure correct Rcomp values are passed to MRC. Tested with board ID #8 and #11. Change-Id: I9ea3ceda8dc8bf781063d3c16c7c2d9b44e5ddd6 Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> --- M src/mainboard/google/poppy/variants/atlas/memory.c 1 file changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/32695/1 diff --git a/src/mainboard/google/poppy/variants/atlas/memory.c b/src/mainboard/google/poppy/variants/atlas/memory.c index 0b34e72..7b0d17a 100644 --- a/src/mainboard/google/poppy/variants/atlas/memory.c +++ b/src/mainboard/google/poppy/variants/atlas/memory.c @@ -13,8 +13,11 @@ * GNU General Public License for more details. */ +#include <assert.h> #include <baseboard/variants.h> +#define SAMSUNG_C_DIE_2G 10 +#define SAMSUNG_C_DIE_4G 11 /* DQ byte map */ static const u8 dq_map[][12] = { { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, @@ -34,9 +37,12 @@ /* Rcomp target */ static const u16 rcomp_target[] = { 100, 40, 40, 23, 40 }; +static const u16 rcomp_target_samsung_c_die[] = { 100, 40, 40, 18, 40 }; void variant_memory_params(struct memory_params *p) { + int spd_index; + p->type = MEMORY_LPDDR3; p->dq_map = dq_map; p->dq_map_size = sizeof(dq_map); @@ -44,6 +50,11 @@ p->dqs_map_size = sizeof(dqs_map); p->rcomp_resistor = rcomp_resistor; p->rcomp_resistor_size = sizeof(rcomp_resistor); - p->rcomp_target = rcomp_target; + spd_index = variant_memory_sku(); + assert(spd_index >= 0); + if (spd_index == SAMSUNG_C_DIE_2G || spd_index == SAMSUNG_C_DIE_4G) + p->rcomp_target = rcomp_target_samsung_c_die; + else + p->rcomp_target = rcomp_target; p->rcomp_target_size = sizeof(rcomp_target); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32695 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ea3ceda8dc8bf781063d3c16c7c2d9b44e5ddd6 Gerrit-Change-Number: 32695 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK
by Nico Huber (Code Review) 15 May '19

15 May '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30383 ) Change subject: soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK ...................................................................... Patch Set 48: -Code-Review (1 comment) Matt, I think I found something to test :) https://review.coreboot.org/#/c/30383/48/src/soc/intel/broadwell/romstage/r… File src/soc/intel/broadwell/romstage/romstage.c: https://review.coreboot.org/#/c/30383/48/src/soc/intel/broadwell/romstage/r… PS48, Line 72: Losing the initialization of `pei_data` here. Maybe memset() the whole struct or `= { 0 };`? -- To view, visit https://review.coreboot.org/c/coreboot/+/30383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935 Gerrit-Change-Number: 30383 Gerrit-PatchSet: 48 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 14 May 2019 23:27:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/broadwell: Clean up the bootflow
by Arthur Heymans (Code Review) 15 May '19

15 May '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32760 Change subject: soc/intel/broadwell: Clean up the bootflow ...................................................................... soc/intel/broadwell: Clean up the bootflow Call the raminit from a common location instead of from the mainboard specific code. Change-Id: I65d522237a0bb7b2c032536ede10e2cf93c134d8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/auron/romstage.c M src/mainboard/google/jecht/romstage.c M src/mainboard/google/slippy/romstage.c M src/mainboard/intel/wtm2/romstage.c M src/mainboard/purism/librem_bdw/romstage.c M src/soc/intel/broadwell/include/soc/romstage.h M src/soc/intel/broadwell/romstage/romstage.c 7 files changed, 18 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/32760/1 diff --git a/src/mainboard/google/auron/romstage.c b/src/mainboard/google/auron/romstage.c index 5e1a66a..d56f357 100644 --- a/src/mainboard/google/auron/romstage.c +++ b/src/mainboard/google/auron/romstage.c @@ -27,7 +27,7 @@ { } -void mainboard_romstage_entry(struct romstage_params *rp) +void mainboard_pre_raminit(struct romstage_params *rp) { struct pei_data pei_data; @@ -38,10 +38,10 @@ mainboard_fill_pei_data(&pei_data); mainboard_fill_spd_data(&pei_data); rp->pei_data = &pei_data; +} - /* Call into the real romstage main with this board's attributes. */ - romstage_common(rp); - +void mainboard_post_raminit(struct romstage_params *rp) +{ /* Do variant-specific init */ variant_romstage_entry(rp); } diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c index de0ed30..e906666 100644 --- a/src/mainboard/google/jecht/romstage.c +++ b/src/mainboard/google/jecht/romstage.c @@ -27,7 +27,7 @@ #include "onboard.h" -void mainboard_romstage_entry(struct romstage_params *rp) +void mainboard_pre_raminit(struct romstage_params *rp) { struct pei_data pei_data; @@ -38,10 +38,10 @@ mainboard_fill_pei_data(&pei_data); mainboard_fill_spd_data(&pei_data); rp->pei_data = &pei_data; +} - /* Call into the real romstage main with this board's attributes. */ - romstage_common(rp); - +void mainboard_post_raminit(struct romstage_params *rp) +{ if (CONFIG(CHROMEOS)) init_bootmode_straps(); } diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index ec5d5ea..efa3a07 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -20,5 +20,5 @@ void mainboard_romstage_entry(unsigned long bist) { - variant_romstage_entry(bist); + variant_romstage_entry(bist); } diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c index de4237d..223621a 100644 --- a/src/mainboard/intel/wtm2/romstage.c +++ b/src/mainboard/intel/wtm2/romstage.c @@ -22,7 +22,7 @@ #include <soc/pei_wrapper.h> #include <soc/romstage.h> -void mainboard_romstage_entry(struct romstage_params *rp) +void mainboard_pre_raminit(struct romstage_params *rp) { struct pei_data pei_data; @@ -32,6 +32,4 @@ memset(&pei_data, 0, sizeof(pei_data)); mainboard_fill_pei_data(&pei_data); rp->pei_data = &pei_data; - - romstage_common(rp); } diff --git a/src/mainboard/purism/librem_bdw/romstage.c b/src/mainboard/purism/librem_bdw/romstage.c index 6591229..9aae83f 100644 --- a/src/mainboard/purism/librem_bdw/romstage.c +++ b/src/mainboard/purism/librem_bdw/romstage.c @@ -26,7 +26,4 @@ memset(&pei_data, 0, sizeof(pei_data)); mainboard_fill_pei_data(&pei_data); rp->pei_data = &pei_data; - - /* Initialize memory */ - romstage_common(rp); } diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h index 31184f9..fd95e92 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/soc/intel/broadwell/include/soc/romstage.h @@ -27,7 +27,8 @@ struct pei_data *pei_data; }; -void mainboard_romstage_entry(struct romstage_params *params); +void mainboard_pre_raminit(struct romstage_params *params); +void mainboard_post_raminit(struct romstage_params *params); void romstage_common(struct romstage_params *params); void raminit(struct pei_data *pei_data); diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 7847829..8ad8513 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -104,8 +104,12 @@ /* Initialize GPIOs */ init_gpios(mainboard_gpio_config); - /* Call into mainboard. */ - mainboard_romstage_entry(&rp); + /* Fill in mainboard pei_date. */ + mainboard_pre_raminit(&rp); + + romstage_common(&rp); + + mainboard_post_raminit(&rp); platform_enter_postcar(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32760 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65d522237a0bb7b2c032536ede10e2cf93c134d8 Gerrit-Change-Number: 32760 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/broadwell: Don't use a pointer for pei_data
by Arthur Heymans (Code Review) 15 May '19

15 May '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32762 Change subject: soc/intel/broadwell: Don't use a pointer for pei_data ...................................................................... soc/intel/broadwell: Don't use a pointer for pei_data To improve the bootflow, the scope of the pei_data needs to be extended. Change-Id: Ic6d91692a7bf9218b81da5bb36b5b26dabac454e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/auron/romstage.c M src/mainboard/google/jecht/romstage.c M src/mainboard/intel/wtm2/romstage.c M src/mainboard/purism/librem_bdw/romstage.c M src/soc/intel/broadwell/include/soc/romstage.h M src/soc/intel/broadwell/romstage/romstage.c 6 files changed, 13 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/32762/1 diff --git a/src/mainboard/google/auron/romstage.c b/src/mainboard/google/auron/romstage.c index 5e1a66a..4974899 100644 --- a/src/mainboard/google/auron/romstage.c +++ b/src/mainboard/google/auron/romstage.c @@ -29,15 +29,11 @@ void mainboard_romstage_entry(struct romstage_params *rp) { - struct pei_data pei_data; - post_code(0x32); /* Fill out PEI DATA */ - memset(&pei_data, 0, sizeof(pei_data)); - mainboard_fill_pei_data(&pei_data); - mainboard_fill_spd_data(&pei_data); - rp->pei_data = &pei_data; + mainboard_fill_pei_data(&rp->pei_data); + mainboard_fill_spd_data(&rp->pei_data); /* Call into the real romstage main with this board's attributes. */ romstage_common(rp); diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c index de0ed30..8d1ae8a 100644 --- a/src/mainboard/google/jecht/romstage.c +++ b/src/mainboard/google/jecht/romstage.c @@ -29,15 +29,11 @@ void mainboard_romstage_entry(struct romstage_params *rp) { - struct pei_data pei_data; - post_code(0x32); /* Fill out PEI DATA */ - memset(&pei_data, 0, sizeof(pei_data)); - mainboard_fill_pei_data(&pei_data); - mainboard_fill_spd_data(&pei_data); - rp->pei_data = &pei_data; + mainboard_fill_pei_data(&rp->pei_data); + mainboard_fill_spd_data(&rp->pei_data); /* Call into the real romstage main with this board's attributes. */ romstage_common(rp); diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c index de4237d..d74572d 100644 --- a/src/mainboard/intel/wtm2/romstage.c +++ b/src/mainboard/intel/wtm2/romstage.c @@ -24,14 +24,11 @@ void mainboard_romstage_entry(struct romstage_params *rp) { - struct pei_data pei_data; - post_code(0x32); /* Fill out PEI DATA */ - memset(&pei_data, 0, sizeof(pei_data)); - mainboard_fill_pei_data(&pei_data); - rp->pei_data = &pei_data; + mainboard_fill_pei_data(&rp->pei_data); + mainboard_fill_spd_data(&rp->pei_data); romstage_common(rp); } diff --git a/src/mainboard/purism/librem_bdw/romstage.c b/src/mainboard/purism/librem_bdw/romstage.c index 6591229..1e84abe 100644 --- a/src/mainboard/purism/librem_bdw/romstage.c +++ b/src/mainboard/purism/librem_bdw/romstage.c @@ -20,12 +20,9 @@ void mainboard_romstage_entry(struct romstage_params *rp) { - struct pei_data pei_data; - /* Fill out PEI DATA */ - memset(&pei_data, 0, sizeof(pei_data)); - mainboard_fill_pei_data(&pei_data); - rp->pei_data = &pei_data; + mainboard_fill_pei_data(&rp->pei_data); + mainboard_fill_spd_data(&rp->pei_data); /* Initialize memory */ romstage_common(rp); diff --git a/src/soc/intel/broadwell/include/soc/romstage.h b/src/soc/intel/broadwell/include/soc/romstage.h index 31184f9..b78555c 100644 --- a/src/soc/intel/broadwell/include/soc/romstage.h +++ b/src/soc/intel/broadwell/include/soc/romstage.h @@ -18,13 +18,15 @@ #include <stdint.h> #include <arch/cpu.h> +#include <soc/pm.h> +#include <soc/pei_data.h> struct chipset_power_state; struct pei_data; struct romstage_params { unsigned long bist; struct chipset_power_state *power_state; - struct pei_data *pei_data; + struct pei_data pei_data; }; void mainboard_romstage_entry(struct romstage_params *params); diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 7847829..2a3ac8b 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -68,7 +68,6 @@ { struct romstage_params rp = { .bist = bist, - .pei_data = NULL, }; post_code(0x30); @@ -125,7 +124,7 @@ timestamp_add_now(TS_BEFORE_INITRAM); - params->pei_data->boot_mode = params->power_state->prev_sleep_state; + params->pei_data.boot_mode = params->power_state->prev_sleep_state; #if CONFIG(ELOG_BOOT_COUNT) if (params->power_state->prev_sleep_state != ACPI_S3) @@ -140,7 +139,7 @@ &params->power_state->hsio_checksum); /* Initialize RAM */ - raminit(params->pei_data); + raminit(&params->pei_data); timestamp_add_now(TS_AFTER_INITRAM); -- To view, visit https://review.coreboot.org/c/coreboot/+/32762 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic6d91692a7bf9218b81da5bb36b5b26dabac454e Gerrit-Change-Number: 32762 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

3 7

Change in ...coreboot[master]: soc/intel/broadwell: Move GPIO init to a common place
by Nico Huber (Code Review) 15 May '19

15 May '19

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32759 ) Change subject: soc/intel/broadwell: Move GPIO init to a common place ...................................................................... soc/intel/broadwell: Move GPIO init to a common place This also links the gpio configuration instead of including it as a header. Change-Id: I9309d2b842495f6cff33fdab18aa139a82c1959c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32759 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/auron/Makefile.inc M src/mainboard/google/auron/romstage.c R src/mainboard/google/auron/variants/auron_paine/gpio.c D src/mainboard/google/auron/variants/auron_paine/include/variant/gpio.h M src/mainboard/google/auron/variants/auron_paine/spd/spd.c C src/mainboard/google/auron/variants/auron_yuna/gpio.c M src/mainboard/google/auron/variants/auron_yuna/spd/spd.c R src/mainboard/google/auron/variants/buddy/gpio.c R src/mainboard/google/auron/variants/gandof/gpio.c M src/mainboard/google/auron/variants/gandof/spd/spd.c R src/mainboard/google/auron/variants/lulu/gpio.c M src/mainboard/google/auron/variants/lulu/spd/spd.c R src/mainboard/google/auron/variants/samus/gpio.c M src/mainboard/google/auron/variants/samus/spd/spd.c M src/mainboard/google/jecht/Makefile.inc M src/mainboard/google/jecht/romstage.c R src/mainboard/google/jecht/variants/guado/gpio.c R src/mainboard/google/jecht/variants/jecht/gpio.c R src/mainboard/google/jecht/variants/rikku/gpio.c R src/mainboard/google/jecht/variants/tidus/gpio.c M src/mainboard/intel/wtm2/Makefile.inc R src/mainboard/intel/wtm2/gpio.c M src/mainboard/intel/wtm2/romstage.c M src/mainboard/purism/librem_bdw/Makefile.inc R src/mainboard/purism/librem_bdw/gpio.c M src/mainboard/purism/librem_bdw/romstage.c M src/soc/intel/broadwell/include/soc/gpio.h M src/soc/intel/broadwell/romstage/romstage.c 28 files changed, 25 insertions(+), 216 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Matt DeVillier: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/auron/Makefile.inc b/src/mainboard/google/auron/Makefile.inc index 170e168..c81aeaf 100644 --- a/src/mainboard/google/auron/Makefile.inc +++ b/src/mainboard/google/auron/Makefile.inc @@ -32,3 +32,5 @@ subdirs-y += variants/$(VARIANT_DIR)/spd CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +romstage-y += variants/$(VARIANT_DIR)/gpio.c diff --git a/src/mainboard/google/auron/romstage.c b/src/mainboard/google/auron/romstage.c index aea8e21..5e1a66a 100644 --- a/src/mainboard/google/auron/romstage.c +++ b/src/mainboard/google/auron/romstage.c @@ -17,11 +17,9 @@ #include <console/console.h> #include <string.h> #include <ec/google/chromeec/ec.h> -#include <soc/gpio.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> #include <soc/romstage.h> -#include <variant/gpio.h> #include <variant/spd.h> #include "variant.h" @@ -35,9 +33,6 @@ post_code(0x32); - /* Initialize GPIOs */ - init_gpios(mainboard_gpio_config); - /* Fill out PEI DATA */ memset(&pei_data, 0, sizeof(pei_data)); mainboard_fill_pei_data(&pei_data); diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/gpio.h b/src/mainboard/google/auron/variants/auron_paine/gpio.c similarity index 96% rename from src/mainboard/google/auron/variants/auron_yuna/include/variant/gpio.h rename to src/mainboard/google/auron/variants/auron_paine/gpio.c index eca65d1..e8b6c06 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/include/variant/gpio.h +++ b/src/mainboard/google/auron/variants/auron_paine/gpio.c @@ -13,12 +13,9 @@ * GNU General Public License for more details. */ -#ifndef AURON_YUNA_GPIO_H -#define AURON_YUNA_GPIO_H - #include <soc/gpio.h> -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ PCH_GPIO_UNUSED, /* 1: UNUSED */ PCH_GPIO_UNUSED, /* 2: UNUSED */ @@ -116,5 +113,3 @@ PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/gpio.h b/src/mainboard/google/auron/variants/auron_paine/include/variant/gpio.h deleted file mode 100644 index 44b930a..0000000 --- a/src/mainboard/google/auron/variants/auron_paine/include/variant/gpio.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef AURON_PAINE_GPIO_H -#define AURON_PAINE_GPIO_H - -#include <soc/gpio.h> - -static const struct gpio_config mainboard_gpio_config[] = { - PCH_GPIO_UNUSED, /* 0: UNUSED */ - PCH_GPIO_UNUSED, /* 1: UNUSED */ - PCH_GPIO_UNUSED, /* 2: UNUSED */ - PCH_GPIO_UNUSED, /* 3: UNUSED */ - PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ - PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ - PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ - PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ - PCH_GPIO_ACPI_SCI, /* 8: LTE_WAKE_L_Q */ - PCH_GPIO_INPUT, /* 9: RAM_ID1 */ - PCH_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ - PCH_GPIO_UNUSED, /* 11: UNUSED */ - PCH_GPIO_INPUT_INVERT, /* 12: TRACKPAD_INT_L (WAKE) */ - PCH_GPIO_INPUT, /* 13: RAM_ID0 */ - PCH_GPIO_INPUT, /* 14: EC_IN_RW */ - PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ - PCH_GPIO_UNUSED, /* 16: UNUSED */ - PCH_GPIO_UNUSED, /* 17: UNUSED */ - PCH_GPIO_NATIVE, /* 18: PCIE_CLKREQ_WLAN# */ - PCH_GPIO_UNUSED, /* 19: UNUSED */ - PCH_GPIO_UNUSED, /* 20: UNUSED */ - PCH_GPIO_UNUSED, /* 21: UNUSED */ - PCH_GPIO_UNUSED, /* 22: UNUSED */ - PCH_GPIO_UNUSED, /* 23: UNUSED */ - PCH_GPIO_UNUSED, /* 24: UNUSED */ - PCH_GPIO_INPUT_INVERT, /* 25: TOUCH_INT_L (WAKE) */ - PCH_GPIO_UNUSED, /* 26: UNUSED */ - PCH_GPIO_UNUSED, /* 27: UNUSED */ - PCH_GPIO_UNUSED, /* 28: UNUSED */ - PCH_GPIO_UNUSED, /* 29: UNUSED */ - PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */ - PCH_GPIO_NATIVE, /* 31: NATIVE: ACPRESENT */ - PCH_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */ - PCH_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ - PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ - PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ - PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ - PCH_GPIO_UNUSED, /* 37: UNUSED */ - PCH_GPIO_UNUSED, /* 38: UNUSED */ - PCH_GPIO_UNUSED, /* 39: UNUSED */ - PCH_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */ - PCH_GPIO_UNUSED, /* 41: UNUSED */ - PCH_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */ - PCH_GPIO_UNUSED, /* 43: UNUSED */ - PCH_GPIO_OUT_HIGH, /* 44: PP3300_SSD_EN */ - PCH_GPIO_OUT_HIGH, /* 45: PP3300_CODEC_EN */ - PCH_GPIO_OUT_HIGH, /* 46: WLAN_DISABLE_L */ - PCH_GPIO_INPUT, /* 47: RAM_ID2 */ - PCH_GPIO_UNUSED, /* 48: UNUSED */ - PCH_GPIO_UNUSED, /* 49: UNUSED */ - PCH_GPIO_UNUSED, /* 50: UNUSED */ - PCH_GPIO_INPUT, /* 51: ALS_INT_L */ - PCH_GPIO_INPUT, /* 52: SIM_DET */ - PCH_GPIO_PIRQ, /* 53: TRACKPAD_INT_DX */ - PCH_GPIO_PIRQ, /* 54: TOUCH_INT_L_DX */ - PCH_GPIO_UNUSED, /* 55: UNUSED */ - PCH_GPIO_UNUSED, /* 56: UNUSED */ - PCH_GPIO_OUT_HIGH, /* 57: PP3300_CCD_EN */ - PCH_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ - PCH_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */ - PCH_GPIO_NATIVE, /* 60: NATIVE: SML0ALERT */ - PCH_GPIO_UNUSED, /* 61: UNUSED */ - PCH_GPIO_UNUSED, /* 62: UNUSED */ - PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ - PCH_GPIO_UNUSED, /* 64: UNUSED */ - PCH_GPIO_UNUSED, /* 65: UNUSED */ - PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */ - PCH_GPIO_UNUSED, /* 67: UNUSED */ - PCH_GPIO_UNUSED, /* 68: UNUSED */ - PCH_GPIO_UNUSED, /* 69: UNUSED */ - PCH_GPIO_UNUSED, /* 70: UNUSED */ - PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ - PCH_GPIO_NATIVE, /* 72: NATIVE: PCH_BATLOW# */ - PCH_GPIO_NATIVE, /* 73: NATIVE: SMB1ALERT# */ - PCH_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */ - PCH_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */ - PCH_GPIO_UNUSED, /* 76: UNUSED */ - PCH_GPIO_UNUSED, /* 77: UNUSED */ - PCH_GPIO_UNUSED, /* 78: UNUSED */ - PCH_GPIO_UNUSED, /* 79: UNUSED */ - PCH_GPIO_UNUSED, /* 80: UNUSED */ - PCH_GPIO_NATIVE, /* 81: NATIVE: SPKR */ - PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ - PCH_GPIO_UNUSED, /* 83: UNUSED */ - PCH_GPIO_UNUSED, /* 84: UNUSED */ - PCH_GPIO_UNUSED, /* 85: UNUSED */ - PCH_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ - PCH_GPIO_UNUSED, /* 87: UNUSED */ - PCH_GPIO_UNUSED, /* 88: UNUSED */ - PCH_GPIO_UNUSED, /* 89: UNUSED */ - PCH_GPIO_UNUSED, /* 90: UNUSED */ - PCH_GPIO_UNUSED, /* 91: UNUSED */ - PCH_GPIO_UNUSED, /* 92: UNUSED */ - PCH_GPIO_UNUSED, /* 93: UNUSED */ - PCH_GPIO_UNUSED, /* 94: UNUSED */ - PCH_GPIO_END -}; - -#endif diff --git a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c index 12c876e..2991d15 100644 --- a/src/mainboard/google/auron/variants/auron_paine/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_paine/spd/spd.c @@ -22,7 +22,6 @@ #include <soc/romstage.h> #include <ec/google/chromeec/ec.h> #include <mainboard/google/auron/ec.h> -#include <variant/gpio.h> #include <variant/spd.h> static void mainboard_print_spd_info(uint8_t spd[]) diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/gpio.h b/src/mainboard/google/auron/variants/auron_yuna/gpio.c similarity index 96% copy from src/mainboard/google/auron/variants/auron_yuna/include/variant/gpio.h copy to src/mainboard/google/auron/variants/auron_yuna/gpio.c index eca65d1..e8b6c06 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/include/variant/gpio.h +++ b/src/mainboard/google/auron/variants/auron_yuna/gpio.c @@ -13,12 +13,9 @@ * GNU General Public License for more details. */ -#ifndef AURON_YUNA_GPIO_H -#define AURON_YUNA_GPIO_H - #include <soc/gpio.h> -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ PCH_GPIO_UNUSED, /* 1: UNUSED */ PCH_GPIO_UNUSED, /* 2: UNUSED */ @@ -116,5 +113,3 @@ PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c index 12c876e..2991d15 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c +++ b/src/mainboard/google/auron/variants/auron_yuna/spd/spd.c @@ -22,7 +22,6 @@ #include <soc/romstage.h> #include <ec/google/chromeec/ec.h> #include <mainboard/google/auron/ec.h> -#include <variant/gpio.h> #include <variant/spd.h> static void mainboard_print_spd_info(uint8_t spd[]) diff --git a/src/mainboard/google/auron/variants/buddy/include/variant/gpio.h b/src/mainboard/google/auron/variants/buddy/gpio.c similarity index 97% rename from src/mainboard/google/auron/variants/buddy/include/variant/gpio.h rename to src/mainboard/google/auron/variants/buddy/gpio.c index efa720f..fbb682a 100644 --- a/src/mainboard/google/auron/variants/buddy/include/variant/gpio.h +++ b/src/mainboard/google/auron/variants/buddy/gpio.c @@ -14,12 +14,9 @@ * GNU General Public License for more details. */ -#ifndef BUDDY_GPIO_H -#define BUDDY_GPIO_H - #include <soc/gpio.h> -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ PCH_GPIO_UNUSED, /* 1: UNUSED */ PCH_GPIO_UNUSED, /* 2: UNUSED */ @@ -117,5 +114,3 @@ PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/gpio.h b/src/mainboard/google/auron/variants/gandof/gpio.c similarity index 96% rename from src/mainboard/google/auron/variants/gandof/include/variant/gpio.h rename to src/mainboard/google/auron/variants/gandof/gpio.c index 68fe4a0..3de9a0b 100644 --- a/src/mainboard/google/auron/variants/gandof/include/variant/gpio.h +++ b/src/mainboard/google/auron/variants/gandof/gpio.c @@ -13,12 +13,9 @@ * GNU General Public License for more details. */ -#ifndef GANDOF_GPIO_H -#define GANDOF_GPIO_H - #include <soc/gpio.h> -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ PCH_GPIO_UNUSED, /* 1: UNUSED */ PCH_GPIO_UNUSED, /* 2: UNUSED */ @@ -116,5 +113,3 @@ PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/google/auron/variants/gandof/spd/spd.c b/src/mainboard/google/auron/variants/gandof/spd/spd.c index 12c876e..2991d15 100644 --- a/src/mainboard/google/auron/variants/gandof/spd/spd.c +++ b/src/mainboard/google/auron/variants/gandof/spd/spd.c @@ -22,7 +22,6 @@ #include <soc/romstage.h> #include <ec/google/chromeec/ec.h> #include <mainboard/google/auron/ec.h> -#include <variant/gpio.h> #include <variant/spd.h> static void mainboard_print_spd_info(uint8_t spd[]) diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/gpio.h b/src/mainboard/google/auron/variants/lulu/gpio.c similarity index 97% rename from src/mainboard/google/auron/variants/lulu/include/variant/gpio.h rename to src/mainboard/google/auron/variants/lulu/gpio.c index 726dcc7..a46c4d4 100644 --- a/src/mainboard/google/auron/variants/lulu/include/variant/gpio.h +++ b/src/mainboard/google/auron/variants/lulu/gpio.c @@ -14,12 +14,9 @@ * GNU General Public License for more details. */ -#ifndef LULU_GPIO_H -#define LULU_GPIO_H - #include <soc/gpio.h> -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ PCH_GPIO_UNUSED, /* 1: UNUSED */ PCH_GPIO_UNUSED, /* 2: UNUSED */ @@ -117,5 +114,3 @@ PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/google/auron/variants/lulu/spd/spd.c b/src/mainboard/google/auron/variants/lulu/spd/spd.c index ac99f5c..bd76947 100644 --- a/src/mainboard/google/auron/variants/lulu/spd/spd.c +++ b/src/mainboard/google/auron/variants/lulu/spd/spd.c @@ -23,7 +23,6 @@ #include <soc/romstage.h> #include <ec/google/chromeec/ec.h> #include <mainboard/google/auron/ec.h> -#include <variant/gpio.h> #include <variant/spd.h> static void mainboard_print_spd_info(uint8_t spd[]) diff --git a/src/mainboard/google/auron/variants/samus/include/variant/gpio.h b/src/mainboard/google/auron/variants/samus/gpio.c similarity index 97% rename from src/mainboard/google/auron/variants/samus/include/variant/gpio.h rename to src/mainboard/google/auron/variants/samus/gpio.c index 8362a4d..72ddcb2 100644 --- a/src/mainboard/google/auron/variants/samus/include/variant/gpio.h +++ b/src/mainboard/google/auron/variants/samus/gpio.c @@ -13,12 +13,9 @@ * GNU General Public License for more details. */ -#ifndef SAMUS_GPIO_H -#define SAMUS_GPIO_H - #include <soc/gpio.h> -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ PCH_GPIO_UNUSED, /* 1: UNUSED */ PCH_GPIO_UNUSED, /* 2: UNUSED */ @@ -116,5 +113,3 @@ PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/google/auron/variants/samus/spd/spd.c b/src/mainboard/google/auron/variants/samus/spd/spd.c index dd632f3..ffb90f9 100644 --- a/src/mainboard/google/auron/variants/samus/spd/spd.c +++ b/src/mainboard/google/auron/variants/samus/spd/spd.c @@ -22,7 +22,6 @@ #include <soc/romstage.h> #include <ec/google/chromeec/ec.h> #include <mainboard/google/auron/ec.h> -#include <variant/gpio.h> #include <variant/spd.h> static void mainboard_print_spd_info(uint8_t spd[]) diff --git a/src/mainboard/google/jecht/Makefile.inc b/src/mainboard/google/jecht/Makefile.inc index 01914ba..39e9b33 100644 --- a/src/mainboard/google/jecht/Makefile.inc +++ b/src/mainboard/google/jecht/Makefile.inc @@ -27,3 +27,5 @@ subdirs-y += variants/$(VARIANT_DIR) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +romstage-y += variants/$(VARIANT_DIR)/gpio.c diff --git a/src/mainboard/google/jecht/romstage.c b/src/mainboard/google/jecht/romstage.c index 3705feb..de0ed30 100644 --- a/src/mainboard/google/jecht/romstage.c +++ b/src/mainboard/google/jecht/romstage.c @@ -18,14 +18,12 @@ #include <console/console.h> #include <string.h> #include <ec/google/chromeec/ec.h> -#include <soc/gpio.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> #include <soc/romstage.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8772f/it8772f.h> #include <mainboard/google/jecht/spd/spd.h> -#include <variant/gpio.h> #include "onboard.h" @@ -35,9 +33,6 @@ post_code(0x32); - /* Initialize GPIOs */ - init_gpios(mainboard_gpio_config); - /* Fill out PEI DATA */ memset(&pei_data, 0, sizeof(pei_data)); mainboard_fill_pei_data(&pei_data); diff --git a/src/mainboard/google/jecht/variants/guado/include/variant/gpio.h b/src/mainboard/google/jecht/variants/guado/gpio.c similarity index 97% rename from src/mainboard/google/jecht/variants/guado/include/variant/gpio.h rename to src/mainboard/google/jecht/variants/guado/gpio.c index 4c167e3..60e769d 100644 --- a/src/mainboard/google/jecht/variants/guado/include/variant/gpio.h +++ b/src/mainboard/google/jecht/variants/guado/gpio.c @@ -13,12 +13,9 @@ * GNU General Public License for more details. */ -#ifndef GUADO_GPIO_H -#define GUADO_GPIO_H - #include <soc/gpio.h> -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ PCH_GPIO_UNUSED, /* 1: UNUSED */ PCH_GPIO_UNUSED, /* 2: UNUSED */ @@ -116,5 +113,3 @@ PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/google/jecht/variants/jecht/include/variant/gpio.h b/src/mainboard/google/jecht/variants/jecht/gpio.c similarity index 97% rename from src/mainboard/google/jecht/variants/jecht/include/variant/gpio.h rename to src/mainboard/google/jecht/variants/jecht/gpio.c index 94e6516..6a2a64c 100644 --- a/src/mainboard/google/jecht/variants/jecht/include/variant/gpio.h +++ b/src/mainboard/google/jecht/variants/jecht/gpio.c @@ -13,12 +13,9 @@ * GNU General Public License for more details. */ -#ifndef JECHT_GPIO_H -#define JECHT_GPIO_H - #include <soc/gpio.h> -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ PCH_GPIO_UNUSED, /* 1: UNUSED */ PCH_GPIO_UNUSED, /* 2: UNUSED */ @@ -116,5 +113,3 @@ PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/google/jecht/variants/rikku/include/variant/gpio.h b/src/mainboard/google/jecht/variants/rikku/gpio.c similarity index 97% rename from src/mainboard/google/jecht/variants/rikku/include/variant/gpio.h rename to src/mainboard/google/jecht/variants/rikku/gpio.c index f58ad24..bc065a0 100644 --- a/src/mainboard/google/jecht/variants/rikku/include/variant/gpio.h +++ b/src/mainboard/google/jecht/variants/rikku/gpio.c @@ -13,12 +13,9 @@ * GNU General Public License for more details. */ -#ifndef RIKKU_GPIO_H -#define RIKKU_GPIO_H - #include <soc/gpio.h> -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ PCH_GPIO_UNUSED, /* 1: UNUSED */ PCH_GPIO_UNUSED, /* 2: UNUSED */ @@ -116,5 +113,3 @@ PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/google/jecht/variants/tidus/include/variant/gpio.h b/src/mainboard/google/jecht/variants/tidus/gpio.c similarity index 97% rename from src/mainboard/google/jecht/variants/tidus/include/variant/gpio.h rename to src/mainboard/google/jecht/variants/tidus/gpio.c index 846fe81..78aa177 100644 --- a/src/mainboard/google/jecht/variants/tidus/include/variant/gpio.h +++ b/src/mainboard/google/jecht/variants/tidus/gpio.c @@ -13,12 +13,9 @@ * GNU General Public License for more details. */ -#ifndef TIDUS_GPIO_H -#define TIDUS_GPIO_H - #include <soc/gpio.h> -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 0: UNUSED */ PCH_GPIO_UNUSED, /* 1: UNUSED */ PCH_GPIO_UNUSED, /* 2: UNUSED */ @@ -116,5 +113,3 @@ PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/intel/wtm2/Makefile.inc b/src/mainboard/intel/wtm2/Makefile.inc index 1613746..4c944f2 100644 --- a/src/mainboard/intel/wtm2/Makefile.inc +++ b/src/mainboard/intel/wtm2/Makefile.inc @@ -13,6 +13,8 @@ ## GNU General Public License for more details. ## +romstage-y += gpio.c + romstage-y += chromeos.c ramstage-y += chromeos.c diff --git a/src/mainboard/intel/wtm2/gpio.h b/src/mainboard/intel/wtm2/gpio.c similarity index 97% rename from src/mainboard/intel/wtm2/gpio.h rename to src/mainboard/intel/wtm2/gpio.c index 9e6f2e6..c81ad10 100644 --- a/src/mainboard/intel/wtm2/gpio.h +++ b/src/mainboard/intel/wtm2/gpio.c @@ -13,12 +13,9 @@ * GNU General Public License for more details. */ -#ifndef INTEL_WTM2_GPIO_H -#define INTEL_WTM2_GPIO_H - #include <soc/gpio.h> -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_NATIVE, /* 0: LPSS_UART1_RXD */ PCH_GPIO_NATIVE, /* 1: LPSS_UART1_TXD */ PCH_GPIO_NATIVE, /* 2: LPSS_UART1_RTS_N_R */ @@ -116,5 +113,3 @@ PCH_GPIO_NATIVE, /* 94: LPSS_UART0_CTS_N */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c index 3c9bb36..de4237d 100644 --- a/src/mainboard/intel/wtm2/romstage.c +++ b/src/mainboard/intel/wtm2/romstage.c @@ -21,7 +21,6 @@ #include <soc/pei_data.h> #include <soc/pei_wrapper.h> #include <soc/romstage.h> -#include "gpio.h" void mainboard_romstage_entry(struct romstage_params *rp) { @@ -29,9 +28,6 @@ post_code(0x32); - /* Initialize GPIOs */ - init_gpios(mainboard_gpio_config); - /* Fill out PEI DATA */ memset(&pei_data, 0, sizeof(pei_data)); mainboard_fill_pei_data(&pei_data); diff --git a/src/mainboard/purism/librem_bdw/Makefile.inc b/src/mainboard/purism/librem_bdw/Makefile.inc index 293e186..16ce37a 100644 --- a/src/mainboard/purism/librem_bdw/Makefile.inc +++ b/src/mainboard/purism/librem_bdw/Makefile.inc @@ -13,5 +13,6 @@ ## GNU General Public License for more details. ## +romstage-y += gpio.c romstage-y += variants/$(VARIANT_DIR)/pei_data.c ramstage-y += variants/$(VARIANT_DIR)/pei_data.c diff --git a/src/mainboard/purism/librem_bdw/gpio.h b/src/mainboard/purism/librem_bdw/gpio.c similarity index 95% rename from src/mainboard/purism/librem_bdw/gpio.h rename to src/mainboard/purism/librem_bdw/gpio.c index 98b09bc..5102996 100644 --- a/src/mainboard/purism/librem_bdw/gpio.h +++ b/src/mainboard/purism/librem_bdw/gpio.c @@ -13,12 +13,9 @@ * GNU General Public License for more details. */ -#ifndef MAINBOARD_GPIO_H -#define MAINBOARD_GPIO_H - #include <soc/gpio.h> -static const struct gpio_config mainboard_gpio_config[] = { +const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_INPUT, /* 0 */ PCH_GPIO_INPUT, /* 1 */ PCH_GPIO_INPUT, /* 2 */ @@ -116,5 +113,3 @@ PCH_GPIO_INPUT, /* 94 */ PCH_GPIO_END }; - -#endif diff --git a/src/mainboard/purism/librem_bdw/romstage.c b/src/mainboard/purism/librem_bdw/romstage.c index 2e0ae85..6591229 100644 --- a/src/mainboard/purism/librem_bdw/romstage.c +++ b/src/mainboard/purism/librem_bdw/romstage.c @@ -14,19 +14,14 @@ */ #include <string.h> -#include <soc/gpio.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> #include <soc/romstage.h> -#include "gpio.h" void mainboard_romstage_entry(struct romstage_params *rp) { struct pei_data pei_data; - /* Initialize GPIOs */ - init_gpios(mainboard_gpio_config); - /* Fill out PEI DATA */ memset(&pei_data, 0, sizeof(pei_data)); mainboard_fill_pei_data(&pei_data); diff --git a/src/soc/intel/broadwell/include/soc/gpio.h b/src/soc/intel/broadwell/include/soc/gpio.h index 66820b2..c0ac134 100644 --- a/src/soc/intel/broadwell/include/soc/gpio.h +++ b/src/soc/intel/broadwell/include/soc/gpio.h @@ -193,4 +193,6 @@ */ unsigned int get_gpios(const int *gpio_num_array); +extern const struct gpio_config mainboard_gpio_config[]; + #endif diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 2531665..7847829 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -27,6 +27,7 @@ #include <romstage_handoff.h> #include <stage_cache.h> #include <timestamp.h> +#include <soc/gpio.h> #include <soc/me.h> #include <soc/pei_data.h> #include <soc/pm.h> @@ -100,6 +101,9 @@ /* Set CPU frequency to maximum */ set_max_freq(); + /* Initialize GPIOs */ + init_gpios(mainboard_gpio_config); + /* Call into mainboard. */ mainboard_romstage_entry(&rp); -- To view, visit https://review.coreboot.org/c/coreboot/+/32759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9309d2b842495f6cff33fdab18aa139a82c1959c Gerrit-Change-Number: 32759 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mainboard/google/hatch: Use SpiCs options in device tree.
by Tim Wawrzynczak (Code Review) 14 May '19

14 May '19

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32792 Change subject: mainboard/google/hatch: Use SpiCs options in device tree. ...................................................................... mainboard/google/hatch: Use SpiCs options in device tree. Explicitly set CsEnable, CsPolarity and DefaultCsOutput for SPI0 and SPI1 in the devicetree. BUG=b:130329260 BRANCH=none TEST=Hatch still boots, no errors seen in coreboot output. TPM still communicates properly. Change-Id: I481a2c2b51738d6401f8d7ee89448e982262471d Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/hatch/variants/hatch/overridetree.cb 1 file changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/32792/1 diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index 562bb8b..12e1602 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -15,6 +15,31 @@ [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + register "SerialIoSpi0CsPolarity" = "{ + [0] = PchSerialIoCsActiveLow, + [1] = PchSerialIoCsActiveLow, + }" + + register "SerialIoSpi1CsPolarity" = "{ + [0] = PchSerialIoCsActiveLow, + [1] = PchSerialIoCsActiveLow, + }" + + register "SerialIoSpi0CsEnable" = "{ + [0] = PchSerialIoCsEnable, + [1] = PchSerialIoCsGpio, + }" + + register "SerialIoSpi1CsEnable" = "{ + [0] = PchSerialIoCsGpio, + [1] = PchSerialIoCsEnable, + }" + + register "SerialIoSpiDefaultCsOutput" = "{ + [0] = PchSerialIoCS0, + [1] = PchSerialIoCS1, + }" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | -- To view, visit https://review.coreboot.org/c/coreboot/+/32792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I481a2c2b51738d6401f8d7ee89448e982262471d Gerrit-Change-Number: 32792 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/drivers/xgi: Move coreboot related includes to xgi_coreboot.h
by HAOUAS Elyes (Code Review) 14 May '19

14 May '19

Hello Alexander Couzens, Patrick Rudolph, Angel Pons, Paul Menzel, build bot (Jenkins), Damien Zammit, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29307 to look at the new patch set (#23). Change subject: src/drivers/xgi: Move coreboot related includes to xgi_coreboot.h ...................................................................... src/drivers/xgi: Move coreboot related includes to xgi_coreboot.h Change-Id: Ia18c77876121594a272a07d56acfaa863d0ccb25 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/xgi/common/vb_init.c M src/drivers/xgi/common/vb_setmode.c M src/drivers/xgi/common/vb_util.c M src/drivers/xgi/common/xgi_coreboot.h 4 files changed, 5 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/29307/23 -- To view, visit https://review.coreboot.org/c/coreboot/+/29307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia18c77876121594a272a07d56acfaa863d0ccb25 Gerrit-Change-Number: 29307 Gerrit-PatchSet: 23 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: src/drivers: Remove unneeded include <arch/io.h>
by HAOUAS Elyes (Code Review) 14 May '19

14 May '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29307 ) Change subject: src/drivers: Remove unneeded include <arch/io.h> ...................................................................... Patch Set 22: (1 comment) https://review.coreboot.org/#/c/29307/22/src/drivers/xgi/common/vb_init.c File src/drivers/xgi/common/vb_init.c: https://review.coreboot.org/#/c/29307/22/src/drivers/xgi/common/vb_init.c@7 PS22, Line 7: * coreboot-specific includes added at top > It was intended that all coreboot related includes come indirectly from xgi_coreboot.h file. […] so this "#include <delay.h>" should go to xgi_coreboot.h ... -- To view, visit https://review.coreboot.org/c/coreboot/+/29307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia18c77876121594a272a07d56acfaa863d0ccb25 Gerrit-Change-Number: 29307 Gerrit-PatchSet: 22 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Comment-Date: Tue, 14 May 2019 19:39:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: coreboot: add post code for SoC initialization failure
by Martin Roth (Code Review) 14 May '19

14 May '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32774 ) Change subject: coreboot: add post code for SoC initialization failure ...................................................................... Patch Set 2: (3 comments) https://review.coreboot.org/#/c/32774/2//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/32774/2//COMMIT_MSG@10 PS2, Line 10: integratred integrated. https://review.coreboot.org/#/c/32774/2/src/include/console/post_codes.h File src/include/console/post_codes.h: https://review.coreboot.org/#/c/32774/2/src/include/console/post_codes.h@356 PS2, Line 356: POST_SOC_FAILURE Why is this just for SOCs? Wouldn't those same components be somewhere else like the southbridge in a Non-SOC system? Maybe make it more generic - POST_INIT_FAILURE? https://review.coreboot.org/#/c/32774/2/src/soc/intel/quark/i2c.c File src/soc/intel/quark/i2c.c: https://review.coreboot.org/#/c/32774/2/src/soc/intel/quark/i2c.c@42 PS2, Line 42: die("ERROR - I2C failed to disable!\n"); Only somewhat related to the overall patch, but is it really appropriate to halt the system because an I2C device didn't disable properly? -- To view, visit https://review.coreboot.org/c/coreboot/+/32774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73820d24b3e1c269d9d446a78ef4f97e167e3552 Gerrit-Change-Number: 32774 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 14 May 2019 19:38:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: coreboot: add post code for SoC initialization failure
by Keith Short (Code Review) 14 May '19

14 May '19

Keith Short has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32774 ) Change subject: coreboot: add post code for SoC initialization failure ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/32774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73820d24b3e1c269d9d446a78ef4f97e167e3552 Gerrit-Change-Number: 32774 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 14 May 2019 19:08:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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