coreboot-gerrit May 2019

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Change in ...coreboot[master]: coreboot: add post code for video initialization failure
by Keith Short (Code Review) 14 May '19

14 May '19

Hello Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/32775 to look at the new patch set (#3). Change subject: coreboot: add post code for video initialization failure ...................................................................... coreboot: add post code for video initialization failure Add a new post code POST_VIDEO_FAILURE used when the Intel FSP silicon initialization returns an error when graphics was also initialized. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: Ibc7f7defbed34038f445949010a37c8e368aae20 Signed-off-by: Keith Short <keithshort(a)chromium.org> --- M src/drivers/intel/fsp2_0/silicon_init.c M src/include/console/post_codes.h 2 files changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/32775/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/32775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc7f7defbed34038f445949010a37c8e368aae20 Gerrit-Change-Number: 32775 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: autoport: Remove unneeded include <arch/io.h>
by Kyösti Mälkki (Code Review) 14 May '19

14 May '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32787 ) Change subject: autoport: Remove unneeded include <arch/io.h> ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/32787 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7cb4b47e2fd893274303bb20dc7fa895830b4493 Gerrit-Change-Number: 32787 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 14 May 2019 19:04:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/drivers: Remove unneeded include <arch/io.h>
by Kyösti Mälkki (Code Review) 14 May '19

14 May '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29307 ) Change subject: src/drivers: Remove unneeded include <arch/io.h> ...................................................................... Patch Set 22: (1 comment) https://review.coreboot.org/#/c/29307/22/src/drivers/xgi/common/vb_init.c File src/drivers/xgi/common/vb_init.c: https://review.coreboot.org/#/c/29307/22/src/drivers/xgi/common/vb_init.c@7 PS22, Line 7: * coreboot-specific includes added at top It was intended that all coreboot related includes come indirectly from xgi_coreboot.h file. I see no value in changing that. -- To view, visit https://review.coreboot.org/c/coreboot/+/29307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia18c77876121594a272a07d56acfaa863d0ccb25 Gerrit-Change-Number: 29307 Gerrit-PatchSet: 22 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Comment-Date: Tue, 14 May 2019 18:59:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/cannonlake: Add FSP SPI CS options
by Shelley Chen (Code Review) 14 May '19

14 May '19

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32793 Change subject: soc/intel/cannonlake: Add FSP SPI CS options ...................................................................... soc/intel/cannonlake: Add FSP SPI CS options Allow setting of SPI CS FSP options. BUG=b:130329260 BRANCH=None TEST=boot up and make sure these options are set as expected in fsp_params. Change-Id: I3a77f8bd3b447bec5a2807a2afab723aa500f146 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/soc/intel/cannonlake/chip.h M src/soc/intel/cannonlake/fsp_params.c 2 files changed, 34 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/32793/1 diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index b17df4b..65009f0 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -21,7 +21,6 @@ #include <intelblocks/chip.h> #include <drivers/i2c/designware/dw_i2c.h> #include <intelblocks/gspi.h> -#include <smbios.h> #include <stdint.h> #include <soc/gpio.h> #include <soc/pch.h> @@ -338,6 +337,27 @@ */ uint8_t SerialIoDevMode[PchSerialIoIndexMAX]; + /* + * Chip Select Polarity + * 0 : PchSerialIoCsActiveLow + * 1 : PchSerialIoCsActiveHigh + */ + uint8_t SerialIoSpi0CsPolarity[2]; + uint8_t SerialIoSpi1CsPolarity[2]; + /* + * Chip Select Enable + * 0 : Disabled + * 1 : Enabled + */ + uint8_t SerialIoSpi0CsEnable[2]; + uint8_t SerialIoSpi1CsEnable[2]; + /* + * Default Chip Select Output + * 0 : CS0 + * 1 : CS1 + */ + uint8_t SerialIoSpiDefaultCsOutput[2]; + /* GPIO SD card detect pin */ unsigned int sdcard_cd_gpio; @@ -401,10 +421,6 @@ /* Unlock all GPIO Pads */ uint8_t PchUnlockGpioPads; - - /* Enable GBE wakeup */ - uint8_t LanWakeFromDeepSx; - uint8_t WolEnableOverride; }; typedef struct soc_intel_cannonlake_config config_t; diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index cc01d10..e9043e2 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -86,6 +86,19 @@ params->SerialIoUartMode[i] = get_param_value(config, dev_offset); } + + params->SerialIoSpi0CsPolarity[0] = config->SerialIoSpi0CsPolarity[0]; + params->SerialIoSpi0CsPolarity[1] = config->SerialIoSpi0CsPolarity[1]; + params->SerialIoSpi1CsPolarity[0] = config->SerialIoSpi1CsPolarity[0]; + params->SerialIoSpi1CsPolarity[1] = config->SerialIoSpi1CsPolarity[1]; + params->SerialIoSpi0CsEnable[0] = config->SerialIoSpi0CsEnable[0]; + params->SerialIoSpi0CsEnable[1] = config->SerialIoSpi0CsEnable[1]; + params->SerialIoSpi1CsEnable[0] = config->SerialIoSpi1CsEnable[0]; + params->SerialIoSpi1CsEnable[1] = config->SerialIoSpi1CsEnable[1]; + params->SerialIoSpiDefaultCsOutput[0] = + config->SerialIoSpiDefaultCsOutput[0]; + params->SerialIoSpiDefaultCsOutput[1] = + config->SerialIoSpiDefaultCsOutput[1]; } #else static void parse_devicetree_param(const config_t *config, FSP_S_CONFIG *params) @@ -212,10 +225,6 @@ params->DdiPortDDdc = config->DdiPortDDdc; params->DdiPortFDdc = config->DdiPortFDdc; - /* WOL */ - params->PchPmPcieWakeFromDeepSx = config->LanWakeFromDeepSx; - params->PchPmWolEnableOverride = config->WolEnableOverride; - /* S0ix */ params->PchPmSlpS0Enable = config->s0ix_enable; -- To view, visit https://review.coreboot.org/c/coreboot/+/32793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a77f8bd3b447bec5a2807a2afab723aa500f146 Gerrit-Change-Number: 32793 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mv/google/hatch: Set FSP SPI CS options
by Shelley Chen (Code Review) 14 May '19

14 May '19

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32794 Change subject: mv/google/hatch: Set FSP SPI CS options ...................................................................... mv/google/hatch: Set FSP SPI CS options Explicitly set SPI CS options in overridetree for kohaku and hatch. BUG=b:130329260 BRANCH=None TEST=Boot up and make sure SPI CS options are set properly in fsp_params Change-Id: Icbbab7df05ac38918ffd5c2d66d22d5db57d471b Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/hatch/variants/hatch/overridetree.cb M src/mainboard/google/hatch/variants/kohaku/overridetree.cb 2 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/32794/1 diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index 42752e6..4cb7fc9 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -15,6 +15,17 @@ [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + register "SerialIoSpi0CsPolarity[0]" = "0" + register "SerialIoSpi0CsPolarity[1]" = "0" + register "SerialIoSpi1CsPolarity[0]" = "0" + register "SerialIoSpi1CsPolarity[1]" = "0" + register "SerialIoSpi0CsEnable[0]" = "1" + register "SerialIoSpi0CsEnable[1]" = "0" + register "SerialIoSpi1CsEnable[0]" = "0" + register "SerialIoSpi1CsEnable[1]" = "1" + register "SerialIoSpiDefaultCsOutput[0]" = "0" + register "SerialIoSpiDefaultCsOutput[1]" = "1" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | diff --git a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb index 9546420..4d7ba72 100644 --- a/src/mainboard/google/hatch/variants/kohaku/overridetree.cb +++ b/src/mainboard/google/hatch/variants/kohaku/overridetree.cb @@ -14,6 +14,17 @@ [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + register "SerialIoSpi0CsPolarity[0]" = "0" + register "SerialIoSpi0CsPolarity[1]" = "0" + register "SerialIoSpi1CsPolarity[0]" = "0" + register "SerialIoSpi1CsPolarity[1]" = "0" + register "SerialIoSpi0CsEnable[0]" = "1" + register "SerialIoSpi0CsEnable[1]" = "0" + register "SerialIoSpi1CsEnable[0]" = "0" + register "SerialIoSpi1CsEnable[1]" = "1" + register "SerialIoSpiDefaultCsOutput[0]" = "0" + register "SerialIoSpiDefaultCsOutput[1]" = "1" + # No PCIe WiFi register "PcieRpEnable[13]" = "0" -- To view, visit https://review.coreboot.org/c/coreboot/+/32794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbbab7df05ac38918ffd5c2d66d22d5db57d471b Gerrit-Change-Number: 32794 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: {arch, console, drivers, include, lib, soc}: Add new features in postcar
by Subrata Banik (Code Review) 14 May '19

14 May '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32667 Change subject: {arch, console, drivers, include, lib, soc}: Add new features in postcar ...................................................................... {arch, console, drivers, include, lib, soc}: Add new features in postcar 1. Able to create ACPI table 2. Cache located in BSS in postcar as well 3. Load payload from postcar 4. Specific soc/pch related programming 5. mutable devicetree structure in postcar 6. Make postcar stage as !__SIMPLE_DEVICE__ 7. Now postcar has heap. Change-Id: Ibf160033362920f737385c792d964d47b3f82bd7 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/arch/x86/include/arch/acpi.h M src/console/post.c M src/drivers/uart/uart8250io.c M src/drivers/uart/uart8250mem.c M src/include/memlayout.h M src/include/rules.h M src/include/stddef.h M src/lib/bootmode.c M src/lib/imd_cbmem.c M src/lib/memrange.c M src/lib/prog_loaders.c M src/lib/program.ld M src/lib/timestamp.c M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/systemagent/systemagent_early.c 16 files changed, 52 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/32667/1 diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 79feaad..9258206 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -838,7 +838,9 @@ unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t *ivrs_struct, unsigned long current)); -#if ENV_RAMSTAGE && !defined(__SIMPLE_DEVICE__) +#if (CONFIG(SKIP_RAMSTAGE) ? ((ENV_RAMSTAGE || ENV_POSTCAR) && \ + !defined(__SIMPLE_DEVICE__)) : (ENV_RAMSTAGE && \ + !defined(__SIMPLE_DEVICE__))) void acpi_create_hpet(acpi_hpet_t *hpet); unsigned long acpi_write_hpet(struct device *device, unsigned long start, acpi_rsdp_t *rsdp); diff --git a/src/console/post.c b/src/console/post.c index 236aa8c..6832151 100644 --- a/src/console/post.c +++ b/src/console/post.c @@ -44,7 +44,7 @@ DECLARE_SPIN_LOCK(cmos_post_lock) -#if ENV_RAMSTAGE +#if (CONFIG(SKIP_RAMSTAGE) ? (ENV_RAMSTAGE || ENV_POSTCAR) : ENV_RAMSTAGE) void cmos_post_log(void) { u8 code = 0; @@ -125,7 +125,7 @@ post_log_extra(0); } #endif /* CONFIG_CMOS_POST_EXTRA */ -#endif /* ENV_RAMSTAGE */ +#endif /* ENV_RAMSTAGE (or ENV_POSTCAR) if SKIP_RAMSTAGE is enable */ static void cmos_post_code(u8 value) { diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index 62671e2..e536ab8 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -124,7 +124,7 @@ uart8250_tx_flush(uart_platform_base(idx)); } -#if ENV_RAMSTAGE +#if (CONFIG(SKIP_RAMSTAGE) ? (ENV_RAMSTAGE || ENV_POSTCAR) : ENV_RAMSTAGE) void uart_fill_lb(void *data) { struct lb_serial serial; diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index c3dff6a..d2a45ba 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -147,7 +147,7 @@ uart8250_mem_tx_flush(base); } -#if ENV_RAMSTAGE +#if (CONFIG(SKIP_RAMSTAGE) ? (ENV_RAMSTAGE || ENV_POSTCAR) : ENV_RAMSTAGE) void uart_fill_lb(void *data) { struct lb_serial serial; diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 273a80d..98bfdfe 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -39,10 +39,17 @@ #define ARCH_STAGE_HAS_BSS_SECTION 1 #endif -/* Default is that currently ramstage, smm, and rmodules have a heap. */ + #ifndef ARCH_STAGE_HAS_HEAP_SECTION +#if CONFIG(SKIP_RAMSTAGE) +/* Default is that currently postcar, ramstage, smm, and rmodules have a heap. */ +#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM || ENV_RMODULE || \ + ENV_POSTCAR) +#else +/* Default is that currently ramstage, smm, and rmodules have a heap. */ #define ARCH_STAGE_HAS_HEAP_SECTION (ENV_RAMSTAGE || ENV_SMM || ENV_RMODULE) #endif +#endif #define STR(x) #x diff --git a/src/include/rules.h b/src/include/rules.h index ea8335f..47a98ee 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -268,7 +268,8 @@ * be built with simple device model. */ -#if (defined(__PRE_RAM__) || ENV_SMM || ENV_POSTCAR) +#if (CONFIG(SKIP_RAMSTAGE) ? (ENV_X86 && (defined(__PRE_RAM__) || ENV_SMM)) \ + : (defined(__PRE_RAM__) || ENV_SMM || ENV_POSTCAR)) #define __SIMPLE_DEVICE__ #endif diff --git a/src/include/stddef.h b/src/include/stddef.h index 993d5f0..c9fdb67 100644 --- a/src/include/stddef.h +++ b/src/include/stddef.h @@ -21,9 +21,10 @@ #define NULL ((void *)0) -/* The devicetree data structures are only mutable in ramstage. All other - stages have a constant devicetree. */ -#if !ENV_RAMSTAGE +/* The devicetree data structures are only mutable in postcar + (if CONFIG_SKIP_RAMSTAGE) and ramstage. All other stages have a constant + devicetree. */ +#if (CONFIG(SKIP_RAMSTAGE) ? (!ENV_RAMSTAGE && !ENV_POSTCAR) : !ENV_RAMSTAGE) #define DEVTREE_EARLY 1 #else #define DEVTREE_EARLY 0 diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index 18f6d5d..faafd2d 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -17,7 +17,7 @@ #include <bootmode.h> #include <vendorcode/google/chromeos/chromeos.h> -#if ENV_RAMSTAGE +#if (CONFIG(SKIP_RAMSTAGE) ? (ENV_RAMSTAGE || ENV_POSTCAR) : ENV_RAMSTAGE) static int gfx_init_done = -1; int gfx_get_init_done(void) diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index 1a67ad5..374767b 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -307,8 +307,10 @@ imd_region_used(cbmem_get_imd(), baseptr, size); } -#if ENV_RAMSTAGE || (CONFIG(EARLY_CBMEM_LIST) \ - && (ENV_POSTCAR || ENV_ROMSTAGE)) +#if (CONFIG(SKIP_RAMSTAGE) ? (ENV_RAMSTAGE || ENV_POSTCAR || \ + (IS_ENABLED(CONFIG_EARLY_CBMEM_LIST) && (ENV_ROMSTAGE))) \ + : (ENV_RAMSTAGE || (CONFIG(EARLY_CBMEM_LIST) \ + && (ENV_POSTCAR || ENV_ROMSTAGE)))) /* * -fdata-sections doesn't work so well on read only strings. They all * get put in the same section even though those strings may never be diff --git a/src/lib/memrange.c b/src/lib/memrange.c index 96d7524..62706c9 100644 --- a/src/lib/memrange.c +++ b/src/lib/memrange.c @@ -47,7 +47,11 @@ range_entry_unlink(&ranges->free_list, r); return r; } +#if CONFIG(SKIP_RAMSTAGE) + if (ENV_RAMSTAGE || ENV_POSTCAR) +#else if (ENV_RAMSTAGE) +#endif return malloc(sizeof(struct range_entry)); return NULL; } diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 3b77712..ed69b37 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -165,7 +165,8 @@ die("Ramstage was not loaded!\n"); } -#ifdef __RAMSTAGE__ // gc-sections should take care of this +#if (CONFIG(SKIP_RAMSTAGE) ? (defined(__RAMSTAGE__) || defined(__POSTCAR__)) \ + : defined(__RAMSTAGE__)) // gc-sections should take care of this static struct prog global_payload = PROG_INIT(PROG_PAYLOAD, CONFIG_CBFS_PREFIX "/payload"); diff --git a/src/lib/program.ld b/src/lib/program.ld index 851aa75..ad65494 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -55,7 +55,7 @@ KEEP(*(.rsbe_init)); _ersbe_init_begin = .; -#if ENV_RAMSTAGE +#if (CONFIG(SKIP_RAMSTAGE) ? (ENV_RAMSTAGE || ENV_POSTCAR) : ENV_RAMSTAGE) . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _pci_drivers = .; KEEP(*(.rodata.pci_driver)); diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index b6330fa..7eaf078 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -47,8 +47,13 @@ #define USE_TIMESTAMP_REGION 0 #endif +#if CONFIG(SKIP_RAMSTAGE) +/* The cache location will sit in BSS when in ramstage and postcar. */ +#define TIMESTAMP_CACHE_IN_BSS (ENV_RAMSTAGE || ENV_POSTCAR) +#else /* The cache location will sit in BSS when in ramstage. */ #define TIMESTAMP_CACHE_IN_BSS ENV_RAMSTAGE +#endif #define HAS_CBMEM (ENV_ROMSTAGE || ENV_RAMSTAGE || ENV_POSTCAR) @@ -299,8 +304,13 @@ if (ts_cbmem_table->base_time == 0) ts_cbmem_table->base_time = ts_cache_table->base_time; +#if CONFIG(SKIP_RAMSTAGE) + /* Seed the timestamp tick frequency in ramstage and postcar. */ + if (ENV_RAMSTAGE || ENV_POSTCAR) +#else /* Seed the timestamp tick frequency in ramstage. */ if (ENV_RAMSTAGE) +#endif ts_cbmem_table->tick_freq_mhz = timestamp_tick_freq_mhz(); /* Cache no longer required. */ @@ -350,6 +360,9 @@ } ROMSTAGE_CBMEM_INIT_HOOK(timestamp_sync_cache_to_cbmem) +#if CONFIG(SKIP_RAMSTAGE) +POSTCAR_CBMEM_INIT_HOOK(timestamp_sync_cache_to_cbmem) +#endif RAMSTAGE_CBMEM_INIT_HOOK(timestamp_sync_cache_to_cbmem) /* Provide default timestamp implementation using monotonic timer. */ diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index 455b13c..dbec4e9 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -250,7 +250,11 @@ bios_size = ALIGN_UP(bios_size, alignment); base = 4ULL*GiB - bios_size; +#if CONFIG(SKIP_RAMSTAGE) + if (ENV_RAMSTAGE || ENV_POSTCAR) { +#else if (ENV_RAMSTAGE) { +#endif mtrr_use_temp_range(base, bios_size, type); } else { int mtrr = get_free_var_mtrr(); diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index a99dfea..1a26802 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -47,7 +47,7 @@ return EARLY_I2C_BASE(bus); } -#if !ENV_RAMSTAGE +#if (CONFIG(SKIP_RAMSTAGE) ? (!ENV_RAMSTAGE && !ENV_POSTCAR) : !ENV_RAMSTAGE) static int lpss_i2c_early_init_bus(unsigned int bus) { const struct dw_i2c_bus_config *config; diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index 61f14a9..5c6b261 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -24,7 +24,7 @@ #include "systemagent_def.h" -#if !ENV_RAMSTAGE +#if (CONFIG(SKIP_RAMSTAGE) ? (!ENV_RAMSTAGE && !ENV_POSTCAR) : !ENV_RAMSTAGE) void bootblock_systemagent_early_init(void) { uint32_t reg; -- To view, visit https://review.coreboot.org/c/coreboot/+/32667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibf160033362920f737385c792d964d47b3f82bd7 Gerrit-Change-Number: 32667 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: vendorcode/amd/pi: Include $(obj)/config.h
by Subrata Banik (Code Review) 14 May '19

14 May '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32768 Change subject: vendorcode/amd/pi: Include $(obj)/config.h ...................................................................... vendorcode/amd/pi: Include $(obj)/config.h This patch allows to have CONFIG() macro in src/include/rules.h Change-Id: I4682d10218675616e025b45537aef41eceaa9e9e Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/vendorcode/amd/pi/00670F00/Makefile.inc M src/vendorcode/amd/pi/Makefile.inc 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/32768/1 diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc index 0e6f2af..ee6f65a 100644 --- a/src/vendorcode/amd/pi/00670F00/Makefile.inc +++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc @@ -77,6 +77,7 @@ @printf " CC $$(subst $(obj)/,,$$(@))\n" $(CC_libagesa) -c -MMD $(CFLAGS_libagesa) $(AGESA_CFLAGS) \ $(AGESA_INC) \ + -include $(obj)/config.h \ -include $(src)/include/rules.h \ -include $(src)/include/kconfig.h \ -include $(src)/commonlib/include/commonlib/compiler.h \ diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc index 4c8db6a..0a21d40 100644 --- a/src/vendorcode/amd/pi/Makefile.inc +++ b/src/vendorcode/amd/pi/Makefile.inc @@ -100,6 +100,7 @@ @printf " CC $$(subst $(obj)/,,$$(@))\n" $(CC_libagesa) -c -MMD $(CFLAGS_libagesa) $(AGESA_CFLAGS) \ $(AGESA_INC) \ + -include $(obj)/config.h \ -include $(src)/include/rules.h \ -include $(src)/include/kconfig.h \ -include $(src)/commonlib/include/commonlib/compiler.h \ -- To view, visit https://review.coreboot.org/c/coreboot/+/32768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4682d10218675616e025b45537aef41eceaa9e9e Gerrit-Change-Number: 32768 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/broadwell: Move GPIO init to a common place
by Matt DeVillier (Code Review) 14 May '19

14 May '19

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32759 ) Change subject: soc/intel/broadwell: Move GPIO init to a common place ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/32759 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9309d2b842495f6cff33fdab18aa139a82c1959c Gerrit-Change-Number: 32759 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 14 May 2019 14:47:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/drivers: Remove unneeded include <arch/io.h>
by HAOUAS Elyes (Code Review) 14 May '19

14 May '19

Hello Alexander Couzens, Patrick Rudolph, Angel Pons, Paul Menzel, build bot (Jenkins), Damien Zammit, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29307 to look at the new patch set (#22). Change subject: src/drivers: Remove unneeded include <arch/io.h> ...................................................................... src/drivers: Remove unneeded include <arch/io.h> Change-Id: Ia18c77876121594a272a07d56acfaa863d0ccb25 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/xgi/common/vb_init.c M src/drivers/xgi/common/vb_setmode.c M src/drivers/xgi/common/vb_util.c M src/drivers/xgi/common/xgi_coreboot.h 4 files changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/29307/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/29307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia18c77876121594a272a07d56acfaa863d0ccb25 Gerrit-Change-Number: 29307 Gerrit-PatchSet: 22 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: vendorcode/amd/pi: Include $(obj)/config.h
by Subrata Banik (Code Review) 14 May '19

14 May '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32781 Change subject: vendorcode/amd/pi: Include $(obj)/config.h ...................................................................... vendorcode/amd/pi: Include $(obj)/config.h This patch allows to have CONFIG() macro in src/include/rules.h Change-Id: Ie2d9df756d5ed7201d6061b53026659c6a55dbbc Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/vendorcode/amd/pi/00670F00/Makefile.inc M src/vendorcode/amd/pi/Makefile.inc 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/32781/1 diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc index 0e6f2af..79eaac0 100644 --- a/src/vendorcode/amd/pi/00670F00/Makefile.inc +++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc @@ -80,6 +80,7 @@ -include $(src)/include/rules.h \ -include $(src)/include/kconfig.h \ -include $(src)/commonlib/include/commonlib/compiler.h \ + -D__BUILD_DIR__=\"$(obj)\" \ -o $$@ \ $(agesa_src_path)/$(notdir $1) diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc index 4c8db6a..8fcd413 100644 --- a/src/vendorcode/amd/pi/Makefile.inc +++ b/src/vendorcode/amd/pi/Makefile.inc @@ -103,6 +103,7 @@ -include $(src)/include/rules.h \ -include $(src)/include/kconfig.h \ -include $(src)/commonlib/include/commonlib/compiler.h \ + -D__BUILD_DIR__=\"$(obj)\" \ -o $$@ \ $(agesa_src_path)/$(notdir $1) -- To view, visit https://review.coreboot.org/c/coreboot/+/32781 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2d9df756d5ed7201d6061b53026659c6a55dbbc Gerrit-Change-Number: 32781 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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