coreboot-gerrit May 2019

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Change in ...coreboot[master]: 3rdparty: Uprev vboot submodule to upstream master
by Julius Werner (Code Review) 13 May '19

13 May '19

Hello Joel Kitching, Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32748 to review the following change. Change subject: 3rdparty: Uprev vboot submodule to upstream master ...................................................................... 3rdparty: Uprev vboot submodule to upstream master This patch uprevs the vboot submodule to the new upstream HEAD commit dac763c782 Make vboot -Wtype-limits compliant Change-Id: I363e218e019b25483bc4c06315ca4e0e34599daf Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/32748/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index e7edff6..dac763c 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit e7edff6653e16ed915c3ad12234d133d1ef4dcc9 +Subproject commit dac763c782ce05476dec02e855f349d2b6f3a910 -- To view, visit https://review.coreboot.org/c/coreboot/+/32748 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I363e218e019b25483bc4c06315ca4e0e34599daf Gerrit-Change-Number: 32748 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Joel Kitching <kitching(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: i82801gx/bootblock: Use macro instead of magic number
by HAOUAS Elyes (Code Review) 13 May '19

13 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32755 Change subject: i82801gx/bootblock: Use macro instead of magic number ...................................................................... i82801gx/bootblock: Use macro instead of magic number Change-Id: I2556c150f53d9580bc3b70ab49b3a2c8477c18ea Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801gx/bootblock.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/32755/1 diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index 426973f..9d94d0c 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -23,10 +23,10 @@ dev = PCI_DEV(0, 0x1f, 0); - reg8 = pci_read_config8(dev, 0xdc); + reg8 = pci_read_config8(dev, BIOS_CNTL); reg8 &= ~(3 << 2); reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); } static void bootblock_southbridge_init(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/32755 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2556c150f53d9580bc3b70ab49b3a2c8477c18ea Gerrit-Change-Number: 32755 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/{cannonlake,icelake}: Drop unused cbmem.c file
by HAOUAS Elyes (Code Review) 13 May '19

13 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32756 Change subject: soc/intel/{cannonlake,icelake}: Drop unused cbmem.c file ...................................................................... soc/intel/{cannonlake,icelake}: Drop unused cbmem.c file Change-Id: Ib9444f7797289c9b8250cfb16eb1c12dff867ec3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- D src/soc/intel/cannonlake/cbmem.c D src/soc/intel/icelake/cbmem.c 2 files changed, 0 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/32756/1 diff --git a/src/soc/intel/cannonlake/cbmem.c b/src/soc/intel/cannonlake/cbmem.c deleted file mode 100644 index 300556a..0000000 --- a/src/soc/intel/cannonlake/cbmem.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2017 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> - -void *cbmem_top(void) -{ - /* not implemented yet */ - return (void *) NULL; -} diff --git a/src/soc/intel/icelake/cbmem.c b/src/soc/intel/icelake/cbmem.c deleted file mode 100644 index 4f44777..0000000 --- a/src/soc/intel/icelake/cbmem.c +++ /dev/null @@ -1,22 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbmem.h> - -void *cbmem_top(void) -{ - /* not implemented yet */ - return (void *) NULL; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/32756 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9444f7797289c9b8250cfb16eb1c12dff867ec3 Gerrit-Change-Number: 32756 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: {bd82x6x,i82801gx,ibexpeak,lynxpoint}: Remove dead code and use macro
by Patrick Georgi (Code Review) 13 May '19

13 May '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29990 ) Change subject: {bd82x6x,i82801gx,ibexpeak,lynxpoint}: Remove dead code and use macro ...................................................................... {bd82x6x,i82801gx,ibexpeak,lynxpoint}: Remove dead code and use macro Use BIOS_CNTL defined macro instead of magic number. Change-Id: I0d2b555ada9c2893af4f85422128f5a8b04e2fc6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29990 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/soc/intel/fsp_baytrail/southcluster.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/fsp_rangeley/lpc.c M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801ix/lpc.c M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/ibexpeak/lpc.c M src/southbridge/intel/lynxpoint/lpc.c 8 files changed, 6 insertions(+), 108 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index 4734e0e..c84f408 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -42,9 +42,6 @@ #include "chip.h" #include <arch/acpi.h> -#define ENABLE_ACPI_MODE_IN_COREBOOT 0 -#define TEST_SMM_FLASH_LOCKDOWN 0 - typedef struct soc_intel_fsp_baytrail_config config_t; static inline void diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index f7bb7e4..7737501 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -436,9 +436,9 @@ u8 reg8; printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); reg8 &= ~(1 << 5); - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); } static void pch_fixups(struct device *dev) diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index 4118e5f..ba5e04b 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -38,9 +38,6 @@ #define NMI_OFF 0 -#define ENABLE_ACPI_MODE_IN_COREBOOT 0 -#define TEST_SMM_FLASH_LOCKDOWN 0 - typedef struct southbridge_intel_fsp_rangeley_config config_t; static void soc_enable_apic(struct device *dev) diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 9a6c9cf..948b6aa 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -40,7 +40,6 @@ #define NMI_OFF 0 #define ENABLE_ACPI_MODE_IN_COREBOOT 0 -#define TEST_SMM_FLASH_LOCKDOWN 0 typedef struct southbridge_intel_i82801gx_config config_t; @@ -333,10 +332,6 @@ #if CONFIG(HAVE_SMI_HANDLER) static void i82801gx_lock_smm(struct device *dev) { -#if TEST_SMM_FLASH_LOCKDOWN - u8 reg8; -#endif - if (!acpi_is_wakeup_s3()) { #if ENABLE_ACPI_MODE_IN_COREBOOT printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); @@ -351,33 +346,6 @@ printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); outb(APM_CNT_ACPI_ENABLE, APM_CNT); } - -#if TEST_SMM_FLASH_LOCKDOWN - /* Now try this: */ - printk(BIOS_DEBUG, "Locking BIOS to RO... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - reg8 &= ~(1 << 0); /* clear BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); - reg8 |= (1 << 1); /* set BLE */ - pci_write_config8(dev, 0xdc, reg8); - printk(BIOS_DEBUG, "ok.\n"); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - - printk(BIOS_DEBUG, "Writing:\n"); - *(volatile u8 *)0xfff00000 = 0x00; - printk(BIOS_DEBUG, "Testing:\n"); - reg8 |= (1 << 0); /* set BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); - - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - printk(BIOS_DEBUG, "Done.\n"); -#endif } #endif diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 4cc1cea..c7de2a1 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -39,7 +39,6 @@ #define NMI_OFF 0 #define ENABLE_ACPI_MODE_IN_COREBOOT 0 -#define TEST_SMM_FLASH_LOCKDOWN 0 typedef struct southbridge_intel_i82801ix_config config_t; @@ -370,10 +369,6 @@ #if CONFIG(HAVE_SMI_HANDLER) static void i82801ix_lock_smm(struct device *dev) { -#if TEST_SMM_FLASH_LOCKDOWN - u8 reg8; -#endif - if (!acpi_is_wakeup_s3()) { #if ENABLE_ACPI_MODE_IN_COREBOOT printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); @@ -393,33 +388,6 @@ */ if (!CONFIG(PARALLEL_MP)) smm_lock(); - -#if TEST_SMM_FLASH_LOCKDOWN - /* Now try this: */ - printk(BIOS_DEBUG, "Locking BIOS to RO... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - reg8 &= ~(1 << 0); /* clear BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); - reg8 |= (1 << 1); /* set BLE */ - pci_write_config8(dev, 0xdc, reg8); - printk(BIOS_DEBUG, "ok.\n"); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - - printk(BIOS_DEBUG, "Writing:\n"); - *(volatile u8 *)0xfff00000 = 0x00; - printk(BIOS_DEBUG, "Testing:\n"); - reg8 |= (1 << 0); /* set BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); - - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - printk(BIOS_DEBUG, "Done.\n"); -#endif } #endif diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index abfe665..5373ba2 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -40,7 +40,6 @@ #define NMI_OFF 0 #define ENABLE_ACPI_MODE_IN_COREBOOT 0 -#define TEST_SMM_FLASH_LOCKDOWN 0 typedef struct southbridge_intel_i82801jx_config config_t; @@ -375,10 +374,6 @@ #if CONFIG(HAVE_SMI_HANDLER) static void i82801jx_lock_smm(struct device *dev) { -#if TEST_SMM_FLASH_LOCKDOWN - u8 reg8; -#endif - if (!acpi_is_wakeup_s3()) { #if ENABLE_ACPI_MODE_IN_COREBOOT printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); @@ -393,33 +388,6 @@ printk(BIOS_DEBUG, "S3 wakeup, enabling ACPI via APMC\n"); outb(APM_CNT_ACPI_ENABLE, APM_CNT); } - -#if TEST_SMM_FLASH_LOCKDOWN - /* Now try this: */ - printk(BIOS_DEBUG, "Locking BIOS to RO... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - reg8 &= ~(1 << 0); /* clear BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); - reg8 |= (1 << 1); /* set BLE */ - pci_write_config8(dev, 0xdc, reg8); - printk(BIOS_DEBUG, "ok.\n"); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - - printk(BIOS_DEBUG, "Writing:\n"); - *(volatile u8 *)0xfff00000 = 0x00; - printk(BIOS_DEBUG, "Testing:\n"); - reg8 |= (1 << 0); /* set BIOSWE */ - pci_write_config8(dev, 0xdc, reg8); - - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ - printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off", - (reg8&1)?"rw":"ro"); - printk(BIOS_DEBUG, "Done.\n"); -#endif } #endif diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index f4464f3..e7162b1 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -451,9 +451,9 @@ u8 reg8; printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); reg8 &= ~(1 << 5); - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); } static void pch_fixups(struct device *dev) diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 951c69c..b0f57c1 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -510,9 +510,9 @@ u8 reg8; printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... "); - reg8 = pci_read_config8(dev, 0xdc); /* BIOS_CNTL */ + reg8 = pci_read_config8(dev, BIOS_CNTL); reg8 &= ~(1 << 5); - pci_write_config8(dev, 0xdc, reg8); + pci_write_config8(dev, BIOS_CNTL, reg8); } static void pch_fixups(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/29990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0d2b555ada9c2893af4f85422128f5a8b04e2fc6 Gerrit-Change-Number: 29990 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: nb/intel/sandybridge: Move boot_count_increment()
by Patrick Rudolph (Code Review) 13 May '19

13 May '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32067 Change subject: nb/intel/sandybridge: Move boot_count_increment() ...................................................................... nb/intel/sandybridge: Move boot_count_increment() Move boot_count_increment() to romstage.c, drop preprocessor code and only increase counter once on regular boot. Change-Id: I6aa52b75edf19953405b70284c7e7db30f607cd6 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/romstage.c 2 files changed, 5 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/32067/1 diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index b923065..34aec38 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -20,7 +20,6 @@ #include <arch/io.h> #include <device/pci_ops.h> #include <device/pci_def.h> -#include <elog.h> #include <pc80/mc146818rtc.h> #include <romstage_handoff.h> #include "sandybridge.h" @@ -45,22 +44,7 @@ pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); -#if CONFIG(ELOG_BOOT_COUNT) - /* Increment Boot Counter for non-S3 resume */ - if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && - ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) - boot_count_increment(); -#endif - - printk(BIOS_DEBUG, " done.\n"); - -#if CONFIG(ELOG_BOOT_COUNT) - /* Increment Boot Counter except when resuming from S3 */ - if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && - ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) - return; - boot_count_increment(); -#endif + printk(BIOS_DEBUG, " done\n"); } static void sandybridge_setup_graphics(void) diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 8ddc156..96d98ea 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -29,6 +29,7 @@ #include <northbridge/intel/sandybridge/chip.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/pmclib.h> +#include <elog.h> static void early_pch_reset_pmcon(void) { @@ -80,6 +81,9 @@ s3resume = southbridge_detect_s3_resume(); + if (CONFIG(ELOG_BOOT_COUNT) && !s3resume) + boot_count_increment(); + post_code(0x38); mainboard_early_init(s3resume); -- To view, visit https://review.coreboot.org/c/coreboot/+/32067 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6aa52b75edf19953405b70284c7e7db30f607cd6 Gerrit-Change-Number: 32067 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/sandybridge: Update pei_data comments
by Patrick Rudolph (Code Review) 13 May '19

13 May '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32706 Change subject: nb/intel/sandybridge: Update pei_data comments ...................................................................... nb/intel/sandybridge: Update pei_data comments Update outdated comments. Change-Id: I100f71345281a1dc52e99d2395f528d60a9a1f58 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/samsung/lumpy/romstage.c M src/northbridge/intel/sandybridge/pei_data.h 2 files changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/32706/1 diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 1080689..26b9dcc 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -148,7 +148,6 @@ die("SPD data not found."); if (spd_file_len < (spd_index + 1) * 256) die("Missing SPD data."); - // leave onboard dimm address at f0, and copy spd data there. return spd_data[spd_index]; } @@ -198,7 +197,6 @@ }, }; *pei_data = pei_data_template; - // leave onboard dimm address at f0, and copy spd data there. memcpy(pei_data->spd_data[0], locate_spd(), 256); } diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h index 0a60707..8e98bec 100644 --- a/src/northbridge/intel/sandybridge/pei_data.h +++ b/src/northbridge/intel/sandybridge/pei_data.h @@ -105,9 +105,10 @@ uint16_t usb_port_config[16][3]; /* See the usb3 struct above for details */ pch_usb3_controller_settings usb3; - /* SPD data array for onboard RAM. Specify address 0xf0, - * 0xf1, 0xf2, 0xf3 to index one of the 4 slots in - * spd_address for a given "DIMM". + /* SPD data array for onboard RAM. + * spd_data [1..3] are ignored, instead the "dimm_channel{0,1}_disabled" + * flag and the spd_addresses are used to determine which DIMMs should + * use the SPD from spd_data[0]. */ uint8_t spd_data[4][256]; tx_byte_func tx_byte; -- To view, visit https://review.coreboot.org/c/coreboot/+/32706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I100f71345281a1dc52e99d2395f528d60a9a1f58 Gerrit-Change-Number: 32706 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/ec/lenovo/h8/acpi: Serialize Control Method
by HAOUAS Elyes (Code Review) 13 May '19

13 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32745 Change subject: src/ec/lenovo/h8/acpi: Serialize Control Method ...................................................................... src/ec/lenovo/h8/acpi: Serialize Control Method IASL reports warning 'Control Method should be made Serialized'. Change-Id: I034f2c00e912e8f9ef87b9918de1db06fade38b9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/ec/lenovo/h8/acpi/battery.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/32745/1 diff --git a/src/ec/lenovo/h8/acpi/battery.asl b/src/ec/lenovo/h8/acpi/battery.asl index 080f247..5f97ed9 100644 --- a/src/ec/lenovo/h8/acpi/battery.asl +++ b/src/ec/lenovo/h8/acpi/battery.asl @@ -160,7 +160,7 @@ Return (Arg1) } -Method(BINF, 2, NotSerialized) +Method(BINF, 2, Serialized) { Acquire(ECLK, 0xffff) ^BPAG(Or(1, Arg1)) /* Battery 0 static information */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I034f2c00e912e8f9ef87b9918de1db06fade38b9 Gerrit-Change-Number: 32745 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/t400/acpi: Fix ATPR's buffer length
by HAOUAS Elyes (Code Review) 13 May '19

13 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32743 Change subject: mb/t400/acpi: Fix ATPR's buffer length ...................................................................... mb/t400/acpi: Fix ATPR's buffer length Change-Id: Ic9cf16a7494667f6dab156c697fb8f8e9966051e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/lenovo/t400/acpi/graphics.asl 1 file changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/32743/1 diff --git a/src/mainboard/lenovo/t400/acpi/graphics.asl b/src/mainboard/lenovo/t400/acpi/graphics.asl index 818ea93..ff6923b 100644 --- a/src/mainboard/lenovo/t400/acpi/graphics.asl +++ b/src/mainboard/lenovo/t400/acpi/graphics.asl @@ -57,15 +57,17 @@ Method (ATPX, 2, Serialized) { /* Create local variables */ - Name (ATPR, Buffer (0x08) { + Name (ATPR, Buffer (0x10) { + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }) CreateWordField (ATPR, 0x00, SIZE) CreateWordField (ATPR, 0x02, VERS) - CreateDWordField (ATPR, 0x02, MASK) - CreateDWordField (ATPR, 0x04, FUNC) - CreateDWordField (ATPR, 0x06, FLAG) + CreateDWordField (ATPR, 0x04, MASK) + CreateDWordField (ATPR, 0x08, FUNC) + CreateDWordField (ATPR, 0x10, FLAG) /* Version request */ if (LEqual(Arg0, 0x0)) -- To view, visit https://review.coreboot.org/c/coreboot/+/32743 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9cf16a7494667f6dab156c697fb8f8e9966051e Gerrit-Change-Number: 32743 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: libpayload/drivers/i8042: Add fallthrough comment
by Jacob Garber (Code Review) 13 May '19

13 May '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32750 Change subject: libpayload/drivers/i8042: Add fallthrough comment ...................................................................... libpayload/drivers/i8042: Add fallthrough comment Ctrl-delete does nothing, so it falls through to the default case. Add a comment to make this explicit. Found-by: Coverity Scan #1260878 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Change-Id: I4a6f51cb04696b6ebcb554c5667a5bbea58622c1 --- M payloads/libpayload/drivers/i8042/keyboard.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/32750/1 diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c index 1035bf2..87d8d29 100644 --- a/payloads/libpayload/drivers/i8042/keyboard.c +++ b/payloads/libpayload/drivers/i8042/keyboard.c @@ -258,6 +258,7 @@ /* vulcan nerve pinch */ if ((modifier & KB_MOD_ALT) && reset_handler) reset_handler(); + /* fallthrough */ default: ret = 0; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32750 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4a6f51cb04696b6ebcb554c5667a5bbea58622c1 Gerrit-Change-Number: 32750 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/inteltool: Error if first channel is not found
by Jacob Garber (Code Review) 13 May '19

13 May '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32713 Change subject: util/inteltool: Error if first channel is not found ...................................................................... util/inteltool: Error if first channel is not found The first channel is needed to initialize the timing arrays. If it is not present there will be undefined reads in the 'print_time' function calls starting on line 182. Found-by: Coverity Scan #1370{584,585,588,589,590-596,600} Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Change-Id: I6b59989242e498474782876302e0850e3e4cf2d3 --- M util/inteltool/ivy_memory.c 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/32713/1 diff --git a/util/inteltool/ivy_memory.c b/util/inteltool/ivy_memory.c index 8ce8611..c079071 100644 --- a/util/inteltool/ivy_memory.c +++ b/util/inteltool/ivy_memory.c @@ -97,7 +97,13 @@ rankmap[channel] = read_mchbar32(0xc14 + 0x100 * channel) >> 24; } - two_channels = rankmap[0] && rankmap[1]; + // The second channel is optional, but the first channel is not + if (rankmap[0] == 0) { + fputs("Error: first channel not found\n", stderr); + exit(1); + } + + two_channels = rankmap[1]; mr0[0] = read_mchbar32(0x0004); mr1[0] = read_mchbar32(0x0008); -- To view, visit https://review.coreboot.org/c/coreboot/+/32713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b59989242e498474782876302e0850e3e4cf2d3 Gerrit-Change-Number: 32713 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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