coreboot-gerrit May 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: util/intelvbttool: Free file object on error path
by Jacob Garber (Code Review) 13 May '19

13 May '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32685 Change subject: util/intelvbttool: Free file object on error path ...................................................................... util/intelvbttool: Free file object on error path Prevents a memory leak. Found-by: Coverity Scan #1396047 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Change-Id: I4c72a17351d8afbe23302edfeeba74b17608aef2 --- M util/intelvbttool/intelvbttool.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/32685/1 diff --git a/util/intelvbttool/intelvbttool.c b/util/intelvbttool/intelvbttool.c index f8e4bda..715b39a 100644 --- a/util/intelvbttool/intelvbttool.c +++ b/util/intelvbttool/intelvbttool.c @@ -1028,8 +1028,10 @@ if (old_vbt) { if (oh->vbt_offset + vbt_size(old_vbt) == fo->size) { /* Located at the end of file - reduce file size */ - if (fo->size < vbt_size(old_vbt)) + if (fo->size < vbt_size(old_vbt)) { + free_fo(old_vbt); return 1; + } fo = remalloc_fo(fo, fo->size - vbt_size(old_vbt)); if (!fo) { printerr("Failed to allocate memory\n"); -- To view, visit https://review.coreboot.org/c/coreboot/+/32685 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c72a17351d8afbe23302edfeeba74b17608aef2 Gerrit-Change-Number: 32685 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/ifdtool: Add find_fd null check
by Jacob Garber (Code Review) 13 May '19

13 May '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32691 Change subject: util/ifdtool: Add find_fd null check ...................................................................... util/ifdtool: Add find_fd null check As the previous comment indicated, this null check is currently superfluous, but adding it in makes Coverity happy, and future-proofs the code in case someone changes the internals of 'find_fcba' later and forgets/doesn't know to update this error check. Found-by: Coverity Scan #1395066 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Change-Id: I594cd0098f5b36cef5b3efc4c904710d3ba9b815 --- M util/ifdtool/ifdtool.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/32691/1 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index a97f352..6c5e784 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -236,7 +236,7 @@ int read_freq; const fcba_t *fcba = find_fcba(image, size); const fdbar_t *fdb = find_fd(image, size); - if (!fcba) /* a valid fcba indicates a valid fdb */ + if (!fcba || !fdb) exit(EXIT_FAILURE); chipset = guess_ich_chipset(fdb); -- To view, visit https://review.coreboot.org/c/coreboot/+/32691 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I594cd0098f5b36cef5b3efc4c904710d3ba9b815 Gerrit-Change-Number: 32691 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src/mainboard/libretrend/lt1000: Initial commit
by Michał Żygowski (Code Review) 13 May '19

13 May '19

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30360 ) Change subject: src/mainboard/libretrend/lt1000: Initial commit ...................................................................... Patch Set 8: (12 comments) https://review.coreboot.org/#/c/30360/6/src/ec/libretrend/lt1000/Kconfig File src/ec/libretrend/lt1000/Kconfig: https://review.coreboot.org/#/c/30360/6/src/ec/libretrend/lt1000/Kconfig@1 PS6, Line 1: EC_LIBRETREND_LT1000 > this symbol is unused. Removed as it won't be used. EC is configured along with SuperIO. https://review.coreboot.org/#/c/30360/3/src/mainboard/libretrend/lt1000/Kco… File src/mainboard/libretrend/lt1000/Kconfig: https://review.coreboot.org/#/c/30360/3/src/mainboard/libretrend/lt1000/Kco… PS3, Line 63: onfig CPU_MICROCODE_CBFS_LOC : hex : default 0xFFE115A0 : : config CBFS_SIZE : hex : default 0x5c0000 > if you are not using FSP-T this is not needed. Done https://review.coreboot.org/#/c/30360/6/src/mainboard/libretrend/lt1000/Kco… File src/mainboard/libretrend/lt1000/Kconfig: https://review.coreboot.org/#/c/30360/6/src/mainboard/libretrend/lt1000/Kco… PS6, Line 10: select NO_FIXED_XIP_ROM_SIZE : select FSP_M_XIP > This is already done in the soc Kconfig. Done https://review.coreboot.org/#/c/30360/6/src/mainboard/libretrend/lt1000/Kco… PS6, Line 27: if BOARD_LIBRETREND_LT1000 > I assume this is for future expansions? Removed, no future expansion planned. https://review.coreboot.org/#/c/30360/6/src/mainboard/libretrend/lt1000/Kco… PS6, Line 32: : config DEVICETREE : string : default "devicetree.cb" > No need to redefine the default value. Done https://review.coreboot.org/#/c/30360/6/src/mainboard/libretrend/lt1000/Mak… File src/mainboard/libretrend/lt1000/Makefile.inc: https://review.coreboot.org/#/c/30360/6/src/mainboard/libretrend/lt1000/Mak… PS6, Line 16: $(CONFIG_SUPERIO_ITE_COMMON_ROMSTAGE) > why is this conditional on this board? Old code base. Removed the condition. https://review.coreboot.org/#/c/30360/3/src/mainboard/libretrend/lt1000/dev… File src/mainboard/libretrend/lt1000/devicetree.cb: https://review.coreboot.org/#/c/30360/3/src/mainboard/libretrend/lt1000/dev… PS3, Line 283: io 0x60 = 0x3e8 : irq 0x70 = 7 : irq 0xf0 = 0x01 : irq 0xf1 = 0x53 > do you need to set these resources if the device ends up being disabled? These values are set by default either way. Removed those entries. However COM3 is intended to be enabled. Was temporarily disabled until I find a solution for a bug: https://review.coreboot.org/c/coreboot/+/30360/8/src/mainboard/libretrend/l… https://review.coreboot.org/#/c/30360/6/src/mainboard/libretrend/lt1000/dev… File src/mainboard/libretrend/lt1000/devicetree.cb: https://review.coreboot.org/#/c/30360/6/src/mainboard/libretrend/lt1000/dev… PS6, Line 13: activaction > activation Done https://review.coreboot.org/#/c/30360/6/src/mainboard/libretrend/lt1000/dev… PS6, Line 272: turn off ? > This type of LDN usually refers to a device connected through a PS/2 port. […] Yes, it does. There is PS2 pin header on board (although no connectors on the case). Enabling it in case someone would like to connect an extension cable. https://review.coreboot.org/#/c/30360/6/src/mainboard/libretrend/lt1000/dev… PS6, Line 277: turn off ? > Same as above Answer the same as above. https://review.coreboot.org/#/c/30360/7/src/mainboard/libretrend/lt1000/dev… File src/mainboard/libretrend/lt1000/devicetree.cb: https://review.coreboot.org/#/c/30360/7/src/mainboard/libretrend/lt1000/dev… PS7, Line 214: device pci 1c.0 on end # PCI Express Port 1 > add smbios_slot_desc for M. […] I still need to figure out how many PCI Express lanes does the M.2 slot uses. I know it is SATA/NVMe compatible, but I posses only limited schematics. Have to try some NVMe first https://review.coreboot.org/#/c/30360/6/src/mainboard/libretrend/lt1000/hda… File src/mainboard/libretrend/lt1000/hda_verb.h: https://review.coreboot.org/#/c/30360/6/src/mainboard/libretrend/lt1000/hda… PS6, Line 42: /* Pin Complex (NID 0x12) */ > Those comments don't seem to add useful information. The verbs are copy-paste from Librem board. They are not implemented yet, thus removed for now. Any guidance how can I correctly implement the verb data? -- To view, visit https://review.coreboot.org/c/coreboot/+/30360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab Gerrit-Change-Number: 30360 Gerrit-PatchSet: 8 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 13 May 2019 09:09:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in ...coreboot[master]: superio/ite: Add IT8786E-I
by Michał Żygowski (Code Review) 13 May '19

13 May '19

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30335 ) Change subject: superio/ite: Add IT8786E-I ...................................................................... Patch Set 7: (2 comments) https://review.coreboot.org/#/c/30335/6/src/superio/ite/it8786e/superio.c File src/superio/ite/it8786e/superio.c: https://review.coreboot.org/#/c/30335/6/src/superio/ite/it8786e/superio.c@62 PS6, Line 62: &ops > these should be all NULL, since no LDN-specific override is needed here. […] Done https://review.coreboot.org/#/c/30335/6/src/superio/ite/it8786e/superio.c@1… PS6, Line 112: &pnp_ops > this needs to be &ops Thank You Felix, I overlooked that when rebasing. -- To view, visit https://review.coreboot.org/c/coreboot/+/30335 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7317da6a72db64f95f9a790ef96ed7a5f93b3aea Gerrit-Change-Number: 30335 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Mon, 13 May 2019 08:57:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/mainboard/libretrend/lt1000: Initial commit
by Michał Żygowski (Code Review) 13 May '19

13 May '19

Hello Patrick Rudolph, Piotr Król, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30360 to look at the new patch set (#8). Change subject: src/mainboard/libretrend/lt1000: Initial commit ...................................................................... src/mainboard/libretrend/lt1000: Initial commit Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- A src/mainboard/libretrend/Kconfig A src/mainboard/libretrend/Kconfig.name A src/mainboard/libretrend/lt1000/Kconfig A src/mainboard/libretrend/lt1000/Kconfig.name A src/mainboard/libretrend/lt1000/Makefile.inc A src/mainboard/libretrend/lt1000/acpi/ec.asl A src/mainboard/libretrend/lt1000/acpi/mainboard.asl A src/mainboard/libretrend/lt1000/acpi/superio.asl A src/mainboard/libretrend/lt1000/acpi_tables.c A src/mainboard/libretrend/lt1000/board_info.txt A src/mainboard/libretrend/lt1000/bootblock.c A src/mainboard/libretrend/lt1000/devicetree.cb A src/mainboard/libretrend/lt1000/dsdt.asl A src/mainboard/libretrend/lt1000/gpio.h A src/mainboard/libretrend/lt1000/hda_verb.c A src/mainboard/libretrend/lt1000/mainboard.c A src/mainboard/libretrend/lt1000/ramstage.c A src/mainboard/libretrend/lt1000/romstage.c 18 files changed, 983 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/30360/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/30360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I32fc8a7d3177ba379d04ad8b87adefcfca2b0fab Gerrit-Change-Number: 30360 Gerrit-PatchSet: 8 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: superio/ite: Add IT8786E-I
by Michał Żygowski (Code Review) 13 May '19

13 May '19

Hello Kyösti Mälkki, Patrick Rudolph, Felix Held, Piotr Król, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30335 to look at the new patch set (#7). Change subject: superio/ite: Add IT8786E-I ...................................................................... superio/ite: Add IT8786E-I Based on IT8786E-I V0.4.1 datasheet with following remark: "Please note that the IT8786E-I V0.4.1 is applicable only to the D version." Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> Change-Id: I7317da6a72db64f95f9a790ef96ed7a5f93b3aea --- M src/superio/ite/Makefile.inc A src/superio/ite/it8786e/Kconfig A src/superio/ite/it8786e/Makefile.inc A src/superio/ite/it8786e/acpi/superio.asl A src/superio/ite/it8786e/chip.h A src/superio/ite/it8786e/it8786e.h A src/superio/ite/it8786e/superio.c 7 files changed, 395 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/30335/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/30335 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7317da6a72db64f95f9a790ef96ed7a5f93b3aea Gerrit-Change-Number: 30335 Gerrit-PatchSet: 7 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: TEMP: NOT FOR REVIEW: qcs405: Add bl31 stage and elf
by build bot (Jenkins) (Code Review) 13 May '19

13 May '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29981 ) Change subject: TEMP: NOT FOR REVIEW: qcs405: Add bl31 stage and elf ...................................................................... Patch Set 24: (1 comment) https://review.coreboot.org/#/c/29981/24/src/soc/qualcomm/qcs405/soc.c File src/soc/qualcomm/qcs405/soc.c: https://review.coreboot.org/#/c/29981/24/src/soc/qualcomm/qcs405/soc.c@26 PS24, Line 26: bootmem_add_range((uintptr_t)_dram_reserved, _dram_reserved_size, BM_MEM_BL31); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I967c0b78a3561574609bf8332a22838c85e43429 Gerrit-Change-Number: 29981 Gerrit-PatchSet: 24 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 13 May 2019 08:24:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: TEMP: NOT FOR REVIEW: QCS405: Added RPM support
by Nitheesh Sekar (Code Review) 13 May '19

13 May '19

Hello Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29970 to look at the new patch set (#25). Change subject: TEMP: NOT FOR REVIEW: QCS405: Added RPM support ...................................................................... TEMP: NOT FOR REVIEW: QCS405: Added RPM support This patch adds support to read RPM image from 3rdparty/blobs and load it. It takes RPM out of reset. Note that, clock_reset_rpm function to touch the GCC registers actually should reside in clock.c, but for now keeping it here till clock patches are posted. Change-Id: I17f491f0a4bd0dce7522b7e80e1bac97ec18b945 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/include/soc/memlayout.ld A src/soc/qualcomm/qcs405/include/soc/rpm.h M src/soc/qualcomm/qcs405/include/soc/symbols.h M src/soc/qualcomm/qcs405/mmu.c A src/soc/qualcomm/qcs405/rpm_load_reset.c M src/soc/qualcomm/qcs405/soc.c 7 files changed, 106 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/29970/25 -- To view, visit https://review.coreboot.org/c/coreboot/+/29970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17f491f0a4bd0dce7522b7e80e1bac97ec18b945 Gerrit-Change-Number: 29970 Gerrit-PatchSet: 25 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: qclib: Add qclib support with interface tables
by Nitheesh Sekar (Code Review) 13 May '19

13 May '19

Hello Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29967 to look at the new patch set (#25). Change subject: qclib: Add qclib support with interface tables ...................................................................... qclib: Add qclib support with interface tables Add to load and execute qclib blob to configure pmic, clocks and ddr.This also loads the qcsdi, cdt blob. Added support for interface tables to read ddr info from qclib and do ddr one time training based on it. Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/mainboard/google/mistral/Makefile.inc M src/mainboard/google/mistral/romstage.c M src/soc/qualcomm/common/qclib.c M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/include/soc/memlayout.ld A src/soc/qualcomm/qcs405/include/soc/qclib.h M src/soc/qualcomm/qcs405/include/soc/symbols.h M src/soc/qualcomm/qcs405/mmu.c A src/soc/qualcomm/qcs405/soc_blob_load.c 9 files changed, 149 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/29967/25 -- To view, visit https://review.coreboot.org/c/coreboot/+/29967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I534af71163d034ea04420dda6a94ce31b08c8a07 Gerrit-Change-Number: 29967 Gerrit-PatchSet: 25 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/google/poppy/variants/rammus: Support new onboard Hynix memory
by Furquan Shaikh (Code Review) 13 May '19

13 May '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32674 ) Change subject: mb/google/poppy/variants/rammus: Support new onboard Hynix memory ...................................................................... Patch Set 3: > Patch Set 3: > > > Patch Set 3: > > > > File src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCLGALAR-NVD.spd.hex has one or more executable bits set in the file permissions. > > Is it cause by we submit CL by A user but modify file by B user ? No. The file permissions are set incorrectly in the first patchset too. -- To view, visit https://review.coreboot.org/c/coreboot/+/32674 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibd02953d0c6ac62fa4d7751fd8b103b74433aa73 Gerrit-Change-Number: 32674 Gerrit-PatchSet: 3 Gerrit-Owner: YanRu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: YanRu Chen <kane_chen(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Comment-Date: Mon, 13 May 2019 06:32:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit May 2019