Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29669 )
Change subject: cpu/intel/sandybridge: Add `hyper_threading` option
......................................................................
Patch Set 2:
Can we make this a common intel cpu change with an interface for multiple cpu implementations.
It works btw, I am using it for 3 months or so
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29669 )
Change subject: cpu/intel/sandybridge: Add `hyper_threading` option
......................................................................
Patch Set 2:
Now that the MP init patches are merged, this should work.
Just needs somebody to test :)
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Hello Patrick Rudolph, Huang Jin, Arthur Heymans, York Yang, Lee Leahy, Matt DeVillier, build bot (Jenkins), Hannah Williams, Michał Żygowski, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29662
to look at the new patch set (#20).
Change subject: {drivers,soc/intel/braswell}: Add C_ENVIRONMENT_BOOTBLOCK support
......................................................................
{drivers,soc/intel/braswell}: Add C_ENVIRONMENT_BOOTBLOCK support
No C_ENVIRONMENT_BOOTBLOCK support for Braswell is available.
Enable support and add required files for the Braswell Bootblock in C.
The next changes are made support C_ENVIRONMENT_BOOTBLOCK:
- Add post init console functions romstage_c_entry() .
- Add car_stage_entry() function bootblock-c_entry() functions.
- Specify config DCACHE_BSP_STACK_SIZE and C_ENV_BOOTBLOCK_SIZE.
- Add bootblokc_c_entry().
Removed the unused cache_as_ram_main().
BUG=NA
TEST=Booting Embedded Linux on Facebook FBG-1701
Building Google Banos
Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
---
M src/drivers/intel/fsp1_1/Makefile.inc
M src/drivers/intel/fsp1_1/car.c
M src/drivers/intel/fsp1_1/include/fsp/car.h
M src/soc/intel/braswell/Kconfig
M src/soc/intel/braswell/Makefile.inc
M src/soc/intel/braswell/bootblock/bootblock.c
R src/soc/intel/braswell/bootblock/cache_as_ram.S
M src/soc/intel/braswell/romstage/Makefile.inc
A src/soc/intel/braswell/romstage/car_stage_entry.S
9 files changed, 88 insertions(+), 168 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/29662/20
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Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29662 )
Change subject: {drivers,soc/intel/braswell}: Add C_ENVIRONMENT_BOOTBLOCK support
......................................................................
Patch Set 19:
(2 comments)
Will upload new patch set.
https://review.coreboot.org/#/c/29662/19/src/soc/intel/braswell/Kconfig
File src/soc/intel/braswell/Kconfig:
https://review.coreboot.org/#/c/29662/19/src/soc/intel/braswell/Kconfig@57
PS19, Line 57: default 0x2000
> That should be 0x4000 as lzma decoder takes about 16KiB of stack to decompress the next stage. […]
Using value of 0x4000 causes hang on platform without POSTCAR.
Is this 0x4000 also required when Bootblock in C?
https://review.coreboot.org/#/c/29662/19/src/soc/intel/braswell/Kconfig@110
PS19, Line 110: default 0x8000 if VBOOT
> any reason not using 0x8000 as default?
Reason is that 0x4000 works fine on our system.
Tested and confirm that 0x8000 is working fine also.
Will use 0x8000 always.
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Matt DeVillier has uploaded a new patch set (#14) to the change originally created by Nicola Corna. ( https://review.coreboot.org/c/coreboot/+/21107 )
Change subject: sb,soc/intel: Fix flashconsole on older architectures
......................................................................
sb,soc/intel: Fix flashconsole on older architectures
Building coreboot with CONSOLE_SPI_FLASH on Sandybridge (and others) fails
with the following errors:
build/romstage/drivers/spi/spi-generic.o: In function `spi_setup_slave':
src/drivers/spi/spi-generic.c:119: undefined reference to `spi_ctrlr_bus_map'
src/drivers/spi/spi-generic.c:121: undefined reference to `spi_ctrlr_bus_map_count'
src/drivers/spi/spi-generic.c:124: undefined reference to `spi_ctrlr_bus_map'
This is due to the fact that sb/intel/common/spi.c is currently not built
in romstage, but drivers/spi/spi-generic.c requires it.
In this commit sb/intel/common/spi.c is adapted to the romstage and it is
added to it.
The qemu-q35 mainboard also had to have the LAPIC_MONOTONIC_TIMER config selected
because its southbridge now selects the common/spi which selects SPI_FLASH, and the
drivers/spi/spi_flash.c uses timer_monotonic_get. Other boards will usually
have the LAPIC_MONOTONIC_TIMER config enabled from their northbridge, but
qemu-q35 has no config for a northbridge, so it had to be added manually
for compilation to succeed.
In this commit, the broadwell monotonic_timer was also modified to be simpler
and not reset to 0 at every stage (based on a now deprecated/removed change in
the skylake implementation).
Change-Id: Ifd3e8621fa4cb349b7e0e07118cab0380f24ff55
Signed-off-by: Nicola Corna <nicola(a)corna.info>
Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/mainboard/emulation/qemu-q35/Kconfig
M src/soc/intel/baytrail/Makefile.inc
M src/soc/intel/baytrail/spi.c
M src/soc/intel/braswell/Makefile.inc
M src/soc/intel/braswell/spi.c
M src/soc/intel/broadwell/Makefile.inc
M src/soc/intel/broadwell/monotonic_timer.c
M src/soc/intel/broadwell/spi.c
M src/soc/intel/fsp_baytrail/Makefile.inc
M src/soc/intel/fsp_baytrail/spi.c
M src/southbridge/intel/common/spi.c
M src/southbridge/intel/i82801ix/Kconfig
12 files changed, 213 insertions(+), 206 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/21107/14
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