coreboot-gerrit May 2019

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Change in ...coreboot[master]: src/northbridge: Add missing 'include <types.h>'
by Lijian Zhao (Code Review) 15 May '19

15 May '19

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32808 ) Change subject: src/northbridge: Add missing 'include <types.h>' ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/32808/1/src/northbridge/intel/sandybridge/e… File src/northbridge/intel/sandybridge/early_init.c: https://review.coreboot.org/#/c/32808/1/src/northbridge/intel/sandybridge/e… PS1, Line 18: I thought stdlib.h still need to be kept according to commit message? -- To view, visit https://review.coreboot.org/c/coreboot/+/32808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad5367bed844b866b2ad87639eee29a16d9a99ed Gerrit-Change-Number: 32808 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Comment-Date: Wed, 15 May 2019 20:44:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/scaleway/tagada: GPIO on M.2 PCIe/SATA configure FSP HSIO lanes
by Patrick Georgi (Code Review) 15 May '19

15 May '19

Patrick Georgi has uploaded a new patch set (#12) to the change originally created by Julien Viard de Galbert. ( https://review.coreboot.org/c/coreboot/+/25436 ) Change subject: mb/scaleway/tagada: GPIO on M.2 PCIe/SATA configure FSP HSIO lanes ...................................................................... mb/scaleway/tagada: GPIO on M.2 PCIe/SATA configure FSP HSIO lanes Change-Id: Ic3ed97fc2b54d4974ec0b41b9f207fe3d49d2cce Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- A src/mainboard/scaleway/tagada/gpio_defs.h M src/mainboard/scaleway/tagada/hsio.c M src/mainboard/scaleway/tagada/hsio.h 3 files changed, 106 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/25436/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/25436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3ed97fc2b54d4974ec0b41b9f207fe3d49d2cce Gerrit-Change-Number: 25436 Gerrit-PatchSet: 12 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: util/lint/check-style: Don't hardcode clang-format path
by Alex James (Code Review) 15 May '19

15 May '19

Alex James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32707 Change subject: util/lint/check-style: Don't hardcode clang-format path ...................................................................... util/lint/check-style: Don't hardcode clang-format path Signed-off-by: Alex James <theracermaster(a)gmail.com> Change-Id: I688cb60c98370bf74aa8554bab43594ff84c4e24 --- M util/lint/check-style 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/32707/1 diff --git a/util/lint/check-style b/util/lint/check-style index 1ac51b4..2237ed6 100755 --- a/util/lint/check-style +++ b/util/lint/check-style @@ -15,7 +15,7 @@ ################################################################## # SETTINGS # set path to clang-format binary -CLANG_FORMAT="/usr/bin/clang-format" +CLANG_FORMAT="$(command -v clang-format)" # remove any older patches from previous commits. Set to true or false. # DELETE_OLD_PATCHES=false -- To view, visit https://review.coreboot.org/c/coreboot/+/32707 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I688cb60c98370bf74aa8554bab43594ff84c4e24 Gerrit-Change-Number: 32707 Gerrit-PatchSet: 1 Gerrit-Owner: Alex James <theracermaster(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: timestamps: denote "end of romstage" right before loading ramstage
by Patrick Georgi (Code Review) 15 May '19

15 May '19

Patrick Georgi has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/27329 ) Change subject: timestamps: denote "end of romstage" right before loading ramstage ...................................................................... Abandoned obsolete -- To view, visit https://review.coreboot.org/c/coreboot/+/27329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3524a757f5274815d62a17c58a18ed6b9aa726bf Gerrit-Change-Number: 27329 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: soc/intel/denverton_ns: Implement PCIe post config + lock
by Patrick Georgi (Code Review) 15 May '19

15 May '19

Patrick Georgi has uploaded a new patch set (#12) to the change originally created by Julien Viard de Galbert. ( https://review.coreboot.org/c/coreboot/+/25442 ) Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock ...................................................................... soc/intel/denverton_ns: Implement PCIe post config + lock - Configure PCIe maximum payload size to fix Intel SSD - Lock Down PCIe Configuration Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/soc/intel/denverton_ns/lpc.c 1 file changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/25442/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/25442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd Gerrit-Change-Number: 25442 Gerrit-PatchSet: 12 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: soc/intel/denverton_ns: Implement PCIe post config + lock
by build bot (Jenkins) (Code Review) 15 May '19

15 May '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25442 ) Change subject: soc/intel/denverton_ns: Implement PCIe post config + lock ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/#/c/25442/11/src/soc/intel/denverton_ns/lpc.c File src/soc/intel/denverton_ns/lpc.c: https://review.coreboot.org/#/c/25442/11/src/soc/intel/denverton_ns/lpc.c@4… PS11, Line 420: if(!relax_security) space required before the open parenthesis '(' -- To view, visit https://review.coreboot.org/c/coreboot/+/25442 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic028ae9920e932dfe67fdfc0c6f1f53377a158cd Gerrit-Change-Number: 25442 Gerrit-PatchSet: 11 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Comment-Date: Wed, 15 May 2019 19:34:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/denverton_ns: Generate ACPI DMAR Table
by Patrick Georgi (Code Review) 15 May '19

15 May '19

Patrick Georgi has uploaded a new patch set (#11) to the change originally created by Julien Viard de Galbert. ( https://review.coreboot.org/c/coreboot/+/25446 ) Change subject: soc/intel/denverton_ns: Generate ACPI DMAR Table ...................................................................... soc/intel/denverton_ns: Generate ACPI DMAR Table - Write ACPI DMAR Table if VT-d is enabled. - The entries are defined to follow FSP settings. Change-Id: I263b03b96280599266d4c5e193583ecdfe9697b7 Signed-off-by: Julien Viard de Galbert <jviarddegalbert(a)online.net> --- M src/soc/intel/denverton_ns/acpi.c M src/soc/intel/denverton_ns/include/soc/acpi.h M src/soc/intel/denverton_ns/include/soc/iomap.h M src/soc/intel/denverton_ns/include/soc/pci_devs.h M src/soc/intel/denverton_ns/include/soc/systemagent.h M src/soc/intel/denverton_ns/systemagent.c 6 files changed, 81 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/25446/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/25446 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I263b03b96280599266d4c5e193583ecdfe9697b7 Gerrit-Change-Number: 25446 Gerrit-PatchSet: 11 Gerrit-Owner: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Julien Viard de Galbert <coreboot-review-ju(a)vdg.name> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vanny E <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jay Talbott <JayTalbott(a)sysproconsulting.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: nb/intel/sandybridge: Move DMI init code
by Patrick Georgi (Code Review) 15 May '19

15 May '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32073 ) Change subject: nb/intel/sandybridge: Move DMI init code ...................................................................... Patch Set 8: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/32073/8/src/southbridge/intel/bd82x6x/early… File src/southbridge/intel/bd82x6x/early_pch.c: https://review.coreboot.org/#/c/32073/8/src/southbridge/intel/bd82x6x/early… PS8, Line 73: early_pch_init_native_dmi_init1 maybe dmi_pre and dmi_post? -- To view, visit https://review.coreboot.org/c/coreboot/+/32073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0b47391f3309f9ab0c3a3a8d525f38f8cca73c0 Gerrit-Change-Number: 32073 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 15 May 2019 18:37:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/sandybridge: Move DMI init code
by HAOUAS Elyes (Code Review) 15 May '19

15 May '19

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32073 ) Change subject: nb/intel/sandybridge: Move DMI init code ...................................................................... Patch Set 8: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/32073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0b47391f3309f9ab0c3a3a8d525f38f8cca73c0 Gerrit-Change-Number: 32073 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 15 May 2019 18:28:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/mainboard: Remove unneeded include <arch/io.h>
by HAOUAS Elyes (Code Review) 15 May '19

15 May '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32783 Change subject: src/mainboard: Remove unneeded include <arch/io.h> ...................................................................... src/mainboard: Remove unneeded include <arch/io.h> Change-Id: I73c557d6ef009fb2cac35fdea500dee76f525330 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/asus/p5qpl-am/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/dcp847ske/early_southbridge.c M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/z61t/romstage.c 10 files changed, 0 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/32783/1 diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 468cffb..1c84c84 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -18,7 +18,6 @@ /* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ #include <stdint.h> -#include <arch/io.h> #include <cf9_reset.h> #include <device/pci_ops.h> #include <device/pci_def.h> diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index 08379f7..b076b9d 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -18,7 +18,6 @@ // __PRE_RAM__ means: use "unsigned" for device, not a struct. #include <stdint.h> -#include <arch/io.h> #include <cf9_reset.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index bd6bfc6..7d02843 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -15,7 +15,6 @@ * GNU General Public License for more details. */ -#include <arch/io.h> #include <cf9_reset.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 9cb1144..c98556c 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -16,7 +16,6 @@ // __PRE_RAM__ means: use "unsigned" for device, not a struct. #include <stdint.h> -#include <arch/io.h> #include <cf9_reset.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 1673622..6561927 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -15,7 +15,6 @@ #include <string.h> #include <bootmode.h> -#include <arch/io.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 778525f..705ace9 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -17,7 +17,6 @@ */ #include <stdint.h> -#include <arch/io.h> #include <cf9_reset.h> #include <device/pci_ops.h> #include <device/pci_def.h> diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index 219eefb..699141f 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -15,7 +15,6 @@ #include <string.h> #include <bootmode.h> -#include <arch/io.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index b85bd68..85a82c5 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -16,7 +16,6 @@ /* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ #include <stdint.h> -#include <arch/io.h> #include <cf9_reset.h> #include <console/console.h> #include <cpu/intel/romstage.h> diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index ea93707..b66ef66 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -18,7 +18,6 @@ // __PRE_RAM__ means: use "unsigned" for device, not a struct. #include <stdint.h> -#include <arch/io.h> #include <cf9_reset.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 47a52db..502eac3 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -18,7 +18,6 @@ // __PRE_RAM__ means: use "unsigned" for device, not a struct. #include <stdint.h> -#include <arch/io.h> #include <cf9_reset.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/32783 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73c557d6ef009fb2cac35fdea500dee76f525330 Gerrit-Change-Number: 32783 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit May 2019