coreboot-gerrit May 2019

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Change in ...coreboot[master]: coreboot: add post code for hardware initialization failure
by Keith Short (Code Review) 16 May '19

16 May '19

Hello Patrick Rudolph, Huang Jin, Philipp Deppenwiese, build bot (Jenkins), Martin Roth, Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/32774 to look at the new patch set (#3). Change subject: coreboot: add post code for hardware initialization failure ...................................................................... coreboot: add post code for hardware initialization failure Add a new post code POST_HW_INIT_FAILURE, used when coreboot fails to detect or initialize a required hardware component. BUG=b:124401932 BRANCH=sarien TEST=build coreboot for sarien and arcada platforms Change-Id: I73820d24b3e1c269d9d446a78ef4f97e167e3552 Signed-off-by: Keith Short <keithshort(a)chromium.org> --- M src/console/Makefile.inc M src/include/console/post_codes.h M src/soc/intel/apollolake/memmap.c M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/cannonlake/memmap.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/fsp_baytrail/southcluster.c M src/soc/intel/icelake/memmap.c M src/soc/intel/quark/i2c.c 11 files changed, 33 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/32774/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/32774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73820d24b3e1c269d9d446a78ef4f97e167e3552 Gerrit-Change-Number: 32774 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: nb/intel/sandybridge: Move DMI init code
by Patrick Georgi (Code Review) 16 May '19

16 May '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32073 ) Change subject: nb/intel/sandybridge: Move DMI init code ...................................................................... nb/intel/sandybridge: Move DMI init code Move the DMI initialization code to northbridge folder. Leave southbridge specific settings in bd82x6x folder and call it from northbridge code. Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to OS, no errors visible in dmesg. Change-Id: Ib0b47391f3309f9ab0c3a3a8d525f38f8cca73c0 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32073 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/northbridge/intel/sandybridge/Makefile.inc A src/northbridge/intel/sandybridge/early_dmi.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/sandybridge.h M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/pch.h 6 files changed, 236 insertions(+), 204 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index cc4ddaf..ba55466 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -29,6 +29,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += common.c ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) +romstage-y += early_dmi.c romstage-y += raminit.c romstage-y += raminit_common.c romstage-y += raminit_sandy.c diff --git a/src/northbridge/intel/sandybridge/early_dmi.c b/src/northbridge/intel/sandybridge/early_dmi.c new file mode 100644 index 0000000..db49040 --- /dev/null +++ b/src/northbridge/intel/sandybridge/early_dmi.c @@ -0,0 +1,226 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Vladimir Serbinenko <phcoder(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <southbridge/intel/bd82x6x/pch.h> + +void early_init_dmi(void) +{ + volatile u32 tmp; + int i; + + DMIBAR32(0x0914) |= 0x80000000; + DMIBAR32(0x0934) |= 0x80000000; + + for (i = 0; i < 4; i++) { + DMIBAR32(0x0a00 + (i << 4)) &= 0xf3ffffff; + DMIBAR32(0x0a04 + (i << 4)) |= 0x800; + } + DMIBAR32(0x0c30) = (DMIBAR32(0x0c30) & 0xfffffff) | 0x40000000; + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0904 + (i << 5)) &= 0xfe3fffff; + DMIBAR32(0x090c + (i << 5)) &= 0xfff1ffff; + } + + DMIBAR32(0x090c) &= 0xfe1fffff; + DMIBAR32(0x092c) &= 0xfe1fffff; + + tmp = DMIBAR32(0x0904); // !!! = 0x7a1842ec + DMIBAR32(0x0904) = 0x7a1842ec; + tmp = DMIBAR32(0x090c); // !!! = 0x00000208 + DMIBAR32(0x090c) = 0x00000128; + tmp = DMIBAR32(0x0924); // !!! = 0x7a1842ec + DMIBAR32(0x0924) = 0x7a1842ec; + tmp = DMIBAR32(0x092c); // !!! = 0x00000208 + DMIBAR32(0x092c) = 0x00000128; + tmp = DMIBAR32(0x0700); // !!! = 0x46139008 + DMIBAR32(0x0700) = 0x46139008; + tmp = DMIBAR32(0x0720); // !!! = 0x46139008 + DMIBAR32(0x0720) = 0x46139008; + tmp = DMIBAR32(0x0c04); // !!! = 0x2e680008 + DMIBAR32(0x0c04) = 0x2e680008; + tmp = DMIBAR32(0x0904); // !!! = 0x7a1842ec + DMIBAR32(0x0904) = 0x3a1842ec; + tmp = DMIBAR32(0x0924); // !!! = 0x7a1842ec + DMIBAR32(0x0924) = 0x3a1842ec; + tmp = DMIBAR32(0x0910); // !!! = 0x00006300 + DMIBAR32(0x0910) = 0x00004300; + tmp = DMIBAR32(0x0930); // !!! = 0x00006300 + DMIBAR32(0x0930) = 0x00004300; + tmp = DMIBAR32(0x0a00); // !!! = 0x03042010 + DMIBAR32(0x0a00) = 0x03042018; + tmp = DMIBAR32(0x0a10); // !!! = 0x03042010 + DMIBAR32(0x0a10) = 0x03042018; + tmp = DMIBAR32(0x0a20); // !!! = 0x03042010 + DMIBAR32(0x0a20) = 0x03042018; + tmp = DMIBAR32(0x0a30); // !!! = 0x03042010 + DMIBAR32(0x0a30) = 0x03042018; + tmp = DMIBAR32(0x0c00); // !!! = 0x29700c08 + DMIBAR32(0x0c00) = 0x29700c08; + tmp = DMIBAR32(0x0a04); // !!! = 0x0c0708f0 + DMIBAR32(0x0a04) = 0x0c0718f0; + tmp = DMIBAR32(0x0a14); // !!! = 0x0c0708f0 + DMIBAR32(0x0a14) = 0x0c0718f0; + tmp = DMIBAR32(0x0a24); // !!! = 0x0c0708f0 + DMIBAR32(0x0a24) = 0x0c0718f0; + tmp = DMIBAR32(0x0a34); // !!! = 0x0c0708f0 + DMIBAR32(0x0a34) = 0x0c0718f0; + tmp = DMIBAR32(0x0900); // !!! = 0x50000000 + DMIBAR32(0x0900) = 0x50000000; + tmp = DMIBAR32(0x0920); // !!! = 0x50000000 + DMIBAR32(0x0920) = 0x50000000; + tmp = DMIBAR32(0x0908); // !!! = 0x51ffffff + DMIBAR32(0x0908) = 0x51ffffff; + tmp = DMIBAR32(0x0928); // !!! = 0x51ffffff + DMIBAR32(0x0928) = 0x51ffffff; + tmp = DMIBAR32(0x0a00); // !!! = 0x03042018 + DMIBAR32(0x0a00) = 0x03042018; + tmp = DMIBAR32(0x0a10); // !!! = 0x03042018 + DMIBAR32(0x0a10) = 0x03042018; + tmp = DMIBAR32(0x0a20); // !!! = 0x03042018 + DMIBAR32(0x0a20) = 0x03042018; + tmp = DMIBAR32(0x0a30); // !!! = 0x03042018 + DMIBAR32(0x0a30) = 0x03042018; + tmp = DMIBAR32(0x0700); // !!! = 0x46139008 + DMIBAR32(0x0700) = 0x46139008; + tmp = DMIBAR32(0x0720); // !!! = 0x46139008 + DMIBAR32(0x0720) = 0x46139008; + tmp = DMIBAR32(0x0904); // !!! = 0x3a1842ec + DMIBAR32(0x0904) = 0x3a1846ec; + tmp = DMIBAR32(0x0924); // !!! = 0x3a1842ec + DMIBAR32(0x0924) = 0x3a1846ec; + tmp = DMIBAR32(0x0a00); // !!! = 0x03042018 + DMIBAR32(0x0a00) = 0x03042018; + tmp = DMIBAR32(0x0a10); // !!! = 0x03042018 + DMIBAR32(0x0a10) = 0x03042018; + tmp = DMIBAR32(0x0a20); // !!! = 0x03042018 + DMIBAR32(0x0a20) = 0x03042018; + tmp = DMIBAR32(0x0a30); // !!! = 0x03042018 + DMIBAR32(0x0a30) = 0x03042018; + tmp = DMIBAR32(0x0908); // !!! = 0x51ffffff + DMIBAR32(0x0908) = 0x51ffffff; + tmp = DMIBAR32(0x0928); // !!! = 0x51ffffff + DMIBAR32(0x0928) = 0x51ffffff; + tmp = DMIBAR32(0x0c00); // !!! = 0x29700c08 + DMIBAR32(0x0c00) = 0x29700c08; + tmp = DMIBAR32(0x0c0c); // !!! = 0x16063400 + DMIBAR32(0x0c0c) = 0x00063400; + tmp = DMIBAR32(0x0700); // !!! = 0x46139008 + DMIBAR32(0x0700) = 0x46339008; + tmp = DMIBAR32(0x0720); // !!! = 0x46139008 + DMIBAR32(0x0720) = 0x46339008; + tmp = DMIBAR32(0x0700); // !!! = 0x46339008 + DMIBAR32(0x0700) = 0x45339008; + tmp = DMIBAR32(0x0720); // !!! = 0x46339008 + DMIBAR32(0x0720) = 0x45339008; + tmp = DMIBAR32(0x0700); // !!! = 0x45339008 + DMIBAR32(0x0700) = 0x453b9008; + tmp = DMIBAR32(0x0720); // !!! = 0x45339008 + DMIBAR32(0x0720) = 0x453b9008; + tmp = DMIBAR32(0x0700); // !!! = 0x453b9008 + DMIBAR32(0x0700) = 0x45bb9008; + tmp = DMIBAR32(0x0720); // !!! = 0x453b9008 + DMIBAR32(0x0720) = 0x45bb9008; + tmp = DMIBAR32(0x0700); // !!! = 0x45bb9008 + DMIBAR32(0x0700) = 0x45fb9008; + tmp = DMIBAR32(0x0720); // !!! = 0x45bb9008 + DMIBAR32(0x0720) = 0x45fb9008; + tmp = DMIBAR32(0x0914); // !!! = 0x9021a080 + DMIBAR32(0x0914) = 0x9021a280; + tmp = DMIBAR32(0x0934); // !!! = 0x9021a080 + DMIBAR32(0x0934) = 0x9021a280; + tmp = DMIBAR32(0x0914); // !!! = 0x9021a280 + DMIBAR32(0x0914) = 0x9821a280; + tmp = DMIBAR32(0x0934); // !!! = 0x9021a280 + DMIBAR32(0x0934) = 0x9821a280; + tmp = DMIBAR32(0x0a00); // !!! = 0x03042018 + DMIBAR32(0x0a00) = 0x03242018; + tmp = DMIBAR32(0x0a10); // !!! = 0x03042018 + DMIBAR32(0x0a10) = 0x03242018; + tmp = DMIBAR32(0x0a20); // !!! = 0x03042018 + DMIBAR32(0x0a20) = 0x03242018; + tmp = DMIBAR32(0x0a30); // !!! = 0x03042018 + DMIBAR32(0x0a30) = 0x03242018; + tmp = DMIBAR32(0x0258); // !!! = 0x40000600 + DMIBAR32(0x0258) = 0x60000600; + tmp = DMIBAR32(0x0904); // !!! = 0x3a1846ec + DMIBAR32(0x0904) = 0x2a1846ec; + tmp = DMIBAR32(0x0914); // !!! = 0x9821a280 + DMIBAR32(0x0914) = 0x98200280; + tmp = DMIBAR32(0x0924); // !!! = 0x3a1846ec + DMIBAR32(0x0924) = 0x2a1846ec; + tmp = DMIBAR32(0x0934); // !!! = 0x9821a280 + DMIBAR32(0x0934) = 0x98200280; + tmp = DMIBAR32(0x022c); // !!! = 0x00c26460 + DMIBAR32(0x022c) = 0x00c2403c; + + early_pch_init_native_dmi_pre(); + + /* Write once settings. */ + DMIBAR32(DMILCAP) = (DMIBAR32(DMILCAP) & ~0x3f00f) | + (2 << 0) | // 5GT/s + (2 << 12) | // L0s 128 ns to less than 256 ns + (2 << 15); // L1 2 us to less than 4 us + + DMIBAR8(DMILCTL) |= 0x20; // Retrain link + while (DMIBAR16(DMILSTS) & TXTRN) + ; + + DMIBAR8(DMILCTL) |= 0x20; // Retrain link + while (DMIBAR16(DMILSTS) & TXTRN) + ; + + const u8 w = (DMIBAR16(DMILSTS) >> 4) & 0x1f; + const u16 t = (DMIBAR16(DMILSTS) & 0xf) * 2500; + + printk(BIOS_DEBUG, "DMI: Running at X%x @ %dMT/s\n", w, t); + /* + * Virtual Channel resources must match settings in RCBA! + * + * Channel Vp and Vm are documented in + * "Desktop 4th Generation Intel Core Processor Family, Desktop Intel + * Pentium Processor Family, and Desktop Intel Celeron Processor Family + * Vol. 2" + */ + + /* Channel 0: Enable, Set ID to 0, map TC0 and TC3 and TC4 to VC0. */ + DMIBAR32(DMIVC0RCTL) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1; + /* Channel 1: Enable, Set ID to 1, map TC1 and TC5 to VC1. */ + DMIBAR32(DMIVC1RCTL) = (1 << 31) | (1 << 24) | (0x11 << 1); + /* Channel p: Enable, Set ID to 2, map TC2 and TC6 to VCp */ + DMIBAR32(DMIVCPRCTL) = (1 << 31) | (2 << 24) | (0x22 << 1); + /* Channel m: Enable, Set ID to 0, map TC7 to VCm */ + DMIBAR32(DMIVCMRCTL) = (1 << 31) | (7 << 24) | (0x40 << 1); + + /* Set Extended VC Count (EVCC) to 1 as Channel 1 is active. */ + DMIBAR8(DMIPVCCAP1) |= 1; + + early_pch_init_native_dmi_post(); + + /* + * BIOS Requirement: Check if DMI VC Negotiation was successful. + * Wait for virtual channels negotiation pending. + */ + while (DMIBAR16(DMIVC0RSTS) & VC0NP) + ; + while (DMIBAR16(DMIVC1RSTS) & VC1NP) + ; + while (DMIBAR16(DMIVCPRSTS) & VCPNP) + ; + while (DMIBAR16(DMIVCMRSTS) & VCMNP) + ; +} diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 2ebeaf0..f67d61f 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -315,6 +315,7 @@ } early_pch_init_native(); + early_init_dmi(); early_thermal_init(); /* try to find timings in MRC cache */ diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 77f2ead..77165f6 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -220,6 +220,7 @@ void sandybridge_init_iommu(void); void sandybridge_late_initialization(void); void northbridge_romstage_finalize(int s3resume); +void early_init_dmi(void); #endif /* !__SMM__ */ diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 76f1447..e74c304 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -70,158 +70,8 @@ tmp = RCBA8(IOBPS); // call wait_iobp() instead here? } -static void -init_dmi (void) +void early_pch_init_native_dmi_pre(void) { - volatile u32 tmp; - int i; - - DMIBAR32(0x0914) |= 0x80000000; - DMIBAR32(0x0934) |= 0x80000000; - - for (i = 0; i < 4; i++) { - DMIBAR32(0x0a00 + (i << 4)) &= 0xf3ffffff; - DMIBAR32(0x0a04 + (i << 4)) |= 0x800; - } - DMIBAR32(0x0c30) = (DMIBAR32(0x0c30) & 0xfffffff) | 0x40000000; - - for (i = 0; i < 2; i++) { - DMIBAR32(0x0904 + (i << 5)) &= 0xfe3fffff; - DMIBAR32(0x090c + (i << 5)) &= 0xfff1ffff; - } - - DMIBAR32(0x090c) &= 0xfe1fffff; - DMIBAR32(0x092c) &= 0xfe1fffff; - - tmp = DMIBAR32(0x0904); // !!! = 0x7a1842ec - DMIBAR32(0x0904) = 0x7a1842ec; - tmp = DMIBAR32(0x090c); // !!! = 0x00000208 - DMIBAR32(0x090c) = 0x00000128; - tmp = DMIBAR32(0x0924); // !!! = 0x7a1842ec - DMIBAR32(0x0924) = 0x7a1842ec; - tmp = DMIBAR32(0x092c); // !!! = 0x00000208 - DMIBAR32(0x092c) = 0x00000128; - tmp = DMIBAR32(0x0700); // !!! = 0x46139008 - DMIBAR32(0x0700) = 0x46139008; - tmp = DMIBAR32(0x0720); // !!! = 0x46139008 - DMIBAR32(0x0720) = 0x46139008; - tmp = DMIBAR32(0x0c04); // !!! = 0x2e680008 - DMIBAR32(0x0c04) = 0x2e680008; - tmp = DMIBAR32(0x0904); // !!! = 0x7a1842ec - DMIBAR32(0x0904) = 0x3a1842ec; - tmp = DMIBAR32(0x0924); // !!! = 0x7a1842ec - DMIBAR32(0x0924) = 0x3a1842ec; - tmp = DMIBAR32(0x0910); // !!! = 0x00006300 - DMIBAR32(0x0910) = 0x00004300; - tmp = DMIBAR32(0x0930); // !!! = 0x00006300 - DMIBAR32(0x0930) = 0x00004300; - tmp = DMIBAR32(0x0a00); // !!! = 0x03042010 - DMIBAR32(0x0a00) = 0x03042018; - tmp = DMIBAR32(0x0a10); // !!! = 0x03042010 - DMIBAR32(0x0a10) = 0x03042018; - tmp = DMIBAR32(0x0a20); // !!! = 0x03042010 - DMIBAR32(0x0a20) = 0x03042018; - tmp = DMIBAR32(0x0a30); // !!! = 0x03042010 - DMIBAR32(0x0a30) = 0x03042018; - tmp = DMIBAR32(0x0c00); // !!! = 0x29700c08 - DMIBAR32(0x0c00) = 0x29700c08; - tmp = DMIBAR32(0x0a04); // !!! = 0x0c0708f0 - DMIBAR32(0x0a04) = 0x0c0718f0; - tmp = DMIBAR32(0x0a14); // !!! = 0x0c0708f0 - DMIBAR32(0x0a14) = 0x0c0718f0; - tmp = DMIBAR32(0x0a24); // !!! = 0x0c0708f0 - DMIBAR32(0x0a24) = 0x0c0718f0; - tmp = DMIBAR32(0x0a34); // !!! = 0x0c0708f0 - DMIBAR32(0x0a34) = 0x0c0718f0; - tmp = DMIBAR32(0x0900); // !!! = 0x50000000 - DMIBAR32(0x0900) = 0x50000000; - tmp = DMIBAR32(0x0920); // !!! = 0x50000000 - DMIBAR32(0x0920) = 0x50000000; - tmp = DMIBAR32(0x0908); // !!! = 0x51ffffff - DMIBAR32(0x0908) = 0x51ffffff; - tmp = DMIBAR32(0x0928); // !!! = 0x51ffffff - DMIBAR32(0x0928) = 0x51ffffff; - tmp = DMIBAR32(0x0a00); // !!! = 0x03042018 - DMIBAR32(0x0a00) = 0x03042018; - tmp = DMIBAR32(0x0a10); // !!! = 0x03042018 - DMIBAR32(0x0a10) = 0x03042018; - tmp = DMIBAR32(0x0a20); // !!! = 0x03042018 - DMIBAR32(0x0a20) = 0x03042018; - tmp = DMIBAR32(0x0a30); // !!! = 0x03042018 - DMIBAR32(0x0a30) = 0x03042018; - tmp = DMIBAR32(0x0700); // !!! = 0x46139008 - DMIBAR32(0x0700) = 0x46139008; - tmp = DMIBAR32(0x0720); // !!! = 0x46139008 - DMIBAR32(0x0720) = 0x46139008; - tmp = DMIBAR32(0x0904); // !!! = 0x3a1842ec - DMIBAR32(0x0904) = 0x3a1846ec; - tmp = DMIBAR32(0x0924); // !!! = 0x3a1842ec - DMIBAR32(0x0924) = 0x3a1846ec; - tmp = DMIBAR32(0x0a00); // !!! = 0x03042018 - DMIBAR32(0x0a00) = 0x03042018; - tmp = DMIBAR32(0x0a10); // !!! = 0x03042018 - DMIBAR32(0x0a10) = 0x03042018; - tmp = DMIBAR32(0x0a20); // !!! = 0x03042018 - DMIBAR32(0x0a20) = 0x03042018; - tmp = DMIBAR32(0x0a30); // !!! = 0x03042018 - DMIBAR32(0x0a30) = 0x03042018; - tmp = DMIBAR32(0x0908); // !!! = 0x51ffffff - DMIBAR32(0x0908) = 0x51ffffff; - tmp = DMIBAR32(0x0928); // !!! = 0x51ffffff - DMIBAR32(0x0928) = 0x51ffffff; - tmp = DMIBAR32(0x0c00); // !!! = 0x29700c08 - DMIBAR32(0x0c00) = 0x29700c08; - tmp = DMIBAR32(0x0c0c); // !!! = 0x16063400 - DMIBAR32(0x0c0c) = 0x00063400; - tmp = DMIBAR32(0x0700); // !!! = 0x46139008 - DMIBAR32(0x0700) = 0x46339008; - tmp = DMIBAR32(0x0720); // !!! = 0x46139008 - DMIBAR32(0x0720) = 0x46339008; - tmp = DMIBAR32(0x0700); // !!! = 0x46339008 - DMIBAR32(0x0700) = 0x45339008; - tmp = DMIBAR32(0x0720); // !!! = 0x46339008 - DMIBAR32(0x0720) = 0x45339008; - tmp = DMIBAR32(0x0700); // !!! = 0x45339008 - DMIBAR32(0x0700) = 0x453b9008; - tmp = DMIBAR32(0x0720); // !!! = 0x45339008 - DMIBAR32(0x0720) = 0x453b9008; - tmp = DMIBAR32(0x0700); // !!! = 0x453b9008 - DMIBAR32(0x0700) = 0x45bb9008; - tmp = DMIBAR32(0x0720); // !!! = 0x453b9008 - DMIBAR32(0x0720) = 0x45bb9008; - tmp = DMIBAR32(0x0700); // !!! = 0x45bb9008 - DMIBAR32(0x0700) = 0x45fb9008; - tmp = DMIBAR32(0x0720); // !!! = 0x45bb9008 - DMIBAR32(0x0720) = 0x45fb9008; - tmp = DMIBAR32(0x0914); // !!! = 0x9021a080 - DMIBAR32(0x0914) = 0x9021a280; - tmp = DMIBAR32(0x0934); // !!! = 0x9021a080 - DMIBAR32(0x0934) = 0x9021a280; - tmp = DMIBAR32(0x0914); // !!! = 0x9021a280 - DMIBAR32(0x0914) = 0x9821a280; - tmp = DMIBAR32(0x0934); // !!! = 0x9021a280 - DMIBAR32(0x0934) = 0x9821a280; - tmp = DMIBAR32(0x0a00); // !!! = 0x03042018 - DMIBAR32(0x0a00) = 0x03242018; - tmp = DMIBAR32(0x0a10); // !!! = 0x03042018 - DMIBAR32(0x0a10) = 0x03242018; - tmp = DMIBAR32(0x0a20); // !!! = 0x03042018 - DMIBAR32(0x0a20) = 0x03242018; - tmp = DMIBAR32(0x0a30); // !!! = 0x03042018 - DMIBAR32(0x0a30) = 0x03242018; - tmp = DMIBAR32(0x0258); // !!! = 0x40000600 - DMIBAR32(0x0258) = 0x60000600; - tmp = DMIBAR32(0x0904); // !!! = 0x3a1846ec - DMIBAR32(0x0904) = 0x2a1846ec; - tmp = DMIBAR32(0x0914); // !!! = 0x9821a280 - DMIBAR32(0x0914) = 0x98200280; - tmp = DMIBAR32(0x0924); // !!! = 0x3a1846ec - DMIBAR32(0x0924) = 0x2a1846ec; - tmp = DMIBAR32(0x0934); // !!! = 0x9821a280 - DMIBAR32(0x0934) = 0x98200280; - tmp = DMIBAR32(0x022c); // !!! = 0x00c26460 - DMIBAR32(0x022c) = 0x00c2403c; - /* Link Capabilities Register */ RCBA32(0x21a4) = (RCBA32(0x21a4) & ~0x3fc00) | (3 << 10) | // L0s and L1 entry supported @@ -230,45 +80,11 @@ RCBA32(0x2340) = (RCBA32(0x2340) & ~0xff0000) | (0x3a << 16); RCBA8(0x21b0) = (RCBA8(0x21b0) & ~0xf) | 2; +} - /* Write once settings. */ - DMIBAR32(DMILCAP) = (DMIBAR32(DMILCAP) & ~0x3f00f) | - (2 << 0) | // 5GT/s - (2 << 12) | // L0s 128 ns to less than 256 ns - (2 << 15); // L1 2 us to less than 4 us - - DMIBAR8(DMILCTL) |= 0x20; // Retrain link - while (DMIBAR16(DMILSTS) & TXTRN) - ; - - DMIBAR8(DMILCTL) |= 0x20; // Retrain link - while (DMIBAR16(DMILSTS) & TXTRN) - ; - - const u8 w = (DMIBAR16(DMILSTS) >> 4) & 0x1f; - const u16 t = (DMIBAR16(DMILSTS) & 0xf) * 2500; - - printk(BIOS_DEBUG, "DMI: Running at X%x @ %dMT/s\n", w, t); - /* - * Virtual Channel resources must match settings in RCBA! - * - * Channel Vp and Vm are documented in - * "Desktop 4th Generation Intel Core Processor Family, Desktop Intel - * Pentium Processor Family, and Desktop Intel Celeron Processor Family - * Vol. 2" - */ - - /* Channel 0: Enable, Set ID to 0, map TC0 and TC3 and TC4 to VC0. */ - DMIBAR32(DMIVC0RCTL) = (1 << 31) | (0 << 24) | (0x0c << 1) | 1; - /* Channel 1: Enable, Set ID to 1, map TC1 and TC5 to VC1. */ - DMIBAR32(DMIVC1RCTL) = (1 << 31) | (1 << 24) | (0x11 << 1); - /* Channel p: Enable, Set ID to 2, map TC2 and TC6 to VCp */ - DMIBAR32(DMIVCPRCTL) = (1 << 31) | (2 << 24) | (0x22 << 1); - /* Channel m: Enable, Set ID to 0, map TC7 to VCm */ - DMIBAR32(DMIVCMRCTL) = (1 << 31) | (7 << 24) | (0x40 << 1); - - /* Set Extended VC Count (EVCC) to 1 as Channel 1 is active. */ - DMIBAR8(DMIPVCCAP1) |= 1; +void early_pch_init_native_dmi_post(void) +{ + volatile u32 tmp; tmp = RCBA32(0x0050); // !!! = 0x01200654 RCBA32(0x0050) = 0x01200654; @@ -334,19 +150,6 @@ ; while (RCBA16(0x2046) & VCNEGPND) ; - - /* - * BIOS Requirement: Check if DMI VC Negotiation was successful. - * Wait for virtual channels negotiation pending. - */ - while (DMIBAR16(DMIVC0RSTS) & VC0NP) - ; - while (DMIBAR16(DMIVC1RSTS) & VC1NP) - ; - while (DMIBAR16(DMIVCPRSTS) & VCPNP) - ; - while (DMIBAR16(DMIVCMRSTS) & VCMNP) - ; } void @@ -433,8 +236,6 @@ write_iobp(0xec0007b2, 0x04514b5e); write_iobp(0xec00078c, 0x40000200); write_iobp(0xec000780, 0x02000020); - - init_dmi(); } static void pch_enable_bars(void) diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index fb8238a..faa6822 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -77,6 +77,8 @@ void mainboard_rcba_config(void); void early_pch_init_native(void); void early_pch_init(void); +void early_pch_init_native_dmi_pre(void); +void early_pch_init_native_dmi_post(void); struct southbridge_usb_port { -- To view, visit https://review.coreboot.org/c/coreboot/+/32073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0b47391f3309f9ab0c3a3a8d525f38f8cca73c0 Gerrit-Change-Number: 32073 Gerrit-PatchSet: 10 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: sb/intel/bd82x6x/early_pch: Make use of RCBA and DMIBAR marcros
by Patrick Georgi (Code Review) 16 May '19

16 May '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32072 ) Change subject: sb/intel/bd82x6x/early_pch: Make use of RCBA and DMIBAR marcros ...................................................................... sb/intel/bd82x6x/early_pch: Make use of RCBA and DMIBAR marcros Use RCBA and DMIBAR macros to get rid of DEFAULT_RCBA and DEFAULT_DMIBAR. Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to OS, no errors visible in dmesg. Change-Id: Ic9be2240ea10b17c8cc289007dccadbb9e3f69ab Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32072 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> --- M src/southbridge/intel/bd82x6x/early_pch.c 1 file changed, 164 insertions(+), 162 deletions(-) Approvals: build bot (Jenkins): Verified HAOUAS Elyes: Looks good to me, approved diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 76ca202..76f1447 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -20,6 +20,7 @@ #include <device/pci_def.h> #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/common/pmbase.h> +#include <southbridge/intel/common/rcba.h> #include <console/console.h> /* For DMI bar. */ @@ -32,41 +33,41 @@ static void wait_iobp(void) { - while (read8(DEFAULT_RCBA + IOBPS) & 1) + while (RCBA8(IOBPS) & 1) ; // implement timeout? } static u32 read_iobp(u32 address) { + volatile u32 tmp; u32 ret; - write32(DEFAULT_RCBA + IOBPIRI, address); - write16(DEFAULT_RCBA + IOBPS, (read16(DEFAULT_RCBA + IOBPS) - & 0x1ff) | 0x600); + RCBA32(IOBPIRI) = address; + RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x1ff) | 0x600; wait_iobp(); - ret = read32(DEFAULT_RCBA + IOBPD); + ret = RCBA32(IOBPD); wait_iobp(); - read8(DEFAULT_RCBA + IOBPS); // call wait_iobp() instead here? + tmp = RCBA8(IOBPS); // call wait_iobp() instead here? return ret; } static void write_iobp(u32 address, u32 val) { + volatile u32 tmp; /* this function was probably pch_iobp_update with the andvalue * being 0. So either the IOBP read can be removed or this function * and the pch_iobp_update function in ramstage could be merged */ read_iobp(address); - write16(DEFAULT_RCBA + IOBPS, (read16(DEFAULT_RCBA + IOBPS) - & 0x1ff) | 0x600); + RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x1ff) | 0x600; wait_iobp(); - write32(DEFAULT_RCBA + IOBPD, val); + RCBA32(IOBPD) = val; wait_iobp(); - write16(DEFAULT_RCBA + IOBPS, - (read16(DEFAULT_RCBA + IOBPS) & 0x1ff) | 0x600); - read8(DEFAULT_RCBA + IOBPS); // call wait_iobp() instead here? + RCBA16(IOBPS) = (RCBA16(IOBPS) & 0x1ff) | 0x600; + + tmp = RCBA8(IOBPS); // call wait_iobp() instead here? } static void @@ -92,134 +93,134 @@ DMIBAR32(0x090c) &= 0xfe1fffff; DMIBAR32(0x092c) &= 0xfe1fffff; - read32 (DEFAULT_DMIBAR + 0x0904); // !!! = 0x7a1842ec - write32 (DEFAULT_DMIBAR + 0x0904, 0x7a1842ec); - read32 (DEFAULT_DMIBAR + 0x090c); // !!! = 0x00000208 - write32 (DEFAULT_DMIBAR + 0x090c, 0x00000128); - read32 (DEFAULT_DMIBAR + 0x0924); // !!! = 0x7a1842ec - write32 (DEFAULT_DMIBAR + 0x0924, 0x7a1842ec); - read32 (DEFAULT_DMIBAR + 0x092c); // !!! = 0x00000208 - write32 (DEFAULT_DMIBAR + 0x092c, 0x00000128); - read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x46139008 - write32 (DEFAULT_DMIBAR + 0x0700, 0x46139008); - read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x46139008 - write32 (DEFAULT_DMIBAR + 0x0720, 0x46139008); - read32 (DEFAULT_DMIBAR + 0x0c04); // !!! = 0x2e680008 - write32 (DEFAULT_DMIBAR + 0x0c04, 0x2e680008); - read32 (DEFAULT_DMIBAR + 0x0904); // !!! = 0x7a1842ec - write32 (DEFAULT_DMIBAR + 0x0904, 0x3a1842ec); - read32 (DEFAULT_DMIBAR + 0x0924); // !!! = 0x7a1842ec - write32 (DEFAULT_DMIBAR + 0x0924, 0x3a1842ec); - read32 (DEFAULT_DMIBAR + 0x0910); // !!! = 0x00006300 - write32 (DEFAULT_DMIBAR + 0x0910, 0x00004300); - read32 (DEFAULT_DMIBAR + 0x0930); // !!! = 0x00006300 - write32 (DEFAULT_DMIBAR + 0x0930, 0x00004300); - read32 (DEFAULT_DMIBAR + 0x0a00); // !!! = 0x03042010 - write32 (DEFAULT_DMIBAR + 0x0a00, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0a10); // !!! = 0x03042010 - write32 (DEFAULT_DMIBAR + 0x0a10, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0a20); // !!! = 0x03042010 - write32 (DEFAULT_DMIBAR + 0x0a20, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0a30); // !!! = 0x03042010 - write32 (DEFAULT_DMIBAR + 0x0a30, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0c00); // !!! = 0x29700c08 - write32 (DEFAULT_DMIBAR + 0x0c00, 0x29700c08); - read32 (DEFAULT_DMIBAR + 0x0a04); // !!! = 0x0c0708f0 - write32 (DEFAULT_DMIBAR + 0x0a04, 0x0c0718f0); - read32 (DEFAULT_DMIBAR + 0x0a14); // !!! = 0x0c0708f0 - write32 (DEFAULT_DMIBAR + 0x0a14, 0x0c0718f0); - read32 (DEFAULT_DMIBAR + 0x0a24); // !!! = 0x0c0708f0 - write32 (DEFAULT_DMIBAR + 0x0a24, 0x0c0718f0); - read32 (DEFAULT_DMIBAR + 0x0a34); // !!! = 0x0c0708f0 - write32 (DEFAULT_DMIBAR + 0x0a34, 0x0c0718f0); - read32 (DEFAULT_DMIBAR + 0x0900); // !!! = 0x50000000 - write32 (DEFAULT_DMIBAR + 0x0900, 0x50000000); - read32 (DEFAULT_DMIBAR + 0x0920); // !!! = 0x50000000 - write32 (DEFAULT_DMIBAR + 0x0920, 0x50000000); - read32 (DEFAULT_DMIBAR + 0x0908); // !!! = 0x51ffffff - write32 (DEFAULT_DMIBAR + 0x0908, 0x51ffffff); - read32 (DEFAULT_DMIBAR + 0x0928); // !!! = 0x51ffffff - write32 (DEFAULT_DMIBAR + 0x0928, 0x51ffffff); - read32 (DEFAULT_DMIBAR + 0x0a00); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a00, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0a10); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a10, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0a20); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a20, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0a30); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a30, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x46139008 - write32 (DEFAULT_DMIBAR + 0x0700, 0x46139008); - read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x46139008 - write32 (DEFAULT_DMIBAR + 0x0720, 0x46139008); - read32 (DEFAULT_DMIBAR + 0x0904); // !!! = 0x3a1842ec - write32 (DEFAULT_DMIBAR + 0x0904, 0x3a1846ec); - read32 (DEFAULT_DMIBAR + 0x0924); // !!! = 0x3a1842ec - write32 (DEFAULT_DMIBAR + 0x0924, 0x3a1846ec); - read32 (DEFAULT_DMIBAR + 0x0a00); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a00, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0a10); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a10, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0a20); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a20, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0a30); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a30, 0x03042018); - read32 (DEFAULT_DMIBAR + 0x0908); // !!! = 0x51ffffff - write32 (DEFAULT_DMIBAR + 0x0908, 0x51ffffff); - read32 (DEFAULT_DMIBAR + 0x0928); // !!! = 0x51ffffff - write32 (DEFAULT_DMIBAR + 0x0928, 0x51ffffff); - read32 (DEFAULT_DMIBAR + 0x0c00); // !!! = 0x29700c08 - write32 (DEFAULT_DMIBAR + 0x0c00, 0x29700c08); - read32 (DEFAULT_DMIBAR + 0x0c0c); // !!! = 0x16063400 - write32 (DEFAULT_DMIBAR + 0x0c0c, 0x00063400); - read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x46139008 - write32 (DEFAULT_DMIBAR + 0x0700, 0x46339008); - read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x46139008 - write32 (DEFAULT_DMIBAR + 0x0720, 0x46339008); - read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x46339008 - write32 (DEFAULT_DMIBAR + 0x0700, 0x45339008); - read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x46339008 - write32 (DEFAULT_DMIBAR + 0x0720, 0x45339008); - read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x45339008 - write32 (DEFAULT_DMIBAR + 0x0700, 0x453b9008); - read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x45339008 - write32 (DEFAULT_DMIBAR + 0x0720, 0x453b9008); - read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x453b9008 - write32 (DEFAULT_DMIBAR + 0x0700, 0x45bb9008); - read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x453b9008 - write32 (DEFAULT_DMIBAR + 0x0720, 0x45bb9008); - read32 (DEFAULT_DMIBAR + 0x0700); // !!! = 0x45bb9008 - write32 (DEFAULT_DMIBAR + 0x0700, 0x45fb9008); - read32 (DEFAULT_DMIBAR + 0x0720); // !!! = 0x45bb9008 - write32 (DEFAULT_DMIBAR + 0x0720, 0x45fb9008); - read32 (DEFAULT_DMIBAR + 0x0914); // !!! = 0x9021a080 - write32 (DEFAULT_DMIBAR + 0x0914, 0x9021a280); - read32 (DEFAULT_DMIBAR + 0x0934); // !!! = 0x9021a080 - write32 (DEFAULT_DMIBAR + 0x0934, 0x9021a280); - read32 (DEFAULT_DMIBAR + 0x0914); // !!! = 0x9021a280 - write32 (DEFAULT_DMIBAR + 0x0914, 0x9821a280); - read32 (DEFAULT_DMIBAR + 0x0934); // !!! = 0x9021a280 - write32 (DEFAULT_DMIBAR + 0x0934, 0x9821a280); - read32 (DEFAULT_DMIBAR + 0x0a00); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a00, 0x03242018); - read32 (DEFAULT_DMIBAR + 0x0a10); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a10, 0x03242018); - read32 (DEFAULT_DMIBAR + 0x0a20); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a20, 0x03242018); - read32 (DEFAULT_DMIBAR + 0x0a30); // !!! = 0x03042018 - write32 (DEFAULT_DMIBAR + 0x0a30, 0x03242018); - read32 (DEFAULT_DMIBAR + 0x0258); // !!! = 0x40000600 - write32 (DEFAULT_DMIBAR + 0x0258, 0x60000600); - read32 (DEFAULT_DMIBAR + 0x0904); // !!! = 0x3a1846ec - write32 (DEFAULT_DMIBAR + 0x0904, 0x2a1846ec); - read32 (DEFAULT_DMIBAR + 0x0914); // !!! = 0x9821a280 - write32 (DEFAULT_DMIBAR + 0x0914, 0x98200280); - read32 (DEFAULT_DMIBAR + 0x0924); // !!! = 0x3a1846ec - write32 (DEFAULT_DMIBAR + 0x0924, 0x2a1846ec); - read32 (DEFAULT_DMIBAR + 0x0934); // !!! = 0x9821a280 - write32 (DEFAULT_DMIBAR + 0x0934, 0x98200280); - read32 (DEFAULT_DMIBAR + 0x022c); // !!! = 0x00c26460 - write32 (DEFAULT_DMIBAR + 0x022c, 0x00c2403c); + tmp = DMIBAR32(0x0904); // !!! = 0x7a1842ec + DMIBAR32(0x0904) = 0x7a1842ec; + tmp = DMIBAR32(0x090c); // !!! = 0x00000208 + DMIBAR32(0x090c) = 0x00000128; + tmp = DMIBAR32(0x0924); // !!! = 0x7a1842ec + DMIBAR32(0x0924) = 0x7a1842ec; + tmp = DMIBAR32(0x092c); // !!! = 0x00000208 + DMIBAR32(0x092c) = 0x00000128; + tmp = DMIBAR32(0x0700); // !!! = 0x46139008 + DMIBAR32(0x0700) = 0x46139008; + tmp = DMIBAR32(0x0720); // !!! = 0x46139008 + DMIBAR32(0x0720) = 0x46139008; + tmp = DMIBAR32(0x0c04); // !!! = 0x2e680008 + DMIBAR32(0x0c04) = 0x2e680008; + tmp = DMIBAR32(0x0904); // !!! = 0x7a1842ec + DMIBAR32(0x0904) = 0x3a1842ec; + tmp = DMIBAR32(0x0924); // !!! = 0x7a1842ec + DMIBAR32(0x0924) = 0x3a1842ec; + tmp = DMIBAR32(0x0910); // !!! = 0x00006300 + DMIBAR32(0x0910) = 0x00004300; + tmp = DMIBAR32(0x0930); // !!! = 0x00006300 + DMIBAR32(0x0930) = 0x00004300; + tmp = DMIBAR32(0x0a00); // !!! = 0x03042010 + DMIBAR32(0x0a00) = 0x03042018; + tmp = DMIBAR32(0x0a10); // !!! = 0x03042010 + DMIBAR32(0x0a10) = 0x03042018; + tmp = DMIBAR32(0x0a20); // !!! = 0x03042010 + DMIBAR32(0x0a20) = 0x03042018; + tmp = DMIBAR32(0x0a30); // !!! = 0x03042010 + DMIBAR32(0x0a30) = 0x03042018; + tmp = DMIBAR32(0x0c00); // !!! = 0x29700c08 + DMIBAR32(0x0c00) = 0x29700c08; + tmp = DMIBAR32(0x0a04); // !!! = 0x0c0708f0 + DMIBAR32(0x0a04) = 0x0c0718f0; + tmp = DMIBAR32(0x0a14); // !!! = 0x0c0708f0 + DMIBAR32(0x0a14) = 0x0c0718f0; + tmp = DMIBAR32(0x0a24); // !!! = 0x0c0708f0 + DMIBAR32(0x0a24) = 0x0c0718f0; + tmp = DMIBAR32(0x0a34); // !!! = 0x0c0708f0 + DMIBAR32(0x0a34) = 0x0c0718f0; + tmp = DMIBAR32(0x0900); // !!! = 0x50000000 + DMIBAR32(0x0900) = 0x50000000; + tmp = DMIBAR32(0x0920); // !!! = 0x50000000 + DMIBAR32(0x0920) = 0x50000000; + tmp = DMIBAR32(0x0908); // !!! = 0x51ffffff + DMIBAR32(0x0908) = 0x51ffffff; + tmp = DMIBAR32(0x0928); // !!! = 0x51ffffff + DMIBAR32(0x0928) = 0x51ffffff; + tmp = DMIBAR32(0x0a00); // !!! = 0x03042018 + DMIBAR32(0x0a00) = 0x03042018; + tmp = DMIBAR32(0x0a10); // !!! = 0x03042018 + DMIBAR32(0x0a10) = 0x03042018; + tmp = DMIBAR32(0x0a20); // !!! = 0x03042018 + DMIBAR32(0x0a20) = 0x03042018; + tmp = DMIBAR32(0x0a30); // !!! = 0x03042018 + DMIBAR32(0x0a30) = 0x03042018; + tmp = DMIBAR32(0x0700); // !!! = 0x46139008 + DMIBAR32(0x0700) = 0x46139008; + tmp = DMIBAR32(0x0720); // !!! = 0x46139008 + DMIBAR32(0x0720) = 0x46139008; + tmp = DMIBAR32(0x0904); // !!! = 0x3a1842ec + DMIBAR32(0x0904) = 0x3a1846ec; + tmp = DMIBAR32(0x0924); // !!! = 0x3a1842ec + DMIBAR32(0x0924) = 0x3a1846ec; + tmp = DMIBAR32(0x0a00); // !!! = 0x03042018 + DMIBAR32(0x0a00) = 0x03042018; + tmp = DMIBAR32(0x0a10); // !!! = 0x03042018 + DMIBAR32(0x0a10) = 0x03042018; + tmp = DMIBAR32(0x0a20); // !!! = 0x03042018 + DMIBAR32(0x0a20) = 0x03042018; + tmp = DMIBAR32(0x0a30); // !!! = 0x03042018 + DMIBAR32(0x0a30) = 0x03042018; + tmp = DMIBAR32(0x0908); // !!! = 0x51ffffff + DMIBAR32(0x0908) = 0x51ffffff; + tmp = DMIBAR32(0x0928); // !!! = 0x51ffffff + DMIBAR32(0x0928) = 0x51ffffff; + tmp = DMIBAR32(0x0c00); // !!! = 0x29700c08 + DMIBAR32(0x0c00) = 0x29700c08; + tmp = DMIBAR32(0x0c0c); // !!! = 0x16063400 + DMIBAR32(0x0c0c) = 0x00063400; + tmp = DMIBAR32(0x0700); // !!! = 0x46139008 + DMIBAR32(0x0700) = 0x46339008; + tmp = DMIBAR32(0x0720); // !!! = 0x46139008 + DMIBAR32(0x0720) = 0x46339008; + tmp = DMIBAR32(0x0700); // !!! = 0x46339008 + DMIBAR32(0x0700) = 0x45339008; + tmp = DMIBAR32(0x0720); // !!! = 0x46339008 + DMIBAR32(0x0720) = 0x45339008; + tmp = DMIBAR32(0x0700); // !!! = 0x45339008 + DMIBAR32(0x0700) = 0x453b9008; + tmp = DMIBAR32(0x0720); // !!! = 0x45339008 + DMIBAR32(0x0720) = 0x453b9008; + tmp = DMIBAR32(0x0700); // !!! = 0x453b9008 + DMIBAR32(0x0700) = 0x45bb9008; + tmp = DMIBAR32(0x0720); // !!! = 0x453b9008 + DMIBAR32(0x0720) = 0x45bb9008; + tmp = DMIBAR32(0x0700); // !!! = 0x45bb9008 + DMIBAR32(0x0700) = 0x45fb9008; + tmp = DMIBAR32(0x0720); // !!! = 0x45bb9008 + DMIBAR32(0x0720) = 0x45fb9008; + tmp = DMIBAR32(0x0914); // !!! = 0x9021a080 + DMIBAR32(0x0914) = 0x9021a280; + tmp = DMIBAR32(0x0934); // !!! = 0x9021a080 + DMIBAR32(0x0934) = 0x9021a280; + tmp = DMIBAR32(0x0914); // !!! = 0x9021a280 + DMIBAR32(0x0914) = 0x9821a280; + tmp = DMIBAR32(0x0934); // !!! = 0x9021a280 + DMIBAR32(0x0934) = 0x9821a280; + tmp = DMIBAR32(0x0a00); // !!! = 0x03042018 + DMIBAR32(0x0a00) = 0x03242018; + tmp = DMIBAR32(0x0a10); // !!! = 0x03042018 + DMIBAR32(0x0a10) = 0x03242018; + tmp = DMIBAR32(0x0a20); // !!! = 0x03042018 + DMIBAR32(0x0a20) = 0x03242018; + tmp = DMIBAR32(0x0a30); // !!! = 0x03042018 + DMIBAR32(0x0a30) = 0x03242018; + tmp = DMIBAR32(0x0258); // !!! = 0x40000600 + DMIBAR32(0x0258) = 0x60000600; + tmp = DMIBAR32(0x0904); // !!! = 0x3a1846ec + DMIBAR32(0x0904) = 0x2a1846ec; + tmp = DMIBAR32(0x0914); // !!! = 0x9821a280 + DMIBAR32(0x0914) = 0x98200280; + tmp = DMIBAR32(0x0924); // !!! = 0x3a1846ec + DMIBAR32(0x0924) = 0x2a1846ec; + tmp = DMIBAR32(0x0934); // !!! = 0x9821a280 + DMIBAR32(0x0934) = 0x98200280; + tmp = DMIBAR32(0x022c); // !!! = 0x00c26460 + DMIBAR32(0x022c) = 0x00c2403c; /* Link Capabilities Register */ RCBA32(0x21a4) = (RCBA32(0x21a4) & ~0x3fc00) | @@ -269,13 +270,13 @@ /* Set Extended VC Count (EVCC) to 1 as Channel 1 is active. */ DMIBAR8(DMIPVCCAP1) |= 1; - read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x01200654 - write32 (DEFAULT_RCBA + 0x0050, 0x01200654); - read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x01200654 - write32 (DEFAULT_RCBA + 0x0050, 0x012a0654); - read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x012a0654 - read8 (DEFAULT_RCBA + 0x1114); // !!! = 0x00 - write8 (DEFAULT_RCBA + 0x1114, 0x05); + tmp = RCBA32(0x0050); // !!! = 0x01200654 + RCBA32(0x0050) = 0x01200654; + tmp = RCBA32(0x0050); // !!! = 0x01200654 + RCBA32(0x0050) = 0x012a0654; + tmp = RCBA32(0x0050); // !!! = 0x012a0654 + tmp = RCBA8(0x1114); // !!! = 0x00 + RCBA8(0x1114) = 0x05; /* * Virtual Channel resources must match settings in DMIBAR! @@ -351,24 +352,25 @@ void early_pch_init_native (void) { + volatile u32 tmp; pci_write_config8 (SOUTHBRIDGE, 0xa6, pci_read_config8 (SOUTHBRIDGE, 0xa6) | 2); - write32 (DEFAULT_RCBA + 0x2088, 0x00109000); - read32 (DEFAULT_RCBA + 0x20ac); // !!! = 0x00000000 - write32 (DEFAULT_RCBA + 0x20ac, 0x40000000); - write32 (DEFAULT_RCBA + 0x100c, 0x01110000); - write8 (DEFAULT_RCBA + 0x2340, 0x1b); - read32 (DEFAULT_RCBA + 0x2314); // !!! = 0x0a080000 - write32 (DEFAULT_RCBA + 0x2314, 0x0a280000); - read32 (DEFAULT_RCBA + 0x2310); // !!! = 0xc809605b - write32 (DEFAULT_RCBA + 0x2310, 0xa809605b); - write32 (DEFAULT_RCBA + 0x2324, 0x00854c74); - read8 (DEFAULT_RCBA + 0x0400); // !!! = 0x00 - read32 (DEFAULT_RCBA + 0x2310); // !!! = 0xa809605b - write32 (DEFAULT_RCBA + 0x2310, 0xa809605b); - read32 (DEFAULT_RCBA + 0x2310); // !!! = 0xa809605b - write32 (DEFAULT_RCBA + 0x2310, 0xa809605b); + RCBA32(0x2088) = 0x00109000; + tmp = RCBA32(0x20ac); // !!! = 0x00000000 + RCBA32(0x20ac) = 0x40000000; + RCBA32(0x100c) = 0x01110000; + RCBA8(0x2340) = 0x1b; + tmp = RCBA32(0x2314); // !!! = 0x0a080000 + RCBA32(0x2314) = 0x0a280000; + tmp = RCBA32(0x2310); // !!! = 0xc809605b + RCBA32(0x2310) = 0xa809605b; + RCBA32(0x2324) = 0x00854c74; + tmp = RCBA8(0x0400); // !!! = 0x00 + tmp = RCBA32(0x2310); // !!! = 0xa809605b + RCBA32(0x2310) = 0xa809605b; + tmp = RCBA32(0x2310); // !!! = 0xa809605b + RCBA32(0x2310) = 0xa809605b; write_iobp(0xea007f62, 0x00590133); write_iobp(0xec007f62, 0x00590133); -- To view, visit https://review.coreboot.org/c/coreboot/+/32072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9be2240ea10b17c8cc289007dccadbb9e3f69ab Gerrit-Change-Number: 32072 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: sb/intel/sandybridge/early_pch: Make DMI init more readable
by Patrick Rudolph (Code Review) 16 May '19

16 May '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32071 Change subject: sb/intel/sandybridge/early_pch: Make DMI init more readable ...................................................................... sb/intel/sandybridge/early_pch: Make DMI init more readable Add a few comments and use known register values. Untested. Change-Id: I404515b77a22324f55581f117d79630be4ba64dd Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/sandybridge.h M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/bd82x6x/pch.h 3 files changed, 123 insertions(+), 71 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/32071/1 diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 72b2805..2b12521 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -175,12 +175,23 @@ #define DMIPVCCCTL 0x00c /* 16bit */ #define DMIVC0RCAP 0x010 /* 32bit */ -#define DMIVC0RCTL0 0x014 /* 32bit */ +#define DMIVC0RCTL 0x014 /* 32bit */ #define DMIVC0RSTS 0x01a /* 16bit */ +#define VC0NP 0x2 #define DMIVC1RCAP 0x01c /* 32bit */ #define DMIVC1RCTL 0x020 /* 32bit */ #define DMIVC1RSTS 0x026 /* 16bit */ +#define VC1NP 0x2 + +#define DMIVCPRCTL 0x02c /* 16bit */ + +#define DMIVCPRSTS 0x032 /* 16bit */ +#define VCPNP 0x2 + +#define DMIVCMRCTL 0x0038 /* 32 bit */ +#define DMIVCMRSTS 0x003e /* 16 bit */ +#define VCMNP 0x2 #define DMILE1D 0x050 /* 32bit */ #define DMILE1A 0x058 /* 64bit */ @@ -190,7 +201,7 @@ #define DMILCAP 0x084 /* 32bit */ #define DMILCTL 0x088 /* 16bit */ #define DMILSTS 0x08a /* 16bit */ - +#define TXTRN (1 << 11) #define DMICTL1 0x0f0 /* 32bit */ #define DMICTL2 0x0fc /* 32bit */ diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 1bcb2ac..e4462c1 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -39,6 +39,7 @@ static u32 read_iobp(u32 address) { + volatile u32 tmp; u32 ret; write32(DEFAULT_RCBA + IOBPIRI, address); @@ -54,6 +55,8 @@ static void write_iobp(u32 address, u32 val) { + volatile u32 tmp; + /* this function was probably pch_iobp_update with the andvalue * being 0. So either the IOBP read can be removed or this function * and the pch_iobp_update function in ramstage could be merged */ @@ -69,36 +72,28 @@ read8(DEFAULT_RCBA + IOBPS); // call wait_iobp() instead here? } - static void init_dmi (void) { int i; - write32 (DEFAULT_DMIBAR + 0x0914, - read32 (DEFAULT_DMIBAR + 0x0914) | 0x80000000); - write32 (DEFAULT_DMIBAR + 0x0934, - read32 (DEFAULT_DMIBAR + 0x0934) | 0x80000000); - for (i = 0; i < 4; i++) - { - write32 (DEFAULT_DMIBAR + 0x0a00 + (i << 4), - read32 (DEFAULT_DMIBAR + 0x0a00 + (i << 4)) & 0xf3ffffff); - write32 (DEFAULT_DMIBAR + 0x0a04 + (i << 4), - read32 (DEFAULT_DMIBAR + 0x0a04 + (i << 4)) | 0x800); + DMIBAR32(0x0914) |= 0x80000000; + DMIBAR32(0x0934) |= 0x80000000; + + for (i = 0; i < 4; i++) { + DMIBAR32(0x0a00 + (i << 4)) &= 0xf3ffffff; + DMIBAR32(0x0a04 + (i << 4)) |= 0x800; } - write32 (DEFAULT_DMIBAR + 0x0c30, (read32 (DEFAULT_DMIBAR + 0x0c30) - & 0xfffffff) | 0x40000000); - for (i = 0; i < 2; i++) - { - write32 (DEFAULT_DMIBAR + 0x0904 + (i << 5), - read32 (DEFAULT_DMIBAR + 0x0904 + (i << 5)) & 0xfe3fffff); - write32 (DEFAULT_DMIBAR + 0x090c + (i << 5), - read32 (DEFAULT_DMIBAR + 0x090c + (i << 5)) & 0xfff1ffff); + DMIBAR32(0x0c30) = (DMIBAR32(0x0c30) & 0xfffffff) | 0x40000000; + + for (i = 0; i < 2; i++) { + DMIBAR32(0x0904 + (i << 5)) &= 0xfe3fffff; + DMIBAR32(0x090c + (i << 5)) &= 0xfff1ffff; } - write32 (DEFAULT_DMIBAR + 0x090c, - read32 (DEFAULT_DMIBAR + 0x090c) & 0xfe1fffff); - write32 (DEFAULT_DMIBAR + 0x092c, - read32 (DEFAULT_DMIBAR + 0x092c) & 0xfe1fffff); + + DMIBAR32(0x090c) &= 0xfe1fffff; + DMIBAR32(0x092c) &= 0xfe1fffff; + read32 (DEFAULT_DMIBAR + 0x0904); // !!! = 0x7a1842ec write32 (DEFAULT_DMIBAR + 0x0904, 0x7a1842ec); read32 (DEFAULT_DMIBAR + 0x090c); // !!! = 0x00000208 @@ -227,33 +222,45 @@ write32 (DEFAULT_DMIBAR + 0x0934, 0x98200280); read32 (DEFAULT_DMIBAR + 0x022c); // !!! = 0x00c26460 write32 (DEFAULT_DMIBAR + 0x022c, 0x00c2403c); - read8 (DEFAULT_RCBA + 0x21a4); // !!! = 0x42 - read32 (DEFAULT_RCBA + 0x21a4); // !!! = 0x00012c42 - read32 (DEFAULT_RCBA + 0x2340); // !!! = 0x0013001b - write32 (DEFAULT_RCBA + 0x2340, 0x003a001b); - read8 (DEFAULT_RCBA + 0x21b0); // !!! = 0x01 - write8 (DEFAULT_RCBA + 0x21b0, 0x02); - read32 (DEFAULT_DMIBAR + 0x0084); // !!! = 0x0041ac41 - write32 (DEFAULT_DMIBAR + 0x0084, 0x0041ac42); - read8 (DEFAULT_DMIBAR + 0x0088); // !!! = 0x00 - write8 (DEFAULT_DMIBAR + 0x0088, 0x20); - read16 (DEFAULT_DMIBAR + 0x008a); // !!! = 0x0041 - read8 (DEFAULT_DMIBAR + 0x0088); // !!! = 0x00 - write8 (DEFAULT_DMIBAR + 0x0088, 0x20); - read16 (DEFAULT_DMIBAR + 0x008a); // !!! = 0x0042 - read16 (DEFAULT_DMIBAR + 0x008a); // !!! = 0x0042 + /* Link Capabilities Register */ + RCBA32(0x21a4) |= (3 << 10) | // L0s and L1 entry supported + (2 << 12) | // L0s 128 ns to less than 256 ns + (1 << 15); // 1 us to less than 2 us - read32 (DEFAULT_DMIBAR + 0x0014); // !!! = 0x8000007f - write32 (DEFAULT_DMIBAR + 0x0014, 0x80000019); - read32 (DEFAULT_DMIBAR + 0x0020); // !!! = 0x01000000 - write32 (DEFAULT_DMIBAR + 0x0020, 0x81000022); - read32 (DEFAULT_DMIBAR + 0x002c); // !!! = 0x02000000 - write32 (DEFAULT_DMIBAR + 0x002c, 0x82000044); - read32 (DEFAULT_DMIBAR + 0x0038); // !!! = 0x07000080 - write32 (DEFAULT_DMIBAR + 0x0038, 0x87000080); - read8 (DEFAULT_DMIBAR + 0x0004); // !!! = 0x00 - write8 (DEFAULT_DMIBAR + 0x0004, 0x01); + RCBA8(0x2340) = (RCBA8(0x2340) & ~0xff0000) | (0x3a << 16); + RCBA8(0x21b0) = (RCBA8(0x21b0) & ~3) | 2; + + /* Write once settings. */ + DMIBAR16(DMILCAP) = (DMIBAR16(DMILCAP) & ~0x3f00f) | + (0x2 << 0) | // 5GT/s + (0x2 << 12) | // L0s 128 ns to less than 256 ns + (0x3 << 15); // L1 4 us to less than 8 us + + DMIBAR8(DMILCTL) |= 0x20; // Retrain link + while (DMIBAR16(DMILSTS) & TXTRN) + ; + + DMIBAR8(DMILCTL) |= 0x20; // Retrain link + while (DMIBAR16(DMILSTS) & TXTRN) + ; + + const u8 w = (DMIBAR16(DMILSTS) >> 4) & 0x1f; + const u16 t = (DMIBAR16(DMILSTS) & 0xf) * 2500; + + printk(BIOS_DEBUG, "DMI: Running at X%x @ %dMT/s\n", w, t); + + /* Set traffic class */ + DMIBAR32(DMIVC0RCTL) = (DMIBAR32(DMIVC0RCTL) & ~0x7e) | 0x18; + /* Enable channel 1 and set traffic class */ + DMIBAR32(DMIVC1RCTL) = (DMIBAR32(DMIVC1RCTL) & ~0x7e) | 0x80000022; + /* Enable channel private and set traffic class */ + DMIBAR32(DMIVCPRCTL) = (DMIBAR32(DMIVCPRCTL) & ~0x7e) | 0x80000044; + /* Enable channel m */ + DMIBAR32(DMIVCMRCTL) = DMIBAR32(DMIVCMRCTL) | 0x80000000; + + /* Set Extended VC Count (EVCC) to 1 */ + DMIBAR8(DMIPVCCAP1) |= 1; read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x01200654 write32 (DEFAULT_RCBA + 0x0050, 0x01200654); @@ -262,32 +269,64 @@ read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x012a0654 read8 (DEFAULT_RCBA + 0x1114); // !!! = 0x00 write8 (DEFAULT_RCBA + 0x1114, 0x05); - read32 (DEFAULT_RCBA + 0x2014); // !!! = 0x80000011 - write32 (DEFAULT_RCBA + 0x2014, 0x80000019); - read32 (DEFAULT_RCBA + 0x2020); // !!! = 0x00000000 - write32 (DEFAULT_RCBA + 0x2020, 0x81000022); - read32 (DEFAULT_RCBA + 0x2020); // !!! = 0x81000022 - read32 (DEFAULT_RCBA + 0x2030); // !!! = 0x00000000 - write32 (DEFAULT_RCBA + 0x2030, 0x82000044); - read32 (DEFAULT_RCBA + 0x2030); // !!! = 0x82000044 - read32 (DEFAULT_RCBA + 0x2040); // !!! = 0x00000000 - write32 (DEFAULT_RCBA + 0x2040, 0x87000080); - read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x012a0654 - write32 (DEFAULT_RCBA + 0x0050, 0x812a0654); - read32 (DEFAULT_RCBA + 0x0050); // !!! = 0x812a0654 - read16 (DEFAULT_RCBA + 0x201a); // !!! = 0x0000 - read16 (DEFAULT_RCBA + 0x2026); // !!! = 0x0000 - read16 (DEFAULT_RCBA + 0x2036); // !!! = 0x0000 - read16 (DEFAULT_RCBA + 0x2046); // !!! = 0x0000 - read16 (DEFAULT_DMIBAR + 0x001a); // !!! = 0x0000 - read16 (DEFAULT_DMIBAR + 0x0026); // !!! = 0x0000 - read16 (DEFAULT_DMIBAR + 0x0032); // !!! = 0x0000 - read16 (DEFAULT_DMIBAR + 0x003e); // !!! = 0x0000 + + /* Virtual Channel 0 Resource Control Register. Set Transaction class */ + RCBA32(0x2014) |= 8; + + /* Virtual Channel 1 Resource Control Register. + * Enable channel. + * Set Virtual Channel Identifier. + * Set Transaction class. + */ + RCBA32(0x2020) = 0x81000022; + + /* Virtual Channel private Resource Control Register. + * Enable channel. + * Set Virtual Channel Identifier. + * Set Transaction class. + */ + RCBA32(0x2030) = 0x82000044; + + /* Virtual Channel extendend Resource Control Register. + * Enable channel. + * Set Virtual Channel Identifier. + * Set Transaction class. + */ + RCBA32(0x2040) = 0x87000080; + + /* Lock Virtual Channel Resource control register. */ + RCBA32(0x0050) |= 0x80000000; + + /* Virtual Channel 0 Resource Status Register */ + if (RCBA16(0x201a) & VCNEGPND) + printk(BIOS_ERR, "ERR: Virtual Channel 0, Negotiation" + "with ingress port is pending\n"); + /* Virtual Channel 1 Resource Status Register */ + if (RCBA16(0x2026) & VCNEGPND) + printk(BIOS_ERR, "ERR: Virtual Channel 1, Negotiation" + "with ingress port is pending\n"); + if (RCBA16(0x2036) & VCNEGPND) + printk(BIOS_ERR, "ERR: Virtual Channel private, Negotiation" + "with ingress port is pending\n"); + if (RCBA16(0x2046) & VCNEGPND) + printk(BIOS_ERR, "ERR: Virtual Channel m, Negotiation" + "with ingress port is pending\n"); + + /* BIOS Requirement: Check if DMI VC Negotiation was successful. */ + if (DMIBAR16(DMIVC0RSTS) & VC0NP) + printk(BIOS_ERR, "ERR: Virtual Channel 0, Negotiation Pending\n"); + if (DMIBAR16(DMIVC1RSTS) & VC1NP) + printk(BIOS_ERR, "ERR: Virtual Channel 1, Negotiation Pending\n"); + if (DMIBAR16(DMIVCPRSTS) & VCPNP) + printk(BIOS_ERR, "ERR: Virtual Channel private, Negotiation Pending\n"); + if (DMIBAR16(DMIVCMRSTS) & VCMNP) + printk(BIOS_ERR, "ERR: Virtual Channel m, Negotiation Pending\n"); } void early_pch_init_native (void) { + volatile u32 tmp; pci_write_config8 (SOUTHBRIDGE, 0xa6, pci_read_config8 (SOUTHBRIDGE, 0xa6) | 2); diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 21b6031..f3ad469 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -310,6 +310,8 @@ #define IOTR2 0x1e90 /* 64bit */ #define IOTR3 0x1e98 /* 64bit */ +#define VCNEGPND 2 + #define TCTL 0x3000 /* 8bit */ #define NOINT 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/32071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I404515b77a22324f55581f117d79630be4ba64dd Gerrit-Change-Number: 32071 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 8

Change in ...coreboot[master]: sb/amd/cimx/sb800: Get rid of power button device in coreboot
by Paul Menzel (Code Review) 16 May '19

16 May '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27496 ) Change subject: sb/amd/cimx/sb800: Get rid of power button device in coreboot ...................................................................... Patch Set 5: Could somebody please update the commit message so that it is acceptable? -- To view, visit https://review.coreboot.org/c/coreboot/+/27496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cbecb72f7e1bf3d051d3b7656c6af4d6f43b497 Gerrit-Change-Number: 27496 Gerrit-PatchSet: 5 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 16 May 2019 20:22:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: nb/intel/sandybridge: Move DMI init code
by Patrick Georgi (Code Review) 16 May '19

16 May '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32073 ) Change subject: nb/intel/sandybridge: Move DMI init code ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/32073 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib0b47391f3309f9ab0c3a3a8d525f38f8cca73c0 Gerrit-Change-Number: 32073 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 16 May 2019 20:21:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: [WIP] mb/gigabyte/ga-b75m-d3{h,v}: Various cleanups
by Alex James (Code Review) 16 May '19

16 May '19

Alex James has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32752 Change subject: [WIP] mb/gigabyte/ga-b75m-d3{h,v}: Various cleanups ...................................................................... [WIP] mb/gigabyte/ga-b75m-d3{h,v}: Various cleanups - Unconditionally enable LPC TPM support - Remove unused Super I/O ACPI definitions - Remove duplicate chipset register initialization from mainboard_init and move mainboard.c to the common baseboard tree - Move ITE Super I/O configuration to mainboard_config_superio TODO: - Add extracted VBTs from vendor firmware and set INTEL_GMA_HAVE_VBT - Fix mainboard_get_spd - should probably only read spd[0, 2] Signed-off-by: Alex James <theracermaster(a)gmail.com> Change-Id: I2d11c55dc809b920bccf55f5f745d9f29b18bbb6 --- M src/mainboard/gigabyte/ga-panther-point/Kconfig M src/mainboard/gigabyte/ga-panther-point/Makefile.inc M src/mainboard/gigabyte/ga-panther-point/acpi/superio.asl A src/mainboard/gigabyte/ga-panther-point/mainboard.c M src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/devicetree.cb D src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/mainboard.c M src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/romstage.c M src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/devicetree.cb D src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/mainboard.c M src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/romstage.c 10 files changed, 80 insertions(+), 201 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/32752/1 diff --git a/src/mainboard/gigabyte/ga-panther-point/Kconfig b/src/mainboard/gigabyte/ga-panther-point/Kconfig index ce7e195..4533c55 100644 --- a/src/mainboard/gigabyte/ga-panther-point/Kconfig +++ b/src/mainboard/gigabyte/ga-panther-point/Kconfig @@ -26,7 +26,7 @@ select INTEL_INT15 select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_LIBGFXINIT - select MAINBOARD_HAS_LPC_TPM if BOARD_GIGABYTE_GA_B75M_D3H + select MAINBOARD_HAS_LPC_TPM if BOARD_GIGABYTE_BASEBOARD_GA_PANTHER_POINT diff --git a/src/mainboard/gigabyte/ga-panther-point/Makefile.inc b/src/mainboard/gigabyte/ga-panther-point/Makefile.inc index feb9532..08a9957 100644 --- a/src/mainboard/gigabyte/ga-panther-point/Makefile.inc +++ b/src/mainboard/gigabyte/ga-panther-point/Makefile.inc @@ -16,7 +16,6 @@ romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c -ramstage-y += variants/$(VARIANT_DIR)/mainboard.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/gigabyte/ga-panther-point/acpi/superio.asl b/src/mainboard/gigabyte/ga-panther-point/acpi/superio.asl index 78bf687..e69de29 100644 --- a/src/mainboard/gigabyte/ga-panther-point/acpi/superio.asl +++ b/src/mainboard/gigabyte/ga-panther-point/acpi/superio.asl @@ -1,19 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* mainboard configuration */ - -#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard -#define SIO_ENABLE_PS2M // Enable PS/2 Mouse diff --git a/src/mainboard/gigabyte/ga-panther-point/mainboard.c b/src/mainboard/gigabyte/ga-panther-point/mainboard.c new file mode 100644 index 0000000..d2da2c6 --- /dev/null +++ b/src/mainboard/gigabyte/ga-panther-point/mainboard.c @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011-2012 Google Inc. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <drivers/intel/gma/int15.h> +#include <southbridge/intel/bd82x6x/pch.h> + +static void mainboard_init(struct device *dev) +{ +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = mainboard_init; + + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, + GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/devicetree.cb index 7a3568a..15454a5 100644 --- a/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/devicetree.cb @@ -21,11 +21,11 @@ device domain 0 on subsystemid 0x1458 0x5000 inherit - device pci 00.0 on # host bridge + device pci 00.0 on # Host bridge subsystemid 0x1458 0x5000 end device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on # vga controller + device pci 02.0 on # Integrated VGA controller subsystemid 0x1458 0xd000 end @@ -109,7 +109,7 @@ end chip drivers/pc80/tpm - device pnp 0c31.0 on end + device pnp 0c31.0 on end end end device pci 1f.2 on # SATA Controller 1 diff --git a/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/mainboard.c b/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/mainboard.c deleted file mode 100644 index 4e8d9f5..0000000 --- a/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/mainboard.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011-2012 Google Inc. - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <drivers/intel/gma/int15.h> -#include <southbridge/intel/bd82x6x/pch.h> - -static void mainboard_init(struct device *dev) -{ - RCBA32(0x38c8) = 0x00002005; - RCBA32(0x38c4) = 0x00802005; - RCBA32(0x2240) = 0x00330e71; - RCBA32(0x2244) = 0x003f0eb1; - RCBA32(0x2248) = 0x002102cd; - RCBA32(0x224c) = 0x00f60000; - RCBA32(0x2250) = 0x00020000; - RCBA32(0x2254) = 0x00e3004c; - RCBA32(0x2258) = 0x00e20bef; - RCBA32(0x2260) = 0x003304ed; - RCBA32(0x2278) = 0x001107c1; - RCBA32(0x227c) = 0x001d07e9; - RCBA32(0x2280) = 0x00e20000; - RCBA32(0x2284) = 0x00ee0000; - RCBA32(0x2288) = 0x005b05d3; - RCBA32(0x2318) = 0x04b8ff2e; - RCBA32(0x231c) = 0x03930f2e; - RCBA32(0x3808) = 0x005044a3; - RCBA32(0x3810) = 0x52410000; - RCBA32(0x3814) = 0x0000008a; - RCBA32(0x3818) = 0x00000006; - RCBA32(0x381c) = 0x0000072e; - RCBA32(0x3820) = 0x0000000a; - RCBA32(0x3824) = 0x00000123; - RCBA32(0x3828) = 0x00000009; - RCBA32(0x382c) = 0x00000001; - RCBA32(0x3834) = 0x0000061a; - RCBA32(0x3838) = 0x00000003; - RCBA32(0x383c) = 0x00000a76; - RCBA32(0x3840) = 0x00000004; - RCBA32(0x3844) = 0x0000e5e4; - RCBA32(0x3848) = 0x0000000e; -} - -// mainboard_enable is executed as first thing after -// enumerate_buses(). - -static void mainboard_enable(struct device *dev) -{ - dev->ops->init = mainboard_init; - - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, - GMA_INT15_PANEL_FIT_DEFAULT, - GMA_INT15_BOOT_DISPLAY_CRT, 0); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/romstage.c index aa5f484..eb88d36 100644 --- a/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/romstage.c +++ b/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3h/romstage.c @@ -25,12 +25,6 @@ #define SIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO) #define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01) -void mainboard_rcba_config(void) -{ - /* Enable HECI */ - RCBA32(FD2) &= ~0x2; -} - void pch_enable_lpc(void) { pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | @@ -40,7 +34,10 @@ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); +} +void mainboard_config_superio(void) +{ /* Initialize SuperIO */ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); @@ -87,18 +84,21 @@ { 1, 5, 6 }, }; -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd (&spd[0], 0x50, id_only); - read_spd (&spd[1], 0x51, id_only); - read_spd (&spd[2], 0x52, id_only); - read_spd (&spd[3], 0x53, id_only); -} - void mainboard_early_init(int s3resume) { } -void mainboard_config_superio(void) +/* FIXME: This board only has two DIMM slots! */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) { + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} + +void mainboard_rcba_config(void) +{ + /* Enable HECI */ + RCBA32(FD2) &= ~0x2; } diff --git a/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/devicetree.cb b/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/devicetree.cb index a00e2ee..15454a5 100644 --- a/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/devicetree.cb +++ b/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/devicetree.cb @@ -1,4 +1,5 @@ chip northbridge/intel/sandybridge + # IGD Displays register "gfx.ndid" = "3" register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" @@ -20,11 +21,11 @@ device domain 0 on subsystemid 0x1458 0x5000 inherit - device pci 00.0 on # host bridge + device pci 00.0 on # Host bridge subsystemid 0x1458 0x5000 end device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on # vga controller + device pci 02.0 on # Integrated VGA controller subsystemid 0x1458 0xd000 end @@ -106,6 +107,10 @@ device pnp 2e.7 off end # GPIO device pnp 2e.a off end # IR end + + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end end device pci 1f.2 on # SATA Controller 1 subsystemid 0x1458 0xb005 diff --git a/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/mainboard.c b/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/mainboard.c deleted file mode 100644 index 4e8d9f5..0000000 --- a/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/mainboard.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2011-2012 Google Inc. - * Copyright (C) 2014 Vladimir Serbinenko - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <device/device.h> -#include <drivers/intel/gma/int15.h> -#include <southbridge/intel/bd82x6x/pch.h> - -static void mainboard_init(struct device *dev) -{ - RCBA32(0x38c8) = 0x00002005; - RCBA32(0x38c4) = 0x00802005; - RCBA32(0x2240) = 0x00330e71; - RCBA32(0x2244) = 0x003f0eb1; - RCBA32(0x2248) = 0x002102cd; - RCBA32(0x224c) = 0x00f60000; - RCBA32(0x2250) = 0x00020000; - RCBA32(0x2254) = 0x00e3004c; - RCBA32(0x2258) = 0x00e20bef; - RCBA32(0x2260) = 0x003304ed; - RCBA32(0x2278) = 0x001107c1; - RCBA32(0x227c) = 0x001d07e9; - RCBA32(0x2280) = 0x00e20000; - RCBA32(0x2284) = 0x00ee0000; - RCBA32(0x2288) = 0x005b05d3; - RCBA32(0x2318) = 0x04b8ff2e; - RCBA32(0x231c) = 0x03930f2e; - RCBA32(0x3808) = 0x005044a3; - RCBA32(0x3810) = 0x52410000; - RCBA32(0x3814) = 0x0000008a; - RCBA32(0x3818) = 0x00000006; - RCBA32(0x381c) = 0x0000072e; - RCBA32(0x3820) = 0x0000000a; - RCBA32(0x3824) = 0x00000123; - RCBA32(0x3828) = 0x00000009; - RCBA32(0x382c) = 0x00000001; - RCBA32(0x3834) = 0x0000061a; - RCBA32(0x3838) = 0x00000003; - RCBA32(0x383c) = 0x00000a76; - RCBA32(0x3840) = 0x00000004; - RCBA32(0x3844) = 0x0000e5e4; - RCBA32(0x3848) = 0x0000000e; -} - -// mainboard_enable is executed as first thing after -// enumerate_buses(). - -static void mainboard_enable(struct device *dev) -{ - dev->ops->init = mainboard_init; - - install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, - GMA_INT15_PANEL_FIT_DEFAULT, - GMA_INT15_BOOT_DISPLAY_CRT, 0); -} - -struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/romstage.c index 035e20e..eb88d36 100644 --- a/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/romstage.c +++ b/src/mainboard/gigabyte/ga-panther-point/variants/ga-b75m-d3v/romstage.c @@ -25,12 +25,6 @@ #define SIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO) #define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01) -void mainboard_rcba_config(void) -{ - /* Enable HECI */ - RCBA32(FD2) &= ~0x2; -} - void pch_enable_lpc(void) { pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | @@ -40,7 +34,10 @@ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); +} +void mainboard_config_superio(void) +{ /* Initialize SuperIO */ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); @@ -87,19 +84,21 @@ { 1, 5, 6 }, }; -/* FIXME: This board only has two DIMM slots! */ -void mainboard_get_spd(spd_raw_data *spd, bool id_only) -{ - read_spd (&spd[0], 0x50, id_only); - read_spd (&spd[1], 0x51, id_only); - read_spd (&spd[2], 0x52, id_only); - read_spd (&spd[3], 0x53, id_only); -} - void mainboard_early_init(int s3resume) { } -void mainboard_config_superio(void) +/* FIXME: This board only has two DIMM slots! */ +void mainboard_get_spd(spd_raw_data *spd, bool id_only) { + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[1], 0x51, id_only); + read_spd(&spd[2], 0x52, id_only); + read_spd(&spd[3], 0x53, id_only); +} + +void mainboard_rcba_config(void) +{ + /* Enable HECI */ + RCBA32(FD2) &= ~0x2; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d11c55dc809b920bccf55f5f745d9f29b18bbb6 Gerrit-Change-Number: 32752 Gerrit-PatchSet: 1 Gerrit-Owner: Alex James <theracermaster(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/qualcomm/common: replace IS_ENABLED(CONFIG_*) with CONFIG()
by Patrick Georgi (Code Review) 16 May '19

16 May '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32813 Change subject: soc/qualcomm/common: replace IS_ENABLED(CONFIG_*) with CONFIG() ...................................................................... soc/qualcomm/common: replace IS_ENABLED(CONFIG_*) with CONFIG() That's how we do it these days. Change-Id: I1c088d23dff709bcdcb21310059e6a2aab84c0be Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/soc/qualcomm/common/qclib.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/32813/1 diff --git a/src/soc/qualcomm/common/qclib.c b/src/soc/qualcomm/common/qclib.c index 1fd79b5..73c5250 100644 --- a/src/soc/qualcomm/common/qclib.c +++ b/src/soc/qualcomm/common/qclib.c @@ -129,7 +129,7 @@ memset(ddr_region, 0, sizeof(struct region)); /* output area, QCLib copies console log buffer out */ - if (IS_ENABLED(CONFIG_CONSOLE_CBMEM)) + if (CONFIG(CONSOLE_CBMEM)) qclib_add_if_table_entry(QCLIB_TE_QCLIB_LOG_BUFFER, _qclib_serial_log, REGION_SIZE(qclib_serial_log), 0); @@ -152,11 +152,11 @@ } /* Enable QCLib serial output, based on Kconfig */ - if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + if (CONFIG(CONSOLE_SERIAL)) qclib_cb_if_table.global_attributes = QCLIB_GA_ENABLE_UART_LOGGING; - if (IS_ENABLED(CONFIG_QC_SDI_ENABLE)) { + if (CONFIG(QC_SDI_ENABLE)) { struct prog qcsdi = PROG_INIT(PROG_REFCODE, CONFIG_CBFS_PREFIX "/qcsdi"); -- To view, visit https://review.coreboot.org/c/coreboot/+/32813 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c088d23dff709bcdcb21310059e6a2aab84c0be Gerrit-Change-Number: 32813 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/ocp/monolake: replace IS_ENABLED(CONFIG_*) with CONFIG()
by Patrick Georgi (Code Review) 16 May '19

16 May '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32812 Change subject: mb/ocp/monolake: replace IS_ENABLED(CONFIG_*) with CONFIG() ...................................................................... mb/ocp/monolake: replace IS_ENABLED(CONFIG_*) with CONFIG() That's how we do it these days. Change-Id: I6bf6460440d0f2e6973734ba8894a4be981d03c5 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/ocp/monolake/mainboard.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/32812/1 diff --git a/src/mainboard/ocp/monolake/mainboard.c b/src/mainboard/ocp/monolake/mainboard.c index d457859..bbfeeaf 100644 --- a/src/mainboard/ocp/monolake/mainboard.c +++ b/src/mainboard/ocp/monolake/mainboard.c @@ -23,7 +23,7 @@ #define BMC_KCS_BASE 0xca2 #define INTERFACE_IS_IO 0x1 -#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) +#if CONFIG(GENERATE_SMBIOS_TABLES) static int mainboard_smbios_data(struct device *dev, int *handle, unsigned long *current) { @@ -50,7 +50,7 @@ */ static void mainboard_enable(struct device *dev) { -#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES) +#if CONFIG(GENERATE_SMBIOS_TABLES) dev->ops->get_smbios_data = mainboard_smbios_data; #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/32812 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6bf6460440d0f2e6973734ba8894a4be981d03c5 Gerrit-Change-Number: 32812 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: libpayload: make log2 and clz work on signed values internally
by Patrick Georgi (Code Review) 16 May '19

16 May '19

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32184 Change subject: libpayload: make log2 and clz work on signed values internally ...................................................................... libpayload: make log2 and clz work on signed values internally Needed to make libpayload build clean with -Wconversion. BUG=b:111443775 BRANCH=none TEST=make junit.xml shows fewer warnings with -Wconversion enabled Change-Id: Ie193e39854d2231b6d09a2b0deeeef2873e900ab Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M payloads/libpayload/include/libpayload.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/32184/1 diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 0b9ab0d..3cf6aee 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -409,9 +409,9 @@ void fatal(const char *msg) __attribute__((noreturn)); /* Count Leading Zeroes: clz(0) == 32, clz(0xf) == 28, clz(1 << 31) == 0 */ -static inline int clz(u32 x) { return x ? __builtin_clz(x) : sizeof(x) * 8; } +static inline int clz(u32 x) { return x ? __builtin_clz(x) : 32; } /* Integer binary logarithm (rounding down): log2(0) == -1, log2(5) == 2 */ -static inline int log2(u32 x) { return sizeof(x) * 8 - clz(x) - 1; } +static inline int log2(u32 x) { return (int)sizeof(x) * 8 - clz(x) - 1; } /* Find First Set: __ffs(0xf) == 0, __ffs(0) == -1, __ffs(1 << 31) == 31 */ static inline int __ffs(u32 x) { return log2(x & (u32)(-(s32)x)); } /** @} */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie193e39854d2231b6d09a2b0deeeef2873e900ab Gerrit-Change-Number: 32184 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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