coreboot-gerrit May 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: {drivers,soc/intel/braswell}: Add C_ENVIRONMENT_BOOTBLOCK support
by Arthur Heymans (Code Review) 17 May '19

17 May '19

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29662 ) Change subject: {drivers,soc/intel/braswell}: Add C_ENVIRONMENT_BOOTBLOCK support ...................................................................... Patch Set 23: Code-Review-1 (2 comments) https://review.coreboot.org/#/c/29662/23/src/soc/intel/braswell/bootblock/c… File src/soc/intel/braswell/bootblock/cache_as_ram.S: https://review.coreboot.org/#/c/29662/23/src/soc/intel/braswell/bootblock/c… PS23, Line 27: .global cache_as_ram To not have any functional changes, you need to update the microcode here, preferably after setting up caching of the ROM to speed up the cbfswalk. https://review.coreboot.org/#/c/29662/23/src/soc/intel/braswell/romstage/ca… File src/soc/intel/braswell/romstage/car_stage_entry.S: https://review.coreboot.org/#/c/29662/23/src/soc/intel/braswell/romstage/ca… PS23, Line 24: #include "src/drivers/intel/fsp1_1/after_raminit.S" : https://review.coreboot.org/c/coreboot/+/30686 implements postcar stage, which handles exiting CAR more cleanly. It might be a good idea to get that merged first? -- To view, visit https://review.coreboot.org/c/coreboot/+/29662 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c Gerrit-Change-Number: 29662 Gerrit-PatchSet: 23 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 17 May 2019 10:34:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/soc/intel/cannonlake: [TEST-ONLY]Update FSP-M upd config for cml
by Aamir Bohra (Code Review) 17 May '19

17 May '19

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32767 Change subject: src/soc/intel/cannonlake: [TEST-ONLY]Update FSP-M upd config for cml ...................................................................... src/soc/intel/cannonlake: [TEST-ONLY]Update FSP-M upd config for cml This patch updates the fsp-m config for cometlake platform. The FSP release from version 1155 onwards have updated fsp-m config for UART controller number used for debug logs purpose. Change-Id: I232630f91ba6bbc953064bddab7cf0e479510fc9 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/cannonlake/romstage/fsp_params.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/32767/1 diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 6e492bb..77bad8f 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -50,7 +50,11 @@ m_cfg->PcieRpEnableMask = mask; m_cfg->PrmrrSize = config->PrmrrSize; m_cfg->EnableC6Dram = config->enable_c6dram; +#if CONFIG(SOC_INTEL_COMETLAKE) + m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; +#else m_cfg->PcdSerialIoUartNumber = CONFIG_UART_FOR_CONSOLE; +#endif /* * PcdDebugInterfaceFlags * This config will allow coreboot to pass information to the FSP -- To view, visit https://review.coreboot.org/c/coreboot/+/32767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I232630f91ba6bbc953064bddab7cf0e479510fc9 Gerrit-Change-Number: 32767 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/skylake: Use PCI func0 if enabled in device tree
by Caveh Jalali (Code Review) 17 May '19

17 May '19

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32846 ) Change subject: soc/intel/skylake: Use PCI func0 if enabled in device tree ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/32846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c44ee5493eff1f9e04aa891030fde2a6f0c636f Gerrit-Change-Number: 32846 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Fri, 17 May 2019 08:54:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/include/assert.h: add noreturn attribute to dead_code()
by Alan Green (Code Review) 17 May '19

17 May '19

Alan Green has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32833 Change subject: src/include/assert.h: add noreturn attribute to dead_code() ...................................................................... src/include/assert.h: add noreturn attribute to dead_code() Clang does not recognize dead_code() as termination of execution. It gives this message: error: control reaches end of non-void function [-Werror,-Wreturn-type] This change adds an __attribute__((noreturn)) to ensure that clang recognises that this function will terminate execution. This change is more general solution to the problem that was addressed in the specific at https://review.coreboot.org/c/coreboot/+/32798 Signed-off-by: Alan Green <avg(a)google.com> Change-Id: I5ba7189559aa01545d5bbe893bced400a3aaabbb --- M src/include/assert.h 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/32833/1 diff --git a/src/include/assert.h b/src/include/assert.h index 4575a29..0ad7858 100644 --- a/src/include/assert.h +++ b/src/include/assert.h @@ -56,7 +56,8 @@ * bootmode.c:42: undefined reference to `dead_code_assertion_failed_at_line_42' */ #define __dead_code(line) do { \ - extern void dead_code_assertion_failed_at_line_##line(void); \ + extern void dead_code_assertion_failed_at_line_##line(void) \ + __attribute__((__noreturn__)); \ dead_code_assertion_failed_at_line_##line(); \ } while (0) #define _dead_code(line) __dead_code(line) -- To view, visit https://review.coreboot.org/c/coreboot/+/32833 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba7189559aa01545d5bbe893bced400a3aaabbb Gerrit-Change-Number: 32833 Gerrit-PatchSet: 1 Gerrit-Owner: Alan Green <avg(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/amd/cimx/sb800: Get rid of power button device in coreboot
by Stefan Reinauer (Code Review) 17 May '19

17 May '19

Stefan Reinauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27496 ) Change subject: sb/amd/cimx/sb800: Get rid of power button device in coreboot ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/27496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cbecb72f7e1bf3d051d3b7656c6af4d6f43b497 Gerrit-Change-Number: 27496 Gerrit-PatchSet: 6 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 16 May 2019 22:59:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: sb/amd/cimx/sb800: Get rid of power button device in coreboot
by Stefan Reinauer (Code Review) 17 May '19

17 May '19

Stefan Reinauer has uploaded a new patch set (#6) to the change originally created by Paul Menzel. ( https://review.coreboot.org/c/coreboot/+/27496 ) Change subject: sb/amd/cimx/sb800: Get rid of power button device in coreboot ...................................................................... sb/amd/cimx/sb800: Get rid of power button device in coreboot Apply commit d7b88dcb (mb/google/x86-boards: Get rid of power button device in coreboot) to AMD Brazos boards [1]: > As per the ACPI specification, there are two types of power button > devices: > 1. Fixed hardware power button > 2. Generic hardware power button > > Fixed hardware power button is added by the OSPM if POWER_BUTTON flag > is not set in FADT by the BIOS. This device has its programming model > in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this > power button device by default if the power button FADT flag is not > set. > > On the other hand, generic hardware power button can be used by > platforms if fixed register space cannot be used for the power button > device. In order to support this, power button device object with HID > PNP0C0C is expected to be added to ACPI tables. Additionally, > POWER_BUTTON flag should be set to indicate the presence of control > method for power button. [..] > This change gets rid of the generic hardware power button from all > google mainboards and relies completely on the fixed hardware power > button. The same problem exists with the AMD Hudson devices in coreboot. For AMD Hudson (2) and Yangtze based devices this was removed in commit 44f2fab8 (AMD hudson and yangtze boards: Let mainboard declare power button) [2]. Two devices are detected. $ dmesg | grep Button [ 0.209213] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input0 [ 0.209254] ACPI: Power Button [PWRB] [ 0.209332] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input1 [ 0.209349] ACPI: Power Button [PWRF] $ sudo evtest No device specified, trying to scan all of /dev/input/event* Available devices: /dev/input/event0: Power Button /dev/input/event1: Power Button [..] [1]: https://review.coreboot.org/5546 [2]: https://review.coreboot.org/27272 Change-Id: I0cbecb72f7e1bf3d051d3b7656c6af4d6f43b497 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- M src/mainboard/amd/inagua/acpi/gpe.asl M src/mainboard/amd/persimmon/acpi/gpe.asl M src/mainboard/amd/south_station/acpi/gpe.asl M src/mainboard/amd/union_station/acpi/gpe.asl M src/mainboard/asrock/e350m1/acpi/gpe.asl M src/mainboard/elmex/pcm205400/acpi/gpe.asl M src/mainboard/gizmosphere/gizmo/acpi/gpe.asl M src/mainboard/jetway/nf81-t56n-lf/acpi/gpe.asl M src/mainboard/pcengines/apu1/acpi/gpe.asl M src/southbridge/amd/cimx/sb800/acpi/fch.asl 10 files changed, 0 insertions(+), 90 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/27496/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/27496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cbecb72f7e1bf3d051d3b7656c6af4d6f43b497 Gerrit-Change-Number: 27496 Gerrit-PatchSet: 6 Gerrit-Owner: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: src/northbridge: Add missing 'include <types.h>'
by Lijian Zhao (Code Review) 16 May '19

16 May '19

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32808 ) Change subject: src/northbridge: Add missing 'include <types.h>' ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/32808 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad5367bed844b866b2ad87639eee29a16d9a99ed Gerrit-Change-Number: 32808 Gerrit-PatchSet: 2 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 16 May 2019 21:55:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: coreboot: Add new function die_with_post_code()
by Martin Roth (Code Review) 16 May '19

16 May '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32838 ) Change subject: coreboot: Add new function die_with_post_code() ...................................................................... Patch Set 1: Code-Review-1 (1 comment) https://review.coreboot.org/#/c/32838/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/32838/1//COMMIT_MSG@7 PS1, Line 7: coreboot: all or these patches are in coreboot, so this shouldn't be in the subject. Generally we want the area that's being affected - usually a directory. I'd use "console:" here -- To view, visit https://review.coreboot.org/c/coreboot/+/32838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87551d60b253dc13ff76f7898c1f112f573a00a2 Gerrit-Change-Number: 32838 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 16 May 2019 21:35:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: coreboot: Add new function die_with_post_code()
by Furquan Shaikh (Code Review) 16 May '19

16 May '19

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32838 ) Change subject: coreboot: Add new function die_with_post_code() ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/32838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87551d60b253dc13ff76f7898c1f112f573a00a2 Gerrit-Change-Number: 32838 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 16 May 2019 20:52:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: coreboot: Add new function die_with_post_code()
by Aaron Durbin (Code Review) 16 May '19

16 May '19

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32838 ) Change subject: coreboot: Add new function die_with_post_code() ...................................................................... Patch Set 1: Code-Review+2 assuming post_code() won't blow up for all the other platforms. -- To view, visit https://review.coreboot.org/c/coreboot/+/32838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87551d60b253dc13ff76f7898c1f112f573a00a2 Gerrit-Change-Number: 32838 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Thu, 16 May 2019 20:42:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit May 2019