Puthikorn Voravootivat has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32779
Change subject: mb/google/poppy/variants/atlas: Remove B0D4 _PSV ......................................................................
mb/google/poppy/variants/atlas: Remove B0D4 _PSV
Per Intel, the internal thermal protection is working better than putting B0D4 _PSV in dptf.
BUG=b:131251533 TEST=Get ~10% better Octane score. Correct TCC and TCC offset in MSR register.
Change-Id: If85afdc673687477ec85a47efcb264a7e5d6ae45 Signed-off-by: Puthikorn Voravootivat puthik@chromium.org --- M src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl 1 file changed, 0 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/32779/1
diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl index 29c1d3f..570fbbb 100644 --- a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl @@ -49,9 +49,6 @@ })
Name (DTRT, Package () { - /* CPU Throttle Effect on CPU */ - Package () { _SB.PCI0.B0D4, _SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, - /* CPU Throttle Effect on Ambient */ Package () { _SB.PCI0.B0D4, _SB.DPTF.TSR0, 100, 200, 0, 0, 0, 0 },
Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32779 )
Change subject: mb/google/poppy/variants/atlas: Remove B0D4 _PSV ......................................................................
Patch Set 1: Code-Review+2
Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32779 )
Change subject: mb/google/poppy/variants/atlas: Remove B0D4 _PSV ......................................................................
mb/google/poppy/variants/atlas: Remove B0D4 _PSV
Per Intel, the internal thermal protection is working better than putting B0D4 _PSV in dptf.
BUG=b:131251533 TEST=Get ~10% better Octane score. Correct TCC and TCC offset in MSR register.
Change-Id: If85afdc673687477ec85a47efcb264a7e5d6ae45 Signed-off-by: Puthikorn Voravootivat puthik@chromium.org Reviewed-on: https://review.coreboot.org/c/coreboot/+/32779 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Caveh Jalali caveh@google.com --- M src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl 1 file changed, 0 insertions(+), 3 deletions(-)
Approvals: build bot (Jenkins): Verified Caveh Jalali: Looks good to me, approved
diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl index 29c1d3f..570fbbb 100644 --- a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl @@ -49,9 +49,6 @@ })
Name (DTRT, Package () { - /* CPU Throttle Effect on CPU */ - Package () { _SB.PCI0.B0D4, _SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, - /* CPU Throttle Effect on Ambient */ Package () { _SB.PCI0.B0D4, _SB.DPTF.TSR0, 100, 200, 0, 0, 0, 0 },
-
Caveh Jalali (Code Review) -
Patrick Georgi (Code Review)
-
Puthikorn Voravootivat (Code Review)