coreboot-gerrit April 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: soc/intel/cannonlake: Add report for iGD 0x3ea1
by Lijian Zhao (Code Review) 19 Apr '19

19 Apr '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32320 Change subject: soc/intel/cannonlake: Add report for iGD 0x3ea1 ...................................................................... soc/intel/cannonlake: Add report for iGD 0x3ea1 Integrated graphics id 0x3ea1 reported as unknown in bootblock stage, make it correct. BUG=N/A TEST=Boot up into sarien platform and check with serial log, it shows IGD: device id 3ea1 (rev 02) is Whiskeylake ULT GT1. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I2c4c697b108be7fa74736514ca71469a1ca29c22 --- M src/soc/intel/cannonlake/bootblock/report_platform.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/32320/1 diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index 37b55c7..e0c9194 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -96,7 +96,8 @@ { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3, "Cannonlake ULT GT1" }, { PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4, "Cannonlake ULT GT0.5" }, { PCI_DEVICE_ID_INTEL_CFL_GT2_ULT, "Coffeelake ULT GT2" }, - { PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, "Whiskeylake ULT GT1" }, + { PCI_DEVICE_ID_INTEL_WHL_GT1_ULT_1, "Whiskeylake ULT GT1" }, + { PCI_DEVICE_ID_INTEL_WHL_GT2_ULT_1, "Whiskeylake ULT GT2" }, { PCI_DEVICE_ID_INTEL_CFL_H_GT2, "Coffeelake-H GT2" }, { PCI_DEVICE_ID_INTEL_CFL_S_GT2, "Coffeelake-S GT2" }, { PCI_DEVICE_ID_INTEL_CML_GT1_ULT_1, "CometLake ULT GT1" }, -- To view, visit https://review.coreboot.org/c/coreboot/+/32320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c4c697b108be7fa74736514ca71469a1ca29c22 Gerrit-Change-Number: 32320 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/common: Inject SMBIOS type 16 table
by Lijian Zhao (Code Review) 19 Apr '19

19 Apr '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32286 Change subject: soc/intel/common: Inject SMBIOS type 16 table ...................................................................... soc/intel/common: Inject SMBIOS type 16 table Add SMBIOS type 16 table for physical memory array, there's two item had been left over.ECC and max capacity, as of now we set it to fixed value as all the platform support by Intel common code don't support ECC memory and so far the biggest capicity is 32GB. TEST=Boot up with Sarien platform and check with dmidecode, the following is the result: Handle 0x000D, DMI type 16, 23 bytes Physical Memory Array Location: System Board Or Motherboard Use: System Memory Error Correction Type: None Maximum Capacity: 32 GB Error Information Handle: Not Provided Number Of Devices: 2 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: If9c5831956ef273c84d831a2b1572b3442eed961 --- M src/soc/intel/common/block/systemagent/systemagent.c 1 file changed, 37 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/32286/1 diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index d95a4eb..c66eb0a 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <console/console.h> #include <device/pci_ops.h> #include <cbmem.h> #include <device/device.h> @@ -21,6 +22,8 @@ #include <device/pci_ids.h> #include <intelblocks/acpi.h> #include <intelblocks/systemagent.h> +#include <smbios.h> +#include <memory_info.h> #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/systemagent.h> @@ -275,6 +278,37 @@ sa_add_imr_resources(dev, &index); } +#if CONFIG(GENERATE_SMBIOS_TABLES) +static int sa_smbios_write_type_16(struct device *dev, int *handle, + unsigned long *current) +{ + struct smbios_type16 *t = (struct smbios_type16 *)*current; + int len = sizeof(struct smbios_type16); + + struct memory_info *meminfo; + meminfo = cbmem_find(CBMEM_ID_MEMINFO); + if (meminfo == NULL) + return 0; /* can't find mem info in cbmem */ + + memset(t, 0, sizeof(struct smbios_type16)); + t->type = SMBIOS_PHYS_MEMORY_ARRAY; + t->handle = *handle; + t->length = len - 2; + t->location = MEMORY_ARRAY_LOCATION_SYSTEM_BOARD; + t->use = MEMORY_ARRAY_USE_SYSTEM; + /* TBD, meminfo hob have information about ECC */ + t->memory_error_correction = MEMORY_ARRAY_ECC_NONE; + /* no error information handle available */ + t->memory_error_information_handle = 0xFFFE; + t->maximum_capacity = 32 * (GiB / KiB); /* 32GB as default */ + t->number_of_memory_devices = meminfo->dimm_cnt; + + *current += len; + *handle += 1; + return len; +} +#endif + void enable_power_aware_intr(void) { uint8_t pair; @@ -295,6 +329,9 @@ #if CONFIG(HAVE_ACPI_TABLES) .write_acpi_tables = sa_write_acpi_tables, #endif +#if CONFIG(GENERATE_SMBIOS_TABLES) + .get_smbios_data = sa_smbios_write_type_16, +#endif }; static const unsigned short systemagent_ids[] = { -- To view, visit https://review.coreboot.org/c/coreboot/+/32286 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If9c5831956ef273c84d831a2b1572b3442eed961 Gerrit-Change-Number: 32286 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien: Update SMBIOS type17
by Lijian Zhao (Code Review) 19 Apr '19

19 Apr '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32280 Change subject: mb/google/sarien: Update SMBIOS type17 ...................................................................... mb/google/sarien: Update SMBIOS type17 Make SMBIOS type 17 device locator to be match with motherboard silkscreen, using "DIMM-A" and "DIMM-B" instead of "Channel-0-DIMM-0" and "Chaneek-1-DIMM-0". TEST=Boot up with sarien platform and run dmidecode to check SMBIOS type 17 have expected output. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: Ie2125c0381bd24d96f725f68cde93a53da8c94c8 --- M src/mainboard/google/sarien/ramstage.c 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/32280/1 diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c index 96321f8..e1fe62b 100644 --- a/src/mainboard/google/sarien/ramstage.c +++ b/src/mainboard/google/sarien/ramstage.c @@ -14,11 +14,33 @@ */ #include <arch/acpi.h> +#include <smbios.h> #include <soc/gpio.h> #include <soc/ramstage.h> #include <variant/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> +/* mainboard silk screen shows DIMM-A and DIMM-B */ +void smbios_fill_dimm_locator(const struct dimm_info *dimm, + struct smbios_type17 *t) +{ + switch(dimm->channel_num) { + case 0: + t->device_locator = smbios_add_string(t->eos, + "DIMM-A"); + break; + case 1: + t->device_locator = smbios_add_string(t->eos, + "DIMM-B"); + break; + default: { + t->device_locator = smbios_add_string(t->eos, + "UNKOWN"); + break; + } + } +} + void mainboard_silicon_init_params(FSP_S_CONFIG *params) { const struct pad_config *gpio_table; -- To view, visit https://review.coreboot.org/c/coreboot/+/32280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2125c0381bd24d96f725f68cde93a53da8c94c8 Gerrit-Change-Number: 32280 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: smbios: Add type 17 device/bank locator override
by Lijian Zhao (Code Review) 19 Apr '19

19 Apr '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32279 Change subject: smbios: Add type 17 device/bank locator override ...................................................................... smbios: Add type 17 device/bank locator override Current SMBIOS type 17 device and bank locator string is like "Channel-x-Dimm-x" and "Bank-x", x is deciminal number. Give silicon or mainboard vendor a chance to replace with something matches with silkscreen. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I54f7282244cb25a05780a3cdb9d1f5405c600513 --- M src/arch/x86/smbios.c M src/include/smbios.h 2 files changed, 17 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/32279/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 44ff578..d71c0d5 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -203,6 +203,19 @@ } } } +/* this function will fill the corresponding locator */ +void __weak smbios_fill_dimm_locator(const struct dimm_info *dimm, + struct smbios_type17 *t) +{ + char locator[40]; + + snprintf(locator, sizeof(locator), "Channel-%d-DIMM-%d", + dimm->channel_num, dimm->dimm_num); + t->device_locator = smbios_add_string(t->eos, locator); + + snprintf(locator, sizeof(locator), "BANK %d", dimm->bank_locator); + t->bank_locator = smbios_add_string(t->eos, locator); +} static void trim_trailing_whitespace(char *buffer, size_t buffer_size) { @@ -280,7 +293,6 @@ unsigned long *current, int *handle) { struct smbios_type17 *t = (struct smbios_type17 *)*current; - char locator[40]; memset(t, 0, sizeof(struct smbios_type17)); t->memory_type = dimm->ddr_type; @@ -316,13 +328,7 @@ smbios_fill_dimm_manufacturer_from_id(dimm->mod_id, t); smbios_fill_dimm_serial_number(dimm, t); - - snprintf(locator, sizeof(locator), "Channel-%d-DIMM-%d", - dimm->channel_num, dimm->dimm_num); - t->device_locator = smbios_add_string(t->eos, locator); - - snprintf(locator, sizeof(locator), "BANK %d", dimm->bank_locator); - t->bank_locator = smbios_add_string(t->eos, locator); + smbios_fill_dimm_locator(dimm, t); /* put '\0' in the end of data */ dimm->module_part_number[DIMM_INFO_PART_NUMBER_SIZE - 1] = '\0'; diff --git a/src/include/smbios.h b/src/include/smbios.h index 08e6b61..5e06947 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -19,6 +19,7 @@ #define SMBIOS_H #include <types.h> +#include <memory_info.h> unsigned long smbios_write_tables(unsigned long start); int smbios_add_string(u8 *start, const char *str); @@ -629,6 +630,8 @@ void smbios_fill_dimm_manufacturer_from_id(uint16_t mod_id, struct smbios_type17 *t); +void smbios_fill_dimm_locator(const struct dimm_info *dimm, + struct smbios_type17 *t); smbios_board_type smbios_mainboard_board_type(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/32279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54f7282244cb25a05780a3cdb9d1f5405c600513 Gerrit-Change-Number: 32279 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: acpi: Upgrade acpi generate header
by Duncan Laurie (Code Review) 19 Apr '19

19 Apr '19

Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32328 ) Change subject: acpi: Upgrade acpi generate header ...................................................................... acpi: Upgrade acpi generate header Sync acpigen.h content to match with laetst acpica, the link is https://github.com/acpica/acpica/blob/master/source/include/amlcode.h, and revision is 20190405. The purspose of the change is just make spec up to date. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: If5f5da70eb66472ddf5df0d72ca85de41faac128 Reviewed-on: https://review.coreboot.org/c/coreboot/+/32328 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> --- M src/arch/x86/include/arch/acpigen.h 1 file changed, 84 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Furquan Shaikh: Looks good to me, approved Patrick Rudolph: Looks good to me, approved diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index d9379eb..9e57693 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -42,29 +42,57 @@ /* ACPI Op/Prefix Codes */ enum { - ZERO_OP = 0x00, + ZERO_OP = 0x00, ONE_OP = 0x01, - NAME_OP = 0x08, - SCOPE_OP = 0x10, - BUFFER_OP = 0x11, + ALIAS_OP = 0x06, + NAME_OP = 0x08, BYTE_PREFIX = 0x0A, WORD_PREFIX = 0x0B, DWORD_PREFIX = 0x0C, STRING_PREFIX = 0x0D, QWORD_PREFIX = 0x0E, + SCOPE_OP = 0x10, + BUFFER_OP = 0x11, PACKAGE_OP = 0x12, + VARIABLE_PACKAGE_OP = 0x13, METHOD_OP = 0x14, + EXTERNAL_OP = 0x15, DUAL_NAME_PREFIX = 0x2E, MULTI_NAME_PREFIX = 0x2F, EXT_OP_PREFIX = 0x5B, + MUTEX_OP = 0x01, + EVENT_OP = 0x01, + SF_RIGHT_OP = 0x10, + SF_LEFT_OP = 0x11, + COND_REFOF_OP = 0x12, CREATEFIELD_OP = 0x13, + LOAD_TABLE_OP = 0x1f, + LOAD_OP = 0x20, + STALL_OP = 0x21, SLEEP_OP = 0x22, + ACQUIRE_OP = 0x23, + SIGNAL_OP = 0x24, + WAIT_OP = 0x25, + RST_OP = 0x26, + RELEASE_OP = 0x27, + FROM_BCD_OP = 0x28, + TO_BCD_OP = 0x29, + UNLOAD_OP = 0x2A, + REVISON_OP = 0x30, DEBUG_OP = 0x31, + FATAL_OP = 0x32, + TIMER_OP = 0x33, OPREGION_OP = 0x80, FIELD_OP = 0x81, DEVICE_OP = 0x82, PROCESSOR_OP = 0x83, POWER_RES_OP = 0x84, + THERMAL_ZONE_OP = 0x85, + INDEX_FIELD_OP = 0x86, + BANK_FIELD_OP = 0x87, + DATA_REGION_OP = 0x88, + ROOT_PREFIX = 0x5C, + PARENT_PREFIX = 0x5D, LOCAL0_OP = 0x60, LOCAL1_OP = 0x61, LOCAL2_OP = 0x62, @@ -73,29 +101,68 @@ LOCAL5_OP = 0x65, LOCAL6_OP = 0x66, LOCAL7_OP = 0x67, - ARG0_OP = 0x68, - ARG1_OP = 0x69, - ARG2_OP = 0x6A, - ARG3_OP = 0x6B, - ARG4_OP = 0x6C, - ARG5_OP = 0x6D, - ARG6_OP = 0x6E, + ARG0_OP = 0x68, + ARG1_OP = 0x69, + ARG2_OP = 0x6A, + ARG3_OP = 0x6B, + ARG4_OP = 0x6C, + ARG5_OP = 0x6D, + ARG6_OP = 0x6E, STORE_OP = 0x70, + REF_OF_OP = 0x71, + ADD_OP = 0x72, + CONCATENATE_OP = 0x73, SUBTRACT_OP = 0x74, + INCREMENT_OP = 0x75, + DECREMENT_OP = 0x76, MULTIPLY_OP = 0x77, + DIVIDE_OP = 0x78, + SHIFT_LEFT_OP = 0x79, + SHIFT_RIGHT_OP = 0x7A, AND_OP = 0x7B, + NAND_OP = 0x7C, OR_OP = 0x7D, + NOR_OP = 0x7E, + XOR_OP = 0x7F, NOT_OP = 0x80, + FD_SHIFT_LEFT_BIT_OR = 0x81, + FD_SHIFT_RIGHT_BIT_OR = 0x82, + DEREF_OP = 0x83, + CONCATENATE_TEMP_OP = 0x84, + MOD_OP = 0x85, NOTIFY_OP = 0x86, + SIZEOF_OP = 0x87, + INDEX_OP = 0x88, + MATCH_OP = 0x89, + CREATE_DWORD_OP = 0x8A, + CREATE_WORD_OP = 0x8B, + CREATE_BYTE_OP = 0x8C, + CREATE_BIT_OP = 0x8D, + OBJ_TYPE_OP = 0x8E, + CREATE_QWORD_OP = 0x8F, + LAND_OP = 0x90, + LOR_OP = 0x91, + LNOT_OP = 0x92, LEQUAL_OP = 0x93, LGREATER_OP = 0x94, LLESS_OP = 0x95, TO_BUFFER_OP = 0x96, + TO_DEC_STRING_OP = 0x97, + TO_HEX_STRING_OP = 0x98, TO_INTEGER_OP = 0x99, + TO_STRING_OP = 0x9C, + CP_OBJ_OP = 0x9D, + MID_OP = 0x9E, + CONTINUE_OP = 0x9F, IF_OP = 0xA0, - ELSE_OP = 0xA1, + ELSE_OP = 0xA1, + WHILE_OP = 0xA2, + NOOP_OP = 0xA3, RETURN_OP = 0xA4, - ONES_OP = 0xFF, + BREAK_OP = 0xA5, + COMMENT_OP = 0xA9, + BREAKPIONT_OP = 0xCC, + ONES_OP = 0xFF, }; #define FIELDLIST_OFFSET(X) { .type = OFFSET, \ @@ -146,6 +213,10 @@ CMOS, PCIBARTARGET, IPMI, + GPIO_REGION, + GPSERIALBUS, + PCC, + FIXED_HARDWARE = 0x7F, REGION_SPACE_MAX, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/32328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5f5da70eb66472ddf5df0d72ca85de41faac128 Gerrit-Change-Number: 32328 Gerrit-PatchSet: 5 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: mb/google/sarien: Update GPIO GPP_C23 setting
by Lijian Zhao (Code Review) 19 Apr '19

19 Apr '19

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32347 Change subject: mb/google/sarien: Update GPIO GPP_C23 setting ...................................................................... mb/google/sarien: Update GPIO GPP_C23 setting GPIO pin GPP_C23 is used as level trigger but not edge trigger, also it not invented, correct it here. BUG=b:128554235 TEST=Boot up arcada platform with stylus keep on touching the screen, the touch screen is still functional once in OS stage. Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> Change-Id: I2bee664198057e3997dda181a16b9a0388067036 --- M src/mainboard/google/sarien/variants/arcada/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/32347/1 diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index 570ab4a..b66e1dd 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -104,7 +104,7 @@ /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */ /* UART2_RTS# */ PAD_NC(GPP_C22, NONE), /* UART2_CTS# */ PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST, - EDGE_SINGLE, INVERT), /* TS_INT# */ + LEVEL, NONE), /* TS_INT# */ /* SPI1_CS# */ PAD_CFG_GPI_APIC(GPP_D0, NONE, PLTRST, EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32347 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2bee664198057e3997dda181a16b9a0388067036 Gerrit-Change-Number: 32347 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP]mainboard/lenovo/t410: Add new port
by Okashi Odayakana (Code Review) 19 Apr '19

19 Apr '19

Okashi Odayakana has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/11791 ) Change subject: [WIP]mainboard/lenovo/t410: Add new port ...................................................................... Patch Set 13: Can't seem to get this one to boot. Anything in particular I should be doing? -- To view, visit https://review.coreboot.org/c/coreboot/+/11791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Gerrit-Change-Number: 11791 Gerrit-PatchSet: 13 Gerrit-Owner: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eloy Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Okashi Odayakana <brianblevins316(a)gmail.com> Gerrit-CC: Okashi Odayakana <okashi(a)okashi.me> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Comment-Date: Fri, 19 Apr 2019 01:27:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: ec/google/wilco: Support board_id with EC provided ID
by Duncan Laurie (Code Review) 18 Apr '19

18 Apr '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32276 Change subject: ec/google/wilco: Support board_id with EC provided ID ...................................................................... ec/google/wilco: Support board_id with EC provided ID The EC can return a board ID value similar to the Chrome EC. In order to use this for the board version returned by SMBIOS this commit implements the board_id() function for mainboards that use this EC. BUG=b:123261132 TEST=Check /sys/class/dmi/id/board_version to see that it is reflecting the value that the EC provides. Change-Id: I3fbe0dc886701f37d2424fe7a2867fd860fa1ec0 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/ec/google/wilco/Makefile.inc A src/ec/google/wilco/boardid.c M src/ec/google/wilco/commands.c M src/ec/google/wilco/commands.h 4 files changed, 54 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/32276/1 diff --git a/src/ec/google/wilco/Makefile.inc b/src/ec/google/wilco/Makefile.inc index fe8910c..3a7790c 100644 --- a/src/ec/google/wilco/Makefile.inc +++ b/src/ec/google/wilco/Makefile.inc @@ -1,8 +1,8 @@ ifeq ($(CONFIG_EC_GOOGLE_WILCO),y) bootblock-y += bootblock.c -romstage-y += commands.c mailbox.c romstage.c -ramstage-y += chip.c commands.c mailbox.c -smm-y += commands.c mailbox.c smihandler.c +romstage-y += commands.c mailbox.c romstage.c boardid.c +ramstage-y += chip.c commands.c mailbox.c boardid.c +smm-y += commands.c mailbox.c smihandler.c boardid.c endif diff --git a/src/ec/google/wilco/boardid.c b/src/ec/google/wilco/boardid.c new file mode 100644 index 0000000..4ed15bb --- /dev/null +++ b/src/ec/google/wilco/boardid.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 Google LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boardid.h> +#include "commands.h" + +uint32_t board_id(void) +{ + MAYBE_STATIC uint32_t id = BOARD_ID_INIT; + + if (id == BOARD_ID_INIT) { + uint8_t ec_id; + if (wilco_ec_get_board_id(&ec_id) < 0) + id = BOARD_ID_UNKNOWN; + else + id = ec_id; + } + + return id; +} diff --git a/src/ec/google/wilco/commands.c b/src/ec/google/wilco/commands.c index da04e27..d0d572d 100644 --- a/src/ec/google/wilco/commands.c +++ b/src/ec/google/wilco/commands.c @@ -135,6 +135,12 @@ return !!(pm.state[0] & EC_PM1_LID_OPEN); } +int wilco_ec_get_board_id(uint8_t *id) +{ + return wilco_ec_mailbox(WILCO_EC_MSG_RAW, KB_BOARD_ID, + NULL, 0, id, sizeof(*id)); +} + void wilco_ec_slp_en(void) { /* EC does not respond to this command */ diff --git a/src/ec/google/wilco/commands.h b/src/ec/google/wilco/commands.h index 85f5feb..3077eee 100644 --- a/src/ec/google/wilco/commands.h +++ b/src/ec/google/wilco/commands.h @@ -38,6 +38,8 @@ KB_EC_INFO = 0x38, /* Set ACPI mode on or off */ KB_ACPI = 0x3a, + /* Board ID */ + KB_BOARD_ID = 0x3d, /* Change ACPI wake up source */ KB_ACPI_WAKEUP_CHANGE = 0x4a, /* Manage the EC power button passthru to the host */ @@ -267,6 +269,17 @@ */ int wilco_ec_get_lid_state(void); +/** + * wilco_ec_get_board_id + * + * Retrieve the board ID value from the EC. + * @id: Pointer to variable to store the ID read from the EC. + * + * Returns number of bytes transferred from the EC + * Returns -1 if the EC command failed + */ +int wilco_ec_get_board_id(uint8_t *id); + enum ec_wake_change { WAKE_OFF = 0, WAKE_ON -- To view, visit https://review.coreboot.org/c/coreboot/+/32276 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3fbe0dc886701f37d2424fe7a2867fd860fa1ec0 Gerrit-Change-Number: 32276 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien: Enable board_id feature
by Duncan Laurie (Code Review) 18 Apr '19

18 Apr '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32277 Change subject: mb/google/sarien: Enable board_id feature ...................................................................... mb/google/sarien: Enable board_id feature Enable the Kconfig option to automatically read the board ID and populate it into the SMBIOS tables. BUG=b:123261132 TEST=verify current board id from the OS: cat /sys/class/dmi/id/board_version rev1 Change-Id: Id41631bfaa627ca9d5034e2ebe93f8ace2ffdad8 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/mainboard/google/sarien/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/32277/1 diff --git a/src/mainboard/google/sarien/Kconfig b/src/mainboard/google/sarien/Kconfig index 58ab300..9d658fa 100644 --- a/src/mainboard/google/sarien/Kconfig +++ b/src/mainboard/google/sarien/Kconfig @@ -9,6 +9,7 @@ select DRIVERS_USB_ACPI select EC_GOOGLE_WILCO select GENERIC_SPD_BIN + select GOOGLE_SMBIOS_MAINBOARD_VERSION select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_LPSS_UART_FOR_CONSOLE -- To view, visit https://review.coreboot.org/c/coreboot/+/32277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id41631bfaa627ca9d5034e2ebe93f8ace2ffdad8 Gerrit-Change-Number: 32277 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: ec/google/wilco: Send "logo displayed" progress code
by Duncan Laurie (Code Review) 18 Apr '19

18 Apr '19

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32348 Change subject: ec/google/wilco: Send "logo displayed" progress code ...................................................................... ec/google/wilco: Send "logo displayed" progress code This progress code enables keyboard backlight control that otherwise would only work 30 seconds after boot. This code is already defined but it was not being sent by coreboot. It is run in the "post device" step between the other defined progress codes. BUG=b:130754032 Change-Id: Ica6c622e568cb236c17bf3edb6639d0177510846 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- M src/ec/google/wilco/chip.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/32348/1 diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c index 0858e1c..9b0be19 100644 --- a/src/ec/google/wilco/chip.c +++ b/src/ec/google/wilco/chip.c @@ -46,6 +46,13 @@ BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, wilco_ec_post_video_init, NULL); +static void wilco_ec_post_logo_displayed(void *unused) +{ + wilco_ec_send(KB_BIOS_PROGRESS, BIOS_PROGRESS_LOGO_DISPLAYED); +} +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, + wilco_ec_post_logo_displayed, NULL); + static void wilco_ec_resume(void *unused) { wilco_ec_send_noargs(KB_RESTORE); -- To view, visit https://review.coreboot.org/c/coreboot/+/32348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica6c622e568cb236c17bf3edb6639d0177510846 Gerrit-Change-Number: 32348 Gerrit-PatchSet: 1 Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-MessageType: newchange

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coreboot-gerrit April 2019