coreboot-gerrit April 2019

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Change in ...coreboot[master]: arch/x86/postcar: Configure MMU along with MTRRs
by Patrick Rudolph (Code Review) 20 Apr '19

20 Apr '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30501 ) Change subject: arch/x86/postcar: Configure MMU along with MTRRs ...................................................................... Patch Set 4: Code-Review-1 According to "Intel® 64 and IA-32 Architectures Software Developer's Manual" the lesser caching wins when MMU is enabled, that is if MTRRs are properly installed, we can mark all page-tables as WB. There's also no need for special postcar handling, we can load the new pagetables in romstage at any time (when we know how much memory is available). -- To view, visit https://review.coreboot.org/c/coreboot/+/30501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I235c70f05f63ed6d5146f093cf7f735879de4219 Gerrit-Change-Number: 30501 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 20 Apr 2019 09:22:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: AMD microcodes: scripts for applying the unofficial (not-merged-yet) ...
by build bot (Jenkins) (Code Review) 20 Apr '19

20 Apr '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28425 ) Change subject: AMD microcodes: scripts for applying the unofficial (not-merged-yet) updates ...................................................................... Patch Set 10: (5 comments) https://review.coreboot.org/#/c/28425/10/apply_ucode_patches.sh File apply_ucode_patches.sh: https://review.coreboot.org/#/c/28425/10/apply_ucode_patches.sh@4 PS10, Line 4: ### src/vendorcode/amd/agesa/f15tn: Update microcode to version 0x600111F 2018-03-05 line over 80 characters https://review.coreboot.org/#/c/28425/10/apply_ucode_patches.sh@9 PS10, Line 9: ### src/vendorcode/amd/agesa/f16kb: Update microcode to version 0x7000110 2018-02-09 line over 80 characters https://review.coreboot.org/#/c/28425/10/check_ucode_patches.sh File check_ucode_patches.sh: https://review.coreboot.org/#/c/28425/10/check_ucode_patches.sh@10 PS10, Line 10: echo "! MISMATCH ! See ./sha256sums_ucode_my.txt and ./sha256sums_ucode_correct.txt" line over 80 characters https://review.coreboot.org/#/c/28425/10/get_ucode_patches.sh File get_ucode_patches.sh: https://review.coreboot.org/#/c/28425/10/get_ucode_patches.sh@5 PS10, Line 5: ### src/vendorcode/amd/agesa/f15tn: Update microcode to version 0x600111F 2018-03-05 line over 80 characters https://review.coreboot.org/#/c/28425/10/get_ucode_patches.sh@11 PS10, Line 11: ### src/vendorcode/amd/agesa/f16kb: Update microcode to version 0x7000110 2018-02-09 line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/28425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic16c1c4b86576ee7505cceed871b47a2b82f3c56 Gerrit-Change-Number: 28425 Gerrit-PatchSet: 10 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Comment-Date: Sat, 20 Apr 2019 06:32:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: AMD microcodes: scripts for applying the unofficial (not-merged-yet) ...
by mikeb mikeb (Code Review) 20 Apr '19

20 Apr '19

Hello Paul Menzel, Mike Banon, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/28425 to look at the new patch set (#10). Change subject: AMD microcodes: scripts for applying the unofficial (not-merged-yet) updates ...................................................................... AMD microcodes: scripts for applying the unofficial (not-merged-yet) updates These scripts will help you to securely and conveniently apply the two changes 28273 and 28370 to update AMD microcodes for f15tn and f16kb family processors. Save to ./coreboot/ then run ./get_ucode_patches.sh , ./check... and ./apply... https://review.coreboot.org/c/coreboot/+/28273 src/vendorcode/amd/agesa/f15tn: Update microcode to version 0x600111F 2018-03-05 https://review.coreboot.org/c/coreboot/+/28370 src/vendorcode/amd/agesa/f16kb: Update microcode to version 0x7000110 2018-02-09 Change-Id: Ic16c1c4b86576ee7505cceed871b47a2b82f3c56 Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> --- A apply_ucode_patches.sh A check_ucode_patches.sh A get_ucode_patches.sh A sha256sums_ucode_correct.txt 4 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/28425/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/28425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic16c1c4b86576ee7505cceed871b47a2b82f3c56 Gerrit-Change-Number: 28425 Gerrit-PatchSet: 10 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: AMD microcodes: scripts for applying the unofficial (not-merged-yet) ...
by build bot (Jenkins) (Code Review) 20 Apr '19

20 Apr '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28425 ) Change subject: AMD microcodes: scripts for applying the unofficial (not-merged-yet) updates ...................................................................... Patch Set 9: (4 comments) https://review.coreboot.org/#/c/28425/9/apply_ucode_patches.sh File apply_ucode_patches.sh: https://review.coreboot.org/#/c/28425/9/apply_ucode_patches.sh@4 PS9, Line 4: ### src/vendorcode/amd/agesa/f15tn: Update microcode to version 0x600111F 2018-03-05 line over 80 characters https://review.coreboot.org/#/c/28425/9/apply_ucode_patches.sh@9 PS9, Line 9: ### src/vendorcode/amd/agesa/f16kb: Update microcode to version 0x7000110 2018-02-09 line over 80 characters https://review.coreboot.org/#/c/28425/9/get_ucode_patches.sh File get_ucode_patches.sh: https://review.coreboot.org/#/c/28425/9/get_ucode_patches.sh@5 PS9, Line 5: ### src/vendorcode/amd/agesa/f15tn: Update microcode to version 0x600111F 2018-03-05 line over 80 characters https://review.coreboot.org/#/c/28425/9/get_ucode_patches.sh@11 PS9, Line 11: ### src/vendorcode/amd/agesa/f16kb: Update microcode to version 0x7000110 2018-02-09 line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/28425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic16c1c4b86576ee7505cceed871b47a2b82f3c56 Gerrit-Change-Number: 28425 Gerrit-PatchSet: 9 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Comment-Date: Sat, 20 Apr 2019 06:22:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: AMD microcodes: scripts for applying the unofficial (not-merged-yet) ...
by mikeb mikeb (Code Review) 20 Apr '19

20 Apr '19

Hello Paul Menzel, Mike Banon, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/28425 to look at the new patch set (#9). Change subject: AMD microcodes: scripts for applying the unofficial (not-merged-yet) updates ...................................................................... AMD microcodes: scripts for applying the unofficial (not-merged-yet) updates These scripts will help you to securely and conveniently apply the two changes 28273 and 28370 to update AMD microcodes for f15tn and f16kb family processors. Save to ./coreboot/ then run ./get_ucode_patches.sh , ./check... and ./apply... https://review.coreboot.org/c/coreboot/+/28273 src/vendorcode/amd/agesa/f15tn: Update microcode to version 0x600111F 2018-03-05 https://review.coreboot.org/c/coreboot/+/28370 src/vendorcode/amd/agesa/f16kb: Update microcode to version 0x7000110 2018-02-09 Change-Id: Ic16c1c4b86576ee7505cceed871b47a2b82f3c56 Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> --- A apply_ucode_patches.sh A check_ucode_patches.sh A get_ucode_patches.sh A sha256sums_ucode_correct.txt 4 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/28425/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/28425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic16c1c4b86576ee7505cceed871b47a2b82f3c56 Gerrit-Change-Number: 28425 Gerrit-PatchSet: 9 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: AMD microcodes: scripts for applying the unofficial (not-merged-yet) ...
by build bot (Jenkins) (Code Review) 20 Apr '19

20 Apr '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28425 ) Change subject: AMD microcodes: scripts for applying the unofficial (not-merged-yet) updates ...................................................................... Patch Set 8: (4 comments) https://review.coreboot.org/#/c/28425/8/apply_ucode_patches.sh File apply_ucode_patches.sh: https://review.coreboot.org/#/c/28425/8/apply_ucode_patches.sh@4 PS8, Line 4: ### src/vendorcode/amd/agesa/f15tn: Update microcode to version 0x600111F 2018-03-05 line over 80 characters https://review.coreboot.org/#/c/28425/8/apply_ucode_patches.sh@9 PS8, Line 9: ### src/vendorcode/amd/agesa/f16kb: Update microcode to version 0x7000110 2018-02-09 line over 80 characters https://review.coreboot.org/#/c/28425/8/get_ucode_patches.sh File get_ucode_patches.sh: https://review.coreboot.org/#/c/28425/8/get_ucode_patches.sh@5 PS8, Line 5: ### src/vendorcode/amd/agesa/f15tn: Update microcode to version 0x600111F 2018-03-05 line over 80 characters https://review.coreboot.org/#/c/28425/8/get_ucode_patches.sh@11 PS8, Line 11: ### src/vendorcode/amd/agesa/f16kb: Update microcode to version 0x7000110 2018-02-09 line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/28425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic16c1c4b86576ee7505cceed871b47a2b82f3c56 Gerrit-Change-Number: 28425 Gerrit-PatchSet: 8 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Comment-Date: Sat, 20 Apr 2019 05:42:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/braswell: Include LPE ACPI code in mainboard
by Martin Roth (Code Review) 20 Apr '19

20 Apr '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29414 ) Change subject: soc/intel/braswell: Include LPE ACPI code in mainboard ...................................................................... Patch Set 10: (1 comment) https://review.coreboot.org/#/c/29414/10/src/mainboard/google/cyan/dsdt.asl File src/mainboard/google/cyan/dsdt.asl: https://review.coreboot.org/#/c/29414/10/src/mainboard/google/cyan/dsdt.asl… PS10, Line 7: * Copyright (C) 2019 Eltan B.V. Is this contribution really worth adding a copyright line? Is it a "Creative and significant" contribution? While I don't disagree that it's copyrightable, I'd ask you to consider whether it's reasonable and only add a copyright line when it's actually significant. -- To view, visit https://review.coreboot.org/c/coreboot/+/29414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73 Gerrit-Change-Number: 29414 Gerrit-PatchSet: 10 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 20 Apr 2019 04:33:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: nb/intel/nehalem: Hide some raminit output messages
by Arthur Heymans (Code Review) 20 Apr '19

20 Apr '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32318 Change subject: nb/intel/nehalem: Hide some raminit output messages ...................................................................... nb/intel/nehalem: Hide some raminit output messages Hide some debug output behind CONFIG_DEBUG_RAM_SETUP. That way the pre-ram console does not overflow. Change-Id: Idc425f4d10443f6ee7f9b4da67eb6542069cc40c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/nehalem/Kconfig M src/northbridge/intel/nehalem/raminit.c 2 files changed, 19 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/32318/1 diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 9eb6e75..1e50459 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -23,6 +23,7 @@ select CACHE_MRC_SETTINGS select POSTCAR_STAGE select POSTCAR_CONSOLE + select HAVE_DEBUG_RAM_SETUP if NORTHBRIDGE_INTEL_NEHALEM diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 78bc6de..3164a58 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -1568,14 +1568,14 @@ static void dump_timings(struct raminfo *info) { int channel, slot, rank, lane, i; - printk(BIOS_DEBUG, "Timings:\n"); + printk(RAM_DEBUG, "Timings:\n"); FOR_POPULATED_RANKS { - printk(BIOS_DEBUG, "channel %d, slot %d, rank %d\n", channel, + printk(RAM_DEBUG, "channel %d, slot %d, rank %d\n", channel, slot, rank); for (lane = 0; lane < 9; lane++) { - printk(BIOS_DEBUG, "lane %d: ", lane); + printk(RAM_DEBUG, "lane %d: ", lane); for (i = 0; i < 4; i++) { - printk(BIOS_DEBUG, "%x (%x) ", + printk(RAM_DEBUG, "%x (%x) ", read_500(info, channel, get_timing_register_addr (lane, i, slot, rank), @@ -1584,12 +1584,12 @@ lane_timings[i][channel][slot][rank] [lane]); } - printk(BIOS_DEBUG, "\n"); + printk(RAM_DEBUG, "\n"); } } - printk(BIOS_DEBUG, "[178] = %x (%x)\n", read_1d0(0x178, 7), + printk(RAM_DEBUG, "[178] = %x (%x)\n", read_1d0(0x178, 7), info->training.reg_178); - printk(BIOS_DEBUG, "[10b] = %x (%x)\n", read_1d0(0x10b, 6), + printk(RAM_DEBUG, "[10b] = %x (%x)\n", read_1d0(0x10b, 6), info->training.reg_10b); } @@ -1623,8 +1623,8 @@ train.reg_6dc = MCHBAR32(0x6dc); train.reg_6e8 = MCHBAR32(0x6e8); - printk (BIOS_SPEW, "[6dc] = %x\n", train.reg_6dc); - printk (BIOS_SPEW, "[6e8] = %x\n", train.reg_6e8); + printk(RAM_SPEW, "[6dc] = %x\n", train.reg_6dc); + printk(RAM_SPEW, "[6e8] = %x\n", train.reg_6e8); /* Save the MRC S3 restore data to cbmem */ mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, @@ -3403,7 +3403,7 @@ 0, 1, &ratios2); compute_frequence_ratios(info, freq1, freq2, num_cycles_3, num_cycles_4, 0, 1, &ratios1); - printk (BIOS_SPEW, "[%x] <= %x\n", reg, + printk(RAM_SPEW, "[%x] <= %x\n", reg, ratios1.freq4_to_max_remainder | (ratios2. freq4_to_max_remainder << 8) @@ -3486,7 +3486,8 @@ frequency_11(info) / 2, 4000, 4000, 0, 0); if (s3resume) { - printk (BIOS_SPEW, "[6dc] <= %x\n", info->cached_training->reg_6dc); + printk(RAM_SPEW, "[6dc] <= %x\n", + info->cached_training->reg_6dc); MCHBAR32(0x6dc) = info->cached_training->reg_6dc; } else set_6d_reg(info, 0x6dc, 2 * info->fsb_frequency, frequency_11(info), 0, @@ -3497,7 +3498,8 @@ set_2dx8_reg(info, 0x6e4, 1, 2 * info->fsb_frequency, frequency_11(info) / 2, 3500, 0, 0, 0); if (s3resume) { - printk (BIOS_SPEW, "[6e8] <= %x\n", info->cached_training->reg_6e8); + printk(RAM_SPEW, "[6e8] <= %x\n", + info->cached_training->reg_6e8); MCHBAR32(0x6e8) = info->cached_training->reg_6e8; } else set_6d_reg(info, 0x6e8, 2 * info->fsb_frequency, frequency_11(info), 0, @@ -4026,19 +4028,19 @@ int j; if (s3resume && info.cached_training) { restore_274265(&info); - printk(BIOS_DEBUG, "reg2ca9_bit0 = %x\n", + printk(RAM_DEBUG, "reg2ca9_bit0 = %x\n", info.cached_training->reg2ca9_bit0); for (i = 0; i < 2; i++) for (j = 0; j < 3; j++) - printk(BIOS_DEBUG, "reg274265[%d][%d] = %x\n", + printk(RAM_DEBUG, "reg274265[%d][%d] = %x\n", i, j, info.cached_training->reg274265[i][j]); } else { set_274265(&info); - printk(BIOS_DEBUG, "reg2ca9_bit0 = %x\n", + printk(RAM_DEBUG, "reg2ca9_bit0 = %x\n", info.training.reg2ca9_bit0); for (i = 0; i < 2; i++) for (j = 0; j < 3; j++) - printk(BIOS_DEBUG, "reg274265[%d][%d] = %x\n", + printk(RAM_DEBUG, "reg274265[%d][%d] = %x\n", i, j, info.training.reg274265[i][j]); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idc425f4d10443f6ee7f9b4da67eb6542069cc40c Gerrit-Change-Number: 32318 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/facebook/watson: Don't use deprecated IS_ENABLED
by HAOUAS Elyes (Code Review) 20 Apr '19

20 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32312 Change subject: mb/facebook/watson: Don't use deprecated IS_ENABLED ...................................................................... mb/facebook/watson: Don't use deprecated IS_ENABLED Change-Id: Ia4b7311f30f8ec951d02d3c31c30cf8895ed0eb2 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/facebook/watson/mainboard.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/32312/1 diff --git a/src/mainboard/facebook/watson/mainboard.c b/src/mainboard/facebook/watson/mainboard.c index 3a1692f..403090a 100644 --- a/src/mainboard/facebook/watson/mainboard.c +++ b/src/mainboard/facebook/watson/mainboard.c @@ -29,7 +29,7 @@ static void mainboard_init(void *chip_info) { -#if !IS_ENABLED(CONFIG_ENABLE_TURBO) +#if !CONFIG(ENABLE_TURBO) disable_turbo(); #endif } -- To view, visit https://review.coreboot.org/c/coreboot/+/32312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4b7311f30f8ec951d02d3c31c30cf8895ed0eb2 Gerrit-Change-Number: 32312 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/arcada: Set psys_pmax to 140W
by Nathan Chen (Code Review) 20 Apr '19

20 Apr '19

Nathan Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32335 Change subject: mb/google/arcada: Set psys_pmax to 140W ...................................................................... mb/google/arcada: Set psys_pmax to 140W arcada is designed to operate at max power of 140 Watt. Hence set psys_max to 140W. BUG=b:124792558 BRANCH=None TEST=Build and boot arcada. Change-Id: I280dfb81b3e25c7619a68db487e2b18867f52fda --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/32335/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 9ecbf00..2056dd6 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -28,6 +28,7 @@ register "PchPmSlpAMinAssert" = "4" # 2s register "speed_shift_enable" = "1" + register "psys_pmax" = "140" register "s0ix_enable" = "1" register "dptf_enable" = "1" register "dmipwroptimize" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/32335 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I280dfb81b3e25c7619a68db487e2b18867f52fda Gerrit-Change-Number: 32335 Gerrit-PatchSet: 1 Gerrit-Owner: Nathan Chen <nathan_chen(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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coreboot-gerrit April 2019