Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30500 )
Change subject: [WIP]arch/x86/postcar: Add x86_64 support
......................................................................
Patch Set 8:
(3 comments)
https://review.coreboot.org/#/c/30500/8/src/arch/x86/exit_car_x86_64.S
File src/arch/x86/exit_car_x86_64.S:
https://review.coreboot.org/#/c/30500/8/src/arch/x86/exit_car_x86_64.S@70
PS8, Line 70: * 0x00: Number of variable MTRRs to clear
You changed last two items to size_t so they would use 8 bytes each.
https://review.coreboot.org/#/c/30500/8/src/arch/x86/exit_car_x86_64.S@84
PS8, Line 84: pop %rbx /* Number to clear, Number to set */
The comment is wrong?
https://review.coreboot.org/#/c/30500/8/src/arch/x86/exit_car_x86_64.S@100
PS8, Line 100: shr %rbx /* Number to set. */
Should this be 'pop %rbx'?
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28464 )
Change subject: drivers/intel/fsp1_1: Configure UART after memory init
......................................................................
Patch Set 4:
A "new" version of the FSP was released. Please test if it fixes your issue.
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Hello Patrick Rudolph, Felix Held, Matt DeVillier, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30385
to look at the new patch set (#40).
Change subject: soc/intel/broadwell: Enable LPC/SIO setup in bootblock
......................................................................
soc/intel/broadwell: Enable LPC/SIO setup in bootblock
This allows for serial console during the bootblock and enables
bootblock console by default.
Change-Id: I7746e4f819486d6142c96bc4c7480076fbfdfbde
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/google/jecht/Makefile.inc
A src/mainboard/google/jecht/bootblock.c
M src/mainboard/google/jecht/romstage.c
M src/soc/intel/broadwell/Kconfig
M src/soc/intel/broadwell/bootblock/pch.c
A src/soc/intel/broadwell/include/soc/bootblock.h
M src/soc/intel/broadwell/romstage/pch.c
M src/soc/intel/broadwell/romstage/romstage.c
8 files changed, 109 insertions(+), 63 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/30385/40
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Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30384
to look at the new patch set (#39).
Change subject: nb/intel/broadwell: Add an option for where verstage starts
......................................................................
nb/intel/broadwell: Add an option for where verstage starts
Previously broadwell used a romcc bootblock and starting verstage in
romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also
possible to have a separate verstage.
This selects using a separate verstage by default but still keeps the
option around to use verstage in romstage.
Also make sure mrc.bin is only added to the COREBOOT fmap region as it
requires to be run at a specific offset. This means that coreboot will
have to jump from a RW region to the RO region for that binary and
back to that RW region after that binary is done initializing the
memory.
Change-Id: I900233cadb3c76da329fb98f93917570e633365f
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/google/auron/Makefile.inc
M src/mainboard/google/jecht/Makefile.inc
M src/mainboard/intel/wtm2/Makefile.inc
M src/soc/intel/broadwell/Kconfig
M src/soc/intel/broadwell/Makefile.inc
M src/soc/intel/broadwell/romstage/raminit.c
6 files changed, 35 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/30384/39
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Hello Kyösti Mälkki, Patrick Rudolph, Patrick Rudolph, Tristan Corrick, Duncan Laurie, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30315
to look at the new patch set (#47).
Change subject: sb/intel/lynxpoint: Enable LPC/SIO setup in bootblock
......................................................................
sb/intel/lynxpoint: Enable LPC/SIO setup in bootblock
This allows for serial console during the bootblock and enables
console in general for the bootblock.
Change-Id: I5c6e107c267a7acb5bf9cbeb54eb5361af3b6db4
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/asrock/h81m-hds/Makefile.inc
A src/mainboard/asrock/h81m-hds/bootblock.c
M src/mainboard/asrock/h81m-hds/romstage.c
M src/northbridge/intel/haswell/Kconfig
M src/southbridge/intel/lynxpoint/Makefile.inc
M src/southbridge/intel/lynxpoint/bootblock.c
M src/southbridge/intel/lynxpoint/early_pch.c
7 files changed, 56 insertions(+), 37 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/30315/47
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Hello Aaron Durbin, Patrick Rudolph, Patrick Rudolph, Duncan Laurie, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/26926
to look at the new patch set (#50).
Change subject: nb/intel/haswell: Add an option for where verstage starts
......................................................................
nb/intel/haswell: Add an option for where verstage starts
Previously Haswell used a romcc bootblock and starting verstage in
romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also
possible to have a separate verstage.
This selects using a separate verstage by default but still keeps the
option around to use verstage in romstage.
Also make sure mrc.bin is only added to the COREBOOT fmap region as it
requires to be run at a specific offset. This means that coreboot will
have to jump from a RW region to the RO region for that binary and
back to that RW region after that binary is done initializing the
memory.
Change-Id: I3b7b29f4a24c0fb830ff76fe31a35b6afcae4e67
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/intel/haswell/Makefile.inc
M src/mainboard/google/beltino/Makefile.inc
M src/mainboard/intel/baskingridge/Makefile.inc
M src/northbridge/intel/haswell/Kconfig
M src/southbridge/intel/common/Makefile.inc
M src/southbridge/intel/lynxpoint/Makefile.inc
M src/southbridge/intel/lynxpoint/pmutil.c
7 files changed, 36 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/26926/50
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Hello Kyösti Mälkki, Patrick Rudolph, Julius Werner, Patrick Rudolph, Matt DeVillier, Duncan Laurie, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/26859
to look at the new patch set (#55).
Change subject: cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK
......................................................................
cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK
This puts the cache-as-ram init in the bootblock.
Before setting up cache as ram the microcode updates are applied.
This removes the possibility for a normal/fallback setup although
implementing this should be quite easy.
Tested on Google peppy (Acer C720).
Setting up LPC in the bootblock to output console on SuperIOs is not
done in this patch, hence BOOTBLOCK_CONSOLE is not yet enabled by
default.
Change-Id: Ia96499a9d478127f6b9d880883ac41397b58dbea
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/intel/car/non-evict/cache_as_ram.S
M src/cpu/intel/haswell/Kconfig
M src/cpu/intel/haswell/Makefile.inc
M src/cpu/intel/haswell/bootblock.c
M src/northbridge/intel/haswell/Kconfig
M src/northbridge/intel/haswell/Makefile.inc
M src/northbridge/intel/haswell/bootblock.c
M src/southbridge/intel/lynxpoint/Kconfig
M src/southbridge/intel/lynxpoint/Makefile.inc
M src/southbridge/intel/lynxpoint/bootblock.c
M src/southbridge/intel/lynxpoint/early_pch.c
11 files changed, 33 insertions(+), 77 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/26859/55
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30117 )
Change subject: arch/x86: Support x86_64 exceptions
......................................................................
Patch Set 12:
(2 comments)
https://review.coreboot.org/#/c/30117/12/src/arch/x86/include/arch/register…
File src/arch/x86/include/arch/registers.h:
https://review.coreboot.org/#/c/30117/12/src/arch/x86/include/arch/register…
PS12, Line 46: #define QUAD_DOWNTO8(A) \
macros should not use a trailing semicolon
https://review.coreboot.org/#/c/30117/12/src/arch/x86/include/arch/register…
PS12, Line 52: #define QUAD_DOWNTO16(A) \
macros should not use a trailing semicolon
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Gerrit-Comment-Date: Sat, 20 Apr 2019 12:17:58 +0000
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Hello Patrick Rudolph, Huang Jin, Philipp Deppenwiese, build bot (Jenkins), Damien Zammit, David Guckian, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/32374
to look at the new patch set (#4).
Change subject: intel: Add functions to retrieve top of usable DRAM
......................................................................
intel: Add functions to retrieve top of usable DRAM
Implement the following functions on all Intel platforms:
* sa_get_touud_base
Returns the memory address of usable DRAM beyond 4GiB or zero if not
available.
* sa_get_tolud_base
Returns the memory address of usable DRAM below 4GiB
Allows to use both functions in common code. It could be used to:
* clear DRAM as part of TEE
* set up page tables for x86_64
Change-Id: I9ae1f3540d13076469f73188351ae9f9d4b1c63b
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/mainboard/emulation/qemu-i440fx/Makefile.inc
M src/mainboard/emulation/qemu-i440fx/fw_cfg.c
M src/mainboard/emulation/qemu-i440fx/fw_cfg.h
A src/mainboard/emulation/qemu-i440fx/systemagent_early.c
M src/mainboard/emulation/qemu-q35/Makefile.inc
M src/northbridge/intel/e7505/Makefile.inc
A src/northbridge/intel/e7505/systemagent_early.c
M src/northbridge/intel/fsp_rangeley/Makefile.inc
A src/northbridge/intel/fsp_rangeley/systemagent_early.c
M src/northbridge/intel/gm45/Makefile.inc
A src/northbridge/intel/gm45/systemagent_early.c
M src/northbridge/intel/haswell/Makefile.inc
A src/northbridge/intel/haswell/systemagent_early.c
M src/northbridge/intel/i440bx/Makefile.inc
A src/northbridge/intel/i440bx/systemagent_early.c
M src/northbridge/intel/i945/Makefile.inc
A src/northbridge/intel/i945/systemagent_early.c
M src/northbridge/intel/nehalem/Makefile.inc
A src/northbridge/intel/nehalem/systemagent_early.c
M src/northbridge/intel/pineview/Makefile.inc
A src/northbridge/intel/pineview/systemagent_early.c
M src/northbridge/intel/sandybridge/Makefile.inc
A src/northbridge/intel/sandybridge/systemagent_early.c
M src/northbridge/intel/x4x/Makefile.inc
A src/northbridge/intel/x4x/systemagent_early.c
M src/soc/intel/baytrail/romstage/Makefile.inc
A src/soc/intel/baytrail/romstage/systemagent_early.c
M src/soc/intel/braswell/romstage/Makefile.inc
A src/soc/intel/braswell/romstage/systemagent_early.c
M src/soc/intel/broadwell/include/soc/systemagent.h
M src/soc/intel/broadwell/romstage/Makefile.inc
R src/soc/intel/broadwell/romstage/systemagent_early.c
M src/soc/intel/common/block/include/intelblocks/systemagent.h
A src/soc/intel/common/block/include/intelblocks/systemagent_memrange.h
M src/soc/intel/common/block/systemagent/systemagent_early.c
M src/soc/intel/fsp_baytrail/romstage/Makefile.inc
A src/soc/intel/fsp_baytrail/romstage/systemagent_early.c
M src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h
M src/soc/intel/fsp_broadwell_de/romstage/Makefile.inc
A src/soc/intel/fsp_broadwell_de/romstage/systemagent_early.c
M src/soc/intel/quark/romstage/Makefile.inc
A src/soc/intel/quark/romstage/systemagent_early.c
42 files changed, 609 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/32374/4
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