coreboot-gerrit April 2019

coreboot-gerrit@coreboot.org

1 participants
1219 discussions

Change in ...coreboot[master]: arch/x86: Support x86_64 exceptions
by build bot (Jenkins) (Code Review) 20 Apr '19

20 Apr '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30117 ) Change subject: arch/x86: Support x86_64 exceptions ...................................................................... Patch Set 11: (2 comments) https://review.coreboot.org/#/c/30117/11/src/arch/x86/include/arch/register… File src/arch/x86/include/arch/registers.h: https://review.coreboot.org/#/c/30117/11/src/arch/x86/include/arch/register… PS11, Line 46: #define QUAD_DOWNTO8(A) \ macros should not use a trailing semicolon https://review.coreboot.org/#/c/30117/11/src/arch/x86/include/arch/register… PS11, Line 52: #define QUAD_DOWNTO16(A) \ macros should not use a trailing semicolon -- To view, visit https://review.coreboot.org/c/coreboot/+/30117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd12c90a95cc2989eb9b2a718740a84222193f48 Gerrit-Change-Number: 30117 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 20 Apr 2019 11:28:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: intel: Add functions to retrieve top of usable DRAM
by Patrick Rudolph (Code Review) 20 Apr '19

20 Apr '19

Hello Patrick Rudolph, Huang Jin, Philipp Deppenwiese, build bot (Jenkins), Damien Zammit, David Guckian, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/32374 to look at the new patch set (#3). Change subject: intel: Add functions to retrieve top of usable DRAM ...................................................................... intel: Add functions to retrieve top of usable DRAM Implement the following functions on all Intel platforms: * sa_get_touud_base Returns the memory address of usable DRAM beyond 4GiB or zero if not available. * sa_get_tolud_base Returns the memory address of usable DRAM below 4GiB Allows to use both functions in common code. It could be used to: * clear DRAM as part of TEE * set up page tables for x86_64 Change-Id: I9ae1f3540d13076469f73188351ae9f9d4b1c63b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/emulation/qemu-i440fx/Makefile.inc M src/mainboard/emulation/qemu-i440fx/fw_cfg.c M src/mainboard/emulation/qemu-i440fx/fw_cfg.h A src/mainboard/emulation/qemu-i440fx/systemagent_early.c M src/mainboard/emulation/qemu-q35/Makefile.inc M src/northbridge/intel/e7505/Makefile.inc A src/northbridge/intel/e7505/systemagent_early.c M src/northbridge/intel/fsp_rangeley/Makefile.inc A src/northbridge/intel/fsp_rangeley/systemagent_early.c M src/northbridge/intel/gm45/Makefile.inc A src/northbridge/intel/gm45/systemagent_early.c M src/northbridge/intel/haswell/Makefile.inc A src/northbridge/intel/haswell/systemagent_early.c M src/northbridge/intel/i440bx/Makefile.inc A src/northbridge/intel/i440bx/systemagent_early.c M src/northbridge/intel/i945/Makefile.inc A src/northbridge/intel/i945/systemagent_early.c M src/northbridge/intel/nehalem/Makefile.inc A src/northbridge/intel/nehalem/systemagent_early.c M src/northbridge/intel/pineview/Makefile.inc A src/northbridge/intel/pineview/systemagent_early.c M src/northbridge/intel/sandybridge/Makefile.inc A src/northbridge/intel/sandybridge/systemagent_early.c M src/northbridge/intel/x4x/Makefile.inc A src/northbridge/intel/x4x/systemagent_early.c M src/soc/intel/baytrail/romstage/Makefile.inc A src/soc/intel/baytrail/romstage/systemagent_early.c M src/soc/intel/braswell/romstage/Makefile.inc A src/soc/intel/braswell/romstage/systemagent_early.c M src/soc/intel/broadwell/include/soc/systemagent.h M src/soc/intel/broadwell/romstage/Makefile.inc D src/soc/intel/broadwell/romstage/systemagent.c A src/soc/intel/broadwell/romstage/systemagent_early.c M src/soc/intel/common/block/include/intelblocks/systemagent.h A src/soc/intel/common/block/include/intelblocks/systemagent_memrange.h M src/soc/intel/common/block/systemagent/systemagent_early.c M src/soc/intel/fsp_baytrail/romstage/Makefile.inc A src/soc/intel/fsp_baytrail/romstage/systemagent_early.c M src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h M src/soc/intel/fsp_broadwell_de/romstage/Makefile.inc A src/soc/intel/fsp_broadwell_de/romstage/systemagent_early.c M src/soc/intel/quark/romstage/Makefile.inc A src/soc/intel/quark/romstage/systemagent_early.c 43 files changed, 626 insertions(+), 76 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/32374/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/32374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ae1f3540d13076469f73188351ae9f9d4b1c63b Gerrit-Change-Number: 32374 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: arch/x86: Support x86_64 exceptions
by build bot (Jenkins) (Code Review) 20 Apr '19

20 Apr '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30117 ) Change subject: arch/x86: Support x86_64 exceptions ...................................................................... Patch Set 10: (2 comments) https://review.coreboot.org/#/c/30117/10/src/arch/x86/include/arch/register… File src/arch/x86/include/arch/registers.h: https://review.coreboot.org/#/c/30117/10/src/arch/x86/include/arch/register… PS10, Line 46: #define QUAD_DOWNTO8(A) \ macros should not use a trailing semicolon https://review.coreboot.org/#/c/30117/10/src/arch/x86/include/arch/register… PS10, Line 52: #define QUAD_DOWNTO16(A) \ macros should not use a trailing semicolon -- To view, visit https://review.coreboot.org/c/coreboot/+/30117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd12c90a95cc2989eb9b2a718740a84222193f48 Gerrit-Change-Number: 30117 Gerrit-PatchSet: 10 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 20 Apr 2019 11:15:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: intel: Add functions to retrieve top of usable DRAM
by Patrick Rudolph (Code Review) 20 Apr '19

20 Apr '19

Hello Patrick Rudolph, Huang Jin, Philipp Deppenwiese, Damien Zammit, David Guckian, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/32374 to look at the new patch set (#2). Change subject: intel: Add functions to retrieve top of usable DRAM ...................................................................... intel: Add functions to retrieve top of usable DRAM Implement the following functions on all Intel platforms: * sa_get_touud_base Returns the memory address of usable DRAM beyond 4GiB or zero if not available. * sa_get_tolud_base Returns the memory address of usable DRAM below 4GiB Allows to use both functions in common code. It could be used to: * clear DRAM as part of TEE * set up page tables for x86_64 Change-Id: I9ae1f3540d13076469f73188351ae9f9d4b1c63b Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/emulation/qemu-i440fx/Makefile.inc M src/mainboard/emulation/qemu-i440fx/fw_cfg.c M src/mainboard/emulation/qemu-i440fx/fw_cfg.h A src/mainboard/emulation/qemu-i440fx/systemagent_early.c M src/mainboard/emulation/qemu-q35/Makefile.inc M src/northbridge/intel/e7505/Makefile.inc A src/northbridge/intel/e7505/systemagent_early.c M src/northbridge/intel/fsp_rangeley/Makefile.inc A src/northbridge/intel/fsp_rangeley/systemagent_early.c M src/northbridge/intel/gm45/Makefile.inc A src/northbridge/intel/gm45/systemagent_early.c M src/northbridge/intel/haswell/Makefile.inc A src/northbridge/intel/haswell/systemagent_early.c M src/northbridge/intel/i440bx/Makefile.inc A src/northbridge/intel/i440bx/systemagent_early.c M src/northbridge/intel/i945/Makefile.inc A src/northbridge/intel/i945/systemagent_early.c M src/northbridge/intel/nehalem/Makefile.inc A src/northbridge/intel/nehalem/systemagent_early.c M src/northbridge/intel/pineview/Makefile.inc A src/northbridge/intel/pineview/systemagent_early.c M src/northbridge/intel/sandybridge/Makefile.inc A src/northbridge/intel/sandybridge/systemagent_early.c M src/northbridge/intel/x4x/Makefile.inc A src/northbridge/intel/x4x/systemagent_early.c M src/soc/intel/baytrail/romstage/Makefile.inc A src/soc/intel/baytrail/romstage/systemagent_early.c M src/soc/intel/braswell/romstage/Makefile.inc A src/soc/intel/braswell/romstage/systemagent_early.c M src/soc/intel/broadwell/include/soc/systemagent.h M src/soc/intel/broadwell/romstage/Makefile.inc D src/soc/intel/broadwell/romstage/systemagent.c M src/soc/intel/common/block/include/intelblocks/systemagent.h A src/soc/intel/common/block/include/intelblocks/systemagent_memrange.h M src/soc/intel/common/block/systemagent/systemagent_early.c M src/soc/intel/fsp_baytrail/romstage/Makefile.inc A src/soc/intel/fsp_baytrail/romstage/systemagent_early.c M src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h M src/soc/intel/fsp_broadwell_de/romstage/Makefile.inc A src/soc/intel/fsp_broadwell_de/romstage/systemagent_early.c M src/soc/intel/quark/romstage/Makefile.inc A src/soc/intel/quark/romstage/systemagent_early.c 42 files changed, 594 insertions(+), 76 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/32374/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/32374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ae1f3540d13076469f73188351ae9f9d4b1c63b Gerrit-Change-Number: 32374 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: arch/x86: Support x86_64 exceptions
by build bot (Jenkins) (Code Review) 20 Apr '19

20 Apr '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30117 ) Change subject: arch/x86: Support x86_64 exceptions ...................................................................... Patch Set 9: (2 comments) https://review.coreboot.org/#/c/30117/9/src/arch/x86/include/arch/registers… File src/arch/x86/include/arch/registers.h: https://review.coreboot.org/#/c/30117/9/src/arch/x86/include/arch/registers… PS9, Line 46: #define QUAD_DOWNTO8(A) \ macros should not use a trailing semicolon https://review.coreboot.org/#/c/30117/9/src/arch/x86/include/arch/registers… PS9, Line 52: #define QUAD_DOWNTO16(A) \ macros should not use a trailing semicolon -- To view, visit https://review.coreboot.org/c/coreboot/+/30117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idd12c90a95cc2989eb9b2a718740a84222193f48 Gerrit-Change-Number: 30117 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 20 Apr 2019 10:46:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/emulation/qemu-q35: Add x86_64 support
by Patrick Rudolph (Code Review) 20 Apr '19

20 Apr '19

Hello Patrick Rudolph, Aaron Durbin, ron minnich, Julius Werner, Stefan Reinauer, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29667 to look at the new patch set (#17). Change subject: mb/emulation/qemu-q35: Add x86_64 support ...................................................................... mb/emulation/qemu-q35: Add x86_64 support * Enable optional x86_64 romstage, postcar and ramstage * Add Kconfig for x86_64 compilation * Add documentation for x86 qemu mainboards * Increase CAR stack as x86_64 uses more than 0x4000 bytes * Always setup MTRRs even though qemu doesn't care about them Working: * Boots to Linux * Boots to SeaBios * Drops to protected mode at end of ramstage * Enumerates PCI devices * Relocateable ramstage Broken: * Entering SMM due to missing long mode setup Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5 --- M Documentation/arch/x86/index.md A Documentation/mainboard/emulation/qemu-i440fx.md A Documentation/mainboard/emulation/qemu-q35.md M Documentation/mainboard/index.md M src/arch/x86/Kconfig M src/cpu/qemu-x86/Kconfig M src/cpu/qemu-x86/Makefile.inc M src/mainboard/emulation/qemu-i440fx/Kconfig M src/mainboard/emulation/qemu-i440fx/romstage.c M src/mainboard/emulation/qemu-q35/Kconfig M src/mainboard/emulation/qemu-q35/romstage.c 11 files changed, 263 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/29667/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/29667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5 Gerrit-Change-Number: 29667 Gerrit-PatchSet: 17 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: arch/x86/mmu: Port armv8 MMU to x86_64
by Patrick Rudolph (Code Review) 20 Apr '19

20 Apr '19

Patrick Rudolph has uploaded a new patch set (#11) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/30119 ) Change subject: arch/x86/mmu: Port armv8 MMU to x86_64 ...................................................................... arch/x86/mmu: Port armv8 MMU to x86_64 Add functions to set up page tables for long mode. Required to support x86_64, as the MMU is always active. I didn't touch pae/pgtbl.c for the following reasons: * arch/x86/mmu.c generates long mode page tables, while pgtbl.c operates on 32bit/PAE page tables * arch/x86/mmu.c generates dynamic page tables, while pgtbl.c has static tables read from cbfs * arch/x86/mmu.c is intended for RAM environments, while pgtbl.c is for PRERAM environments * arch/x86/mmu.c is designed like the other arch/*/mmu.c Tested on qemu. Doesn't affect existing x86_32 code. Change-Id: I6e8b46e65925823a84b8ccd647c7d6848aa20992 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/arch/x86/index.md M src/arch/x86/Kconfig A src/arch/x86/include/arch/mmu.h A src/arch/x86/mmu.c M src/commonlib/include/commonlib/cbmem_id.h 5 files changed, 497 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/30119/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/30119 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e8b46e65925823a84b8ccd647c7d6848aa20992 Gerrit-Change-Number: 30119 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: arch/x86/assembly_entry: Enable long mode in romstage
by Patrick Rudolph (Code Review) 20 Apr '19

20 Apr '19

Patrick Rudolph has uploaded a new patch set (#7) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/30114 ) Change subject: arch/x86/assembly_entry: Enable long mode in romstage ...................................................................... arch/x86/assembly_entry: Enable long mode in romstage * Install simple page tables for long mode * Activate long mode * Add new Kconfig for CPUs that have 1 GiB hugepage support * Use a minimum of two pagetables if possible * Autodetect 1 GiB hugepage support if not known at compile time The same approach was done on AMD based platforms. The main reason to have a 64bit romstage, is to support rmodules. The existing code assumes that both stages (the loader and the one that is being relocated) have the same architecture. Tested on qemu using KVM. Doesn't affect existing x86_32 code. Change-Id: I57974a55f3b778c90b3587f39e86e4eb8692ad48 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/arch/x86/index.md M src/arch/x86/Kconfig M src/arch/x86/assembly_entry.S M src/cpu/Kconfig M src/cpu/intel/fsp_model_406dx/Kconfig M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/fsp_baytrail/Kconfig M src/soc/intel/fsp_broadwell_de/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/skylake/Kconfig 17 files changed, 171 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/30114/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/30114 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I57974a55f3b778c90b3587f39e86e4eb8692ad48 Gerrit-Change-Number: 30114 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: [WIP]arch/x86/postcar: Add x86_64 support
by Patrick Rudolph (Code Review) 20 Apr '19

20 Apr '19

Patrick Rudolph has uploaded a new patch set (#5) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/30500 ) Change subject: [WIP]arch/x86/postcar: Add x86_64 support ...................................................................... [WIP]arch/x86/postcar: Add x86_64 support * Add support for loading GDT on x86_64. * Add x86_64 assembly code to do the same as the x86_32 code. * Seperate x86_32 and x86_64 code. Tested on qemu x86_32 and x86_64 using additional MTRRs. Needs test on real hardware. Change-Id: I1c190627f5f0ed6f82738cb99423892382899d7b Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/arch/x86/Makefile.inc R src/arch/x86/exit_car_x86_32.S A src/arch/x86/exit_car_x86_64.S M src/arch/x86/gdt_init.S 4 files changed, 158 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/30500/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/30500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1c190627f5f0ed6f82738cb99423892382899d7b Gerrit-Change-Number: 30500 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: src/mb/Kconfig: Fix PCI subsystem IDs
by Kyösti Mälkki (Code Review) 20 Apr '19

20 Apr '19

Hello HAOUAS Elyes, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32107 to review the following change. Change subject: src/mb/Kconfig: Fix PCI subsystem IDs ...................................................................... src/mb/Kconfig: Fix PCI subsystem IDs Change-Id: I72bba8406eea4a264e36cc9bcf467cf5cfbed379 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- M src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t530/Kconfig M util/autoport/bd82x6x.go 4 files changed, 0 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/32107/1 diff --git a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig index 5fba47a..5e46365 100644 --- a/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig +++ b/src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig @@ -40,14 +40,6 @@ string default "GA-H61M-S2PV" -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x5001 - -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x1458 - config MAX_CPUS int default 8 diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index c414083..06f296b 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -65,14 +65,6 @@ string default "pci8086,0126.rom" -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x17aa - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x21cf - config ONBOARD_VGA_IS_PRIMARY bool default y diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 14f9fb2..b36460d 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -62,14 +62,6 @@ default "pci8086,0106.rom" if BOARD_LENOVO_T530 default "pci8086,0166.rom" if BOARD_LENOVO_W530 -config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID - hex - default 0x17aa - -config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID - hex - default 0x21fa - config ONBOARD_VGA_IS_PRIMARY bool default y diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 265cb6f..a97ff1d 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -181,12 +181,6 @@ } KconfigComment["DRAM_RESET_GATE_GPIO"] = "FIXME: check this" - /* Not strictly speaking correct. These subsys/subvendor referer to PCI devices. - But most systems don't have any of those. But the config needs to be set - nevertheless. So set it to southbridge subsys/subvendor. */ - KconfigHex["MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID"] = uint32(GetLE16(addr.ConfigDump[0x2c:0x2e])) - KconfigHex["MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID"] = uint32(GetLE16(addr.ConfigDump[0x2e:0x30])) - ich9GetFlashSize(ctx) DSDTDefines = append(DSDTDefines, -- To view, visit https://review.coreboot.org/c/coreboot/+/32107 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I72bba8406eea4a264e36cc9bcf467cf5cfbed379 Gerrit-Change-Number: 32107 Gerrit-PatchSet: 1 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit April 2019