coreboot-gerrit April 2019

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Change in ...coreboot[master]: nb/intel/haswell: Add an option for where verstage starts
by Martin Roth (Code Review) 21 Apr '19

21 Apr '19

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/26926 ) Change subject: nb/intel/haswell: Add an option for where verstage starts ...................................................................... nb/intel/haswell: Add an option for where verstage starts Previously Haswell used a romcc bootblock and starting verstage in romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also possible to have a separate verstage. This selects using a separate verstage by default but still keeps the option around to use verstage in romstage. Also make sure mrc.bin is only added to the COREBOOT fmap region as it requires to be run at a specific offset. This means that coreboot will have to jump from a RW region to the RO region for that binary and back to that RW region after that binary is done initializing the memory. Change-Id: I3b7b29f4a24c0fb830ff76fe31a35b6afcae4e67 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26926 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/intel/haswell/Makefile.inc M src/mainboard/google/beltino/Makefile.inc M src/mainboard/intel/baskingridge/Makefile.inc M src/northbridge/intel/haswell/Kconfig M src/southbridge/intel/common/Makefile.inc M src/southbridge/intel/lynxpoint/Makefile.inc M src/southbridge/intel/lynxpoint/pmutil.c 7 files changed, 36 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Patrick Rudolph: Looks good to me, but someone else must approve diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 3b52294..f83d5db 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -28,6 +28,8 @@ postcar-y += ../car/non-evict/exit_car.S +verstage-y += tsc_freq.c + subdirs-y += ../../x86/tsc subdirs-y += ../../x86/mtrr subdirs-y += ../../x86/lapic diff --git a/src/mainboard/google/beltino/Makefile.inc b/src/mainboard/google/beltino/Makefile.inc index 5e45472..bb90e97 100644 --- a/src/mainboard/google/beltino/Makefile.inc +++ b/src/mainboard/google/beltino/Makefile.inc @@ -15,6 +15,7 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c +verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += chromeos.c ramstage-y += lan.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c variants/$(VARIANT_DIR)/led.c diff --git a/src/mainboard/intel/baskingridge/Makefile.inc b/src/mainboard/intel/baskingridge/Makefile.inc index 5ef8363..06e86c1 100644 --- a/src/mainboard/intel/baskingridge/Makefile.inc +++ b/src/mainboard/intel/baskingridge/Makefile.inc @@ -15,5 +15,6 @@ romstage-y += chromeos.c ramstage-y += chromeos.c +verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += chromeos.c smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 242ab18..e0c55d2 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -27,9 +27,25 @@ if NORTHBRIDGE_INTEL_HASWELL +config HASWELL_VBOOT_IN_BOOTBLOCK + depends on VBOOT + bool "Start verstage in bootblock" + default y + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_SEPARATE_VERSTAGE + help + Haswell can either start verstage in a separate stage + right after the bootblock has run or it can start it + after romstage for compatibility reasons. + Haswell however uses a mrc.bin to initialse memory which + needs to be located at a fixed offset. Therefore even with + a separate verstage starting after the bootblock that same + binary is used meaning a jump is made from RW to the RO region + and back to the RW region after the binary is done. + config VBOOT select VBOOT_OPROM_MATTERS - select VBOOT_STARTS_IN_ROMSTAGE + select VBOOT_STARTS_IN_ROMSTAGE if !HASWELL_VBOOT_IN_BOOTBLOCK config VGA_BIOS_ID string @@ -93,4 +109,11 @@ VBIOS. On those systems we need to wait for a bit before executing the VBIOS. +# The UEFI System Agent binary needs to be at a fixed offset in the flash +# and can therefore only reside in the COREBOOT fmap region +config RO_REGION_ONLY + string + depends on VBOOT + default "mrc.bin" + endif diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index ac339a2..1085f6c 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -29,6 +29,7 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y) +verstage-y += pmbase.c romstage-y += pmbase.c ramstage-y += pmbase.c postcar-y += pmbase.c @@ -59,6 +60,7 @@ smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE) += finalize.c +verstage-y += rtc.c romstage-y += rtc.c ramstage-y += rtc.c postcar-y += rtc.c diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index 62766df..fd00f6c 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -55,4 +55,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += lp_gpio.c endif +verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += pmutil.c +verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += lp_gpio.c + endif diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index 3c63723..cc49477 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -24,6 +24,9 @@ #include <device/pci.h> #include <device/pci_def.h> #include <console/console.h> +#include <security/vboot/vbnv.h> +#include <security/vboot/vboot_common.h> +#include <southbridge/intel/common/rtc.h> #include "pch.h" #if CONFIG(INTEL_LYNXPOINT_LP) -- To view, visit https://review.coreboot.org/c/coreboot/+/26926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b7b29f4a24c0fb830ff76fe31a35b6afcae4e67 Gerrit-Change-Number: 26926 Gerrit-PatchSet: 51 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: merged

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Change in ...coreboot[master]: cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK
by Martin Roth (Code Review) 21 Apr '19

21 Apr '19

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/26859 ) Change subject: cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK ...................................................................... cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK This puts the cache-as-ram init in the bootblock. Before setting up cache as ram the microcode updates are applied. This removes the possibility for a normal/fallback setup although implementing this should be quite easy. Tested on Google peppy (Acer C720). Setting up LPC in the bootblock to output console on SuperIOs is not done in this patch, hence BOOTBLOCK_CONSOLE is not yet enabled by default. Change-Id: Ia96499a9d478127f6b9d880883ac41397b58dbea Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26859 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/haswell/Kconfig M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/haswell/bootblock.c M src/northbridge/intel/haswell/Kconfig M src/northbridge/intel/haswell/Makefile.inc M src/northbridge/intel/haswell/bootblock.c M src/southbridge/intel/lynxpoint/Kconfig M src/southbridge/intel/lynxpoint/Makefile.inc M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/early_pch.c 11 files changed, 33 insertions(+), 77 deletions(-) Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index b2b915f..251714c 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -33,6 +33,11 @@ bootblock_pre_c_entry: +#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) + movl $cache_as_ram, %esp /* return address */ + jmp check_mtrr /* Check if CPU properly reset */ +#endif + cache_as_ram: post_code(0x20) diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 3aadfde..3fd8bb4 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -24,10 +24,6 @@ select PARALLEL_MP select CPU_INTEL_COMMON -config BOOTBLOCK_CPU_INIT - string - default "cpu/intel/haswell/bootblock.c" - config SMM_TSEG_SIZE hex default 0x800000 diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 1fa71c9..3b52294 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -21,7 +21,11 @@ smm-y += monotonic_timer.c endif -cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S +bootblock-y += ../car/non-evict/cache_as_ram.S +bootblock-y += ../car/bootblock.c +bootblock-y += ../../x86/early_reset.S +bootblock-y += bootblock.c + postcar-y += ../car/non-evict/exit_car.S subdirs-y += ../../x86/tsc diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index 722cc01..7baa2a8 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -14,7 +14,7 @@ */ #include <stdint.h> -#include <cpu/x86/cache.h> +#include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <arch/io.h> @@ -23,41 +23,8 @@ #include <cpu/intel/microcode/microcode.c> #include "haswell.h" -#if CONFIG(SOUTHBRIDGE_INTEL_LYNXPOINT) -/* Needed for RCBA access to set Soft Reset Data register */ #include <southbridge/intel/lynxpoint/pch.h> -#else -#error "CPU must be paired with Intel LynxPoint southbridge" -#endif - -static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size, - unsigned int type) - -{ - /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ - /* FIXME: It only support 4G less range */ - msr_t basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); -} - -static void enable_rom_caching(void) -{ - msr_t msr; - - disable_cache(); - set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); - enable_cache(); - - /* Enable Variable MTRRs */ - msr.hi = 0x00000000; - msr.lo = 0x00000800; - wrmsr(MTRR_DEF_TYPE_MSR, msr); -} +#include <cpu/intel/car/bootblock.h> static void set_flex_ratio_to_tdp_nominal(void) { @@ -105,26 +72,8 @@ halt(); } -static void check_for_clean_reset(void) -{ - msr_t msr; - msr = rdmsr(MTRR_DEF_TYPE_MSR); - - /* Use the MTRR default type MSR as a proxy for detecting INIT#. - * Reset the system if any known bits are set in that MSR. That is - * an indication of the CPU not being properly reset. */ - if (msr.lo & (MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)) { - outb(0x0, 0xcf9); - outb(0x6, 0xcf9); - halt(); - } -} - -static void bootblock_cpu_init(void) +void bootblock_early_cpu_init(void) { /* Set flex ratio and reset if needed */ set_flex_ratio_to_tdp_nominal(); - check_for_clean_reset(); - enable_rom_caching(); - intel_update_microcode_from_cbfs(); } diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index 082f2d6..242ab18 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -22,6 +22,8 @@ select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select POSTCAR_STAGE select POSTCAR_CONSOLE + select C_ENVIRONMENT_BOOTBLOCK +# select BOOTBLOCK_CONSOLE TODO: route LPC if NORTHBRIDGE_INTEL_HASWELL @@ -29,10 +31,6 @@ select VBOOT_OPROM_MATTERS select VBOOT_STARTS_IN_ROMSTAGE -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/intel/haswell/bootblock.c" - config VGA_BIOS_ID string default "8086,0166" @@ -63,6 +61,13 @@ help The amount of cache-as-ram region required by the reference code. +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + config HAVE_MRC bool "Add a System Agent binary" help diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index 055c2a8..7abbcca 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -15,6 +15,8 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_HASWELL),y) +bootblock-y += bootblock.c + ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += gma.c @@ -26,7 +28,6 @@ romstage-y += raminit.c romstage-y += early_init.c romstage-y += report_platform.c -romstage-y += ../../../arch/x86/walkcbfs.S smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c diff --git a/src/northbridge/intel/haswell/bootblock.c b/src/northbridge/intel/haswell/bootblock.c index e503e01..2c1bd58 100644 --- a/src/northbridge/intel/haswell/bootblock.c +++ b/src/northbridge/intel/haswell/bootblock.c @@ -12,11 +12,10 @@ */ #include <device/pci_ops.h> +#include <cpu/intel/car/bootblock.h> +#include "haswell.h" -/* Just re-define this instead of including haswell.h. It blows up romcc. */ -#define PCIEXBAR 0x60 - -static void bootblock_northbridge_init(void) +void bootblock_early_northbridge_init(void) { uint32_t reg; @@ -33,7 +32,7 @@ * 4GiB. */ reg = 0; - pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR + 4, reg); + pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR + 4, reg); reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ - pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg); + pci_io_write_config32(PCI_DEV(0, 0, 0), PCIEXBAR, reg); } diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 431744f..5573ec9 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -53,10 +53,6 @@ hex default 0xe8000000 -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/lynxpoint/bootblock.c" - config SERIRQ_CONTINUOUS_MODE bool default n diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index b18e6da..62766df 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -15,6 +15,8 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT),y) +bootblock-y += bootblock.c + ramstage-y += pch.c ramstage-y += azalia.c ramstage-y += lpc.c diff --git a/src/southbridge/intel/lynxpoint/bootblock.c b/src/southbridge/intel/lynxpoint/bootblock.c index 16f4ef9..69fdd61 100644 --- a/src/southbridge/intel/lynxpoint/bootblock.c +++ b/src/southbridge/intel/lynxpoint/bootblock.c @@ -14,6 +14,7 @@ */ #include <device/pci_ops.h> +#include <cpu/intel/car/bootblock.h> #include "pch.h" /* @@ -69,7 +70,7 @@ SPIBAR8(SSFC + 2) = ssfc; } -static void bootblock_southbridge_init(void) +void bootblock_early_southbridge_init(void) { map_rcba(); enable_spi_prefetch(); diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 3d2d2c4..f615507 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -116,8 +116,6 @@ mainboard_config_superio(); - console_init(); - pch_generic_setup(); /* Enable SMBus for reading SPDs. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/26859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia96499a9d478127f6b9d880883ac41397b58dbea Gerrit-Change-Number: 26859 Gerrit-PatchSet: 56 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: merged

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Change in ...coreboot[master]: arch/x86: Move checking for MTRR's as a proxy for proper CPU reset
by Arthur Heymans (Code Review) 21 Apr '19

21 Apr '19

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32319 Change subject: arch/x86: Move checking for MTRR's as a proxy for proper CPU reset ...................................................................... arch/x86: Move checking for MTRR's as a proxy for proper CPU reset Checking for empty MTRR_DEF_TYPE_MSR as a proxy for proper CPU reset is common across multiple platforms. Therefore place it in a common location. Change-Id: I81d82fb9fe27cd9de6085251fe1a5685cdd651fc Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- A src/cpu/x86/early_reset.S M src/soc/intel/common/block/cpu/Makefile.inc M src/soc/intel/common/block/cpu/car/cache_as_ram.S 3 files changed, 44 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/32319/1 diff --git a/src/cpu/x86/early_reset.S b/src/cpu/x86/early_reset.S new file mode 100644 index 0000000..a35775c --- /dev/null +++ b/src/cpu/x86/early_reset.S @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * input %esp: return address (not pointer to return address!) + * clobber the content of eax, ecx, edx + */ + +#include <cpu/x86/mtrr.h> + +.global check_mtrr +check_mtrr: + + post_code(0x20) + + /* Use the MTRR default type MSR as a proxy for detecting INIT#. + * Reset the system if any known bits are set in that MSR. That is + * an indication of the CPU not being properly reset. */ + +check_for_clean_reset: + movl $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + andl $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax + cmp $0, %eax + jz *%esp + /* perform warm reset */ + movw $0xcf9, %dx + movb $0x06, %al + outb %al, %dx + diff --git a/src/soc/intel/common/block/cpu/Makefile.inc b/src/soc/intel/common/block/cpu/Makefile.inc index 5207227..a6c4f37 100644 --- a/src/soc/intel/common/block/cpu/Makefile.inc +++ b/src/soc/intel/common/block/cpu/Makefile.inc @@ -1,4 +1,5 @@ bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += car/cache_as_ram.S +bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CAR) += ../../../../../cpu/x86/early_reset.S bootblock-$(CONFIG_FSP_CAR)+= car/cache_as_ram_fsp.S bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CPU) += cpulib.c diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S index d3ee671..1160b09 100644 --- a/src/soc/intel/common/block/cpu/car/cache_as_ram.S +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -26,23 +26,8 @@ .global bootblock_pre_c_entry bootblock_pre_c_entry: - post_code(0x20) - - /* - * Use the MTRR default type MSR as a proxy for detecting INIT#. - * Reset the system if any known bits are set in that MSR. That is - * an indication of the CPU not being properly reset. - */ -check_for_clean_reset: - mov $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - and $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax - cmp $0, %eax - jz no_reset - /* perform warm reset */ - movw $0xcf9, %dx - movb $0x06, %al - outb %al, %dx + movl $no_reset, %esp /* return address */ + jmp check_mtrr /* Check if CPU properly reset */ no_reset: post_code(0x21) -- To view, visit https://review.coreboot.org/c/coreboot/+/32319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81d82fb9fe27cd9de6085251fe1a5685cdd651fc Gerrit-Change-Number: 32319 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: x86/acpi: Add Kconfig to toggle 8259 reporting
by Martin Roth (Code Review) 21 Apr '19

21 Apr '19

Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29832 ) Change subject: x86/acpi: Add Kconfig to toggle 8259 reporting ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29832/1/src/arch/x86/acpi.c File src/arch/x86/acpi.c: https://review.coreboot.org/#/c/29832/1/src/arch/x86/acpi.c@223 PS1, Line 223: IS_ENABLED(CONFIG_ACPI_HAVE_PCAT_8259) Switch to the new convention? if (CONFIG(ACPI_HAVE_PCAT_8259)) -- To view, visit https://review.coreboot.org/c/coreboot/+/29832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If3c9783ebc41c103c915788139d91644b805f397 Gerrit-Change-Number: 29832 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Sun, 21 Apr 2019 23:27:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: ipxe: Update stable version from 2017.3 to to 2019.3
by Martin Roth (Code Review) 21 Apr '19

21 Apr '19

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32345 Change subject: ipxe: Update stable version from 2017.3 to to 2019.3 ...................................................................... ipxe: Update stable version from 2017.3 to to 2019.3 Updating iPXE stable from commit id fd6d1f4660: Fri Mar 31 09:08:13 2017 +0300 [thunderx] Use ThunderxConfigProtocol to obtain board configuration to commit id ebf2eaf515: Mar 18 10:24:08 2019 +0000 [intel] Add PCI ID for I219-V and -LM 6 to 9 This brings in 176 new commits Change-Id: Id35fee38e0e61897a623dae35f42fc580e32d3ee Signed-off-by: Martin Roth <martinroth(a)google.com> --- M payloads/external/iPXE/Kconfig M payloads/external/iPXE/Makefile 2 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/32345/1 diff --git a/payloads/external/iPXE/Kconfig b/payloads/external/iPXE/Kconfig index ce0a7ae..f99182c 100644 --- a/payloads/external/iPXE/Kconfig +++ b/payloads/external/iPXE/Kconfig @@ -42,12 +42,12 @@ depends on BUILD_IPXE config IPXE_STABLE - bool "2017.3" + bool "2019.3" help iPXE uses a rolling release with no stable version, for reproducibility, use the last commit of a given month as the 'stable' version. - This is iPXE from the end of March, 2017. + This is iPXE from the end of March, 2019. config IPXE_MASTER bool "master" diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile index a8b1245..3a0585f 100644 --- a/payloads/external/iPXE/Makefile +++ b/payloads/external/iPXE/Makefile @@ -13,9 +13,9 @@ ## GNU General Public License for more details. ## -# 2017.3 - Last commit of March 2017 +# 2019.3 - Last commit of March 2019 # When updating, change the name both here and in payloads/external/iPXE/Kconfig -STABLE_COMMIT_ID=fd6d1f4660a37d75acba1c64e2e5f137307bbc31 +STABLE_COMMIT_ID=ebf2eaf515e46abd43bc798e7e4ba77bfe529218 TAG-$(CONFIG_IPXE_MASTER)=origin/master TAG-$(CONFIG_IPXE_STABLE)=$(STABLE_COMMIT_ID) -- To view, visit https://review.coreboot.org/c/coreboot/+/32345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id35fee38e0e61897a623dae35f42fc580e32d3ee Gerrit-Change-Number: 32345 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/amd/stoneyridge: Fix gnvs aoac initialization
by Marshall Dawson (Code Review) 21 Apr '19

21 Apr '19

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32355 Change subject: soc/amd/stoneyridge: Fix gnvs aoac initialization ...................................................................... soc/amd/stoneyridge: Fix gnvs aoac initialization Correct the SD and SATA assignments. TEST=Boot Grunt BUG=b:130788333 Change-Id: Ib75e1dbb0cd7f90a8d297d11d3a7c3bad47a8d21 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/stoneyridge/southbridge.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/32355/1 diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 2f32c5c..9c54694 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -927,9 +927,9 @@ gnvs->aoac.xhce = is_aoac_device_enabled(FCH_AOAC_D3_STATE_USB3); /* Rely on these being in sync with devicetree */ sd = pcidev_path_on_root(SD_DEVFN); - gnvs->aoac.st_e = sd && sd->enabled ? 1 : 0; + gnvs->aoac.sd_e = sd && sd->enabled ? 1 : 0; sata = pcidev_path_on_root(SATA_DEVFN); - gnvs->aoac.sd_e = sata && sata->enabled ? 1 : 0; + gnvs->aoac.st_e = sata && sata->enabled ? 1 : 0; gnvs->aoac.espi = 1; amdfw_rom = 0x20000 - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX); -- To view, visit https://review.coreboot.org/c/coreboot/+/32355 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib75e1dbb0cd7f90a8d297d11d3a7c3bad47a8d21 Gerrit-Change-Number: 32355 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP]mainboard/lenovo/t410: Add new port
by Peter Lemenkov (Code Review) 21 Apr '19

21 Apr '19

Peter Lemenkov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/11791 ) Change subject: [WIP]mainboard/lenovo/t410: Add new port ...................................................................... Patch Set 13: > Can't seem to get this one to boot. Anything in particular I should > be doing? Also what exactly this means? Do you have any boot log output? -- To view, visit https://review.coreboot.org/c/coreboot/+/11791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Gerrit-Change-Number: 11791 Gerrit-PatchSet: 13 Gerrit-Owner: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eloy Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Okashi Odayakana <okashi(a)okashi.me> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Comment-Date: Sun, 21 Apr 2019 21:13:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: [WIP]mainboard/lenovo/t410: Add new port
by Peter Lemenkov (Code Review) 21 Apr '19

21 Apr '19

Peter Lemenkov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/11791 ) Change subject: [WIP]mainboard/lenovo/t410: Add new port ...................................................................... Patch Set 13: > Can't seem to get this one to boot. Anything in particular I should > be doing? Please try older patchsets. Very likely I've made some mistakes while trying to get it to compile with a most recent master. -- To view, visit https://review.coreboot.org/c/coreboot/+/11791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Gerrit-Change-Number: 11791 Gerrit-PatchSet: 13 Gerrit-Owner: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eloy Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Okashi Odayakana <okashi(a)okashi.me> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Comment-Date: Sun, 21 Apr 2019 21:12:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/intel/broadwell: Enable LPC/SIO setup in bootblock
by Felix Held (Code Review) 21 Apr '19

21 Apr '19

Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30385 ) Change subject: soc/intel/broadwell: Enable LPC/SIO setup in bootblock ...................................................................... Patch Set 40: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7746e4f819486d6142c96bc4c7480076fbfdfbde Gerrit-Change-Number: 30385 Gerrit-PatchSet: 40 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 21 Apr 2019 20:04:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: cpu/intel: Use system_reset()
by HAOUAS Elyes (Code Review) 21 Apr '19

21 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32380 Change subject: cpu/intel: Use system_reset() ...................................................................... cpu/intel: Use system_reset() Use already defined system_reset() function. Change-Id: I1f137611f46caddc5d4d356c73c4f335d030c1c8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/fsp_model_406dx/bootblock.c M src/cpu/intel/haswell/bootblock.c M src/cpu/intel/model_2065x/bootblock.c M src/cpu/intel/model_206ax/bootblock.c 4 files changed, 8 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/32380/1 diff --git a/src/cpu/intel/fsp_model_406dx/bootblock.c b/src/cpu/intel/fsp_model_406dx/bootblock.c index 14cfad9..009c09c 100644 --- a/src/cpu/intel/fsp_model_406dx/bootblock.c +++ b/src/cpu/intel/fsp_model_406dx/bootblock.c @@ -39,8 +39,7 @@ if ((inb(0xcf9) == 0x04) || (pci_io_read_config32(SOC_LPC_DEV, RCBA) & RCBA_ENABLE)) { - outb(0x00, 0xcf9); - outb(0x06, 0xcf9); + system_reset(); } } diff --git a/src/cpu/intel/haswell/bootblock.c b/src/cpu/intel/haswell/bootblock.c index 722cc01..cdbd0ac 100644 --- a/src/cpu/intel/haswell/bootblock.c +++ b/src/cpu/intel/haswell/bootblock.c @@ -14,6 +14,7 @@ */ #include <stdint.h> +#include <cf9_reset.h> #include <cpu/x86/cache.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> @@ -100,9 +101,7 @@ RCBA32_OR(SOFT_RESET_CTRL, 1); /* Issue warm reset, will be "CPU only" due to soft reset data */ - outb(0x0, 0xcf9); - outb(0x6, 0xcf9); - halt(); + system_reset(); } static void check_for_clean_reset(void) @@ -114,9 +113,7 @@ * Reset the system if any known bits are set in that MSR. That is * an indication of the CPU not being properly reset. */ if (msr.lo & (MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)) { - outb(0x0, 0xcf9); - outb(0x6, 0xcf9); - halt(); + system_reset(); } } diff --git a/src/cpu/intel/model_2065x/bootblock.c b/src/cpu/intel/model_2065x/bootblock.c index 19dbda8..693ae7a 100644 --- a/src/cpu/intel/model_2065x/bootblock.c +++ b/src/cpu/intel/model_2065x/bootblock.c @@ -15,6 +15,7 @@ #include <stdint.h> #include <arch/cpu.h> +#include <cf9_reset.h> #include <cpu/x86/cache.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> @@ -104,9 +105,7 @@ RCBA32_OR(SOFT_RESET_CTRL, 1); /* Issue warm reset, will be "CPU only" due to soft reset data */ - outb(0x0, 0xcf9); - outb(0x6, 0xcf9); - halt(); + system_reset(); } static void bootblock_cpu_init(void) diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index 9dcbe37..a7ba2030 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -15,6 +15,7 @@ #include <stdint.h> #include <arch/cpu.h> +#include <cf9_reset.h> #include <cpu/x86/cache.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> @@ -106,9 +107,7 @@ RCBA32_OR(SOFT_RESET_CTRL, 1); /* Issue warm reset, will be "CPU only" due to soft reset data */ - outb(0x0, 0xcf9); - outb(0x6, 0xcf9); - halt(); + system_reset(); } static void bootblock_cpu_init(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/32380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1f137611f46caddc5d4d356c73c4f335d030c1c8 Gerrit-Change-Number: 32380 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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