coreboot-gerrit April 2019

coreboot-gerrit@coreboot.org

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1219 discussions

Change in ...coreboot[master]: soc/intel/common/acpi: Fix leakage power on Touchscreen during S5
by Roy Mingi Park (Code Review) 22 Apr '19

22 Apr '19

Roy Mingi Park has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32360 Change subject: soc/intel/common/acpi: Fix leakage power on Touchscreen during S5 ...................................................................... soc/intel/common/acpi: Fix leakage power on Touchscreen during S5 Leakage power is observed from 3V_TSP_S0_FUSE during S5. To avoid leakage power, GPP_E7 needs to be turned off before S5 entry BUG=b:129899315 TEST= Measure leakage power in S5 from both Arcada and Sarien Change-Id: Id63c992df929c1c4a3992905c9189cdacd8c6e42 Signed-off-by: Roy Mingi Park <roy.mingi.park(a)intel.com> --- M src/soc/intel/common/acpi/platform.asl 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/32360/1 diff --git a/src/soc/intel/common/acpi/platform.asl b/src/soc/intel/common/acpi/platform.asl index bdc0d5c..3d725b6 100644 --- a/src/soc/intel/common/acpi/platform.asl +++ b/src/soc/intel/common/acpi/platform.asl @@ -34,6 +34,11 @@ { Store (POST_OS_ENTER_PTS, DBG0) + if( Arg0 == 5) + { + \_SB.PCI0.CTXS(GPP_E7) + } + #if CONFIG(SOC_INTEL_COMMON_ACPI_EC_PTS_WAK) /* Call EC _PTS handler */ \_SB.PCI0.LPCB.EC0.PTS (Arg0) -- To view, visit https://review.coreboot.org/c/coreboot/+/32360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id63c992df929c1c4a3992905c9189cdacd8c6e42 Gerrit-Change-Number: 32360 Gerrit-PatchSet: 1 Gerrit-Owner: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: Revert "soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/...
by Lijian Zhao (Code Review) 22 Apr '19

22 Apr '19

Hello Aaron Durbin, Patrick Rudolph, Nathaniel L Desimone, Subrata Banik, Aamir Bohra, Maulik V Vaghela, Duncan Laurie, Rizwan Qureshi, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32391 to review the following change. Change subject: Revert "soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML" ...................................................................... Revert "soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML" This reverts commit 41dad286d846819242a84fc65faed2bbb35845ac. The change will make s0ix fail on Sarien/Arcada Platform. Change-Id: I169bc6f41fba82fcf515267e8e1d08aa5ee2dce4 --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/romstage/fsp_params.c 3 files changed, 1 insertion(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/32391/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 14404f7..c30b562 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -27,8 +27,6 @@ bool default n select SOC_INTEL_COMMON_CANNONLAKE_BASE - select FSP_PEIM_TO_PEIM_INTERFACE - select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI help Intel Whiskeylake support @@ -36,12 +34,6 @@ bool default n select SOC_INTEL_COMMON_CANNONLAKE_BASE - # TODO: - # Delete FSP_PEIM_TO_PEIM_INTERFACE and - # USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI selection - # and select PLATFORM_USES_FSP2_1 once FSP support for CML is ready - select FSP_PEIM_TO_PEIM_INTERFACE - select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI help Intel Cometlake support diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 1fd42cd..b8dba18 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -18,9 +18,7 @@ #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> -#include <fsp/ppi/mp_service_ppi.h> #include <fsp/util.h> -#include <intelblocks/mp_init.h> #include <intelblocks/xdci.h> #include <soc/intel/common/vbt.h> #include <soc/pci_devs.h> @@ -144,9 +142,6 @@ params->Usb3OverCurrentPin[i] = 0; } - if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) - params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); - mainboard_silicon_init_params(params); /* Set PsysPmax if it is available from DT */ diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 4545f52..ffdcee4 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -68,10 +68,7 @@ m_cfg->VmxEnable = config->VmxEnable; #if CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE) - if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) - m_cfg->SkipMpInit = 0; - else - m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; + m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; #endif /* Set CpuRatio to match existing MSR value */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I169bc6f41fba82fcf515267e8e1d08aa5ee2dce4 Gerrit-Change-Number: 32391 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML
by Subrata Banik (Code Review) 22 Apr '19

22 Apr '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32301 Change subject: soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML ...................................................................... soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML This patch performs MP initialization by FSP using coreboot MP PPI service. BUG=b:74436746 TEST=Able to perform MP initialization on WHL and CML platform. Change-Id: I530d50e5aacc3cb9b625df14a50d4c5923e3fb4d Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/romstage/fsp_params.c 3 files changed, 17 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/32301/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 55fef5a..52f0e41 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -27,6 +27,8 @@ bool default n select SOC_INTEL_COMMON_CANNONLAKE_BASE + select FSP_PEIM_TO_PEIM_INTERFACE + select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI help Intel Whiskeylake support @@ -34,6 +36,12 @@ bool default n select SOC_INTEL_COMMON_CANNONLAKE_BASE + # TODO: + # Delete FSP_PEIM_TO_PEIM_INTERFACE and + # USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI selection + # and select PLATFORM_USES_FSP2_1 once FSP support for CML is ready + select FSP_PEIM_TO_PEIM_INTERFACE + select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI help Intel Cometlake support diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index b8dba18..1fd42cd 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -18,7 +18,9 @@ #include <device/device.h> #include <device/pci.h> #include <fsp/api.h> +#include <fsp/ppi/mp_service_ppi.h> #include <fsp/util.h> +#include <intelblocks/mp_init.h> #include <intelblocks/xdci.h> #include <soc/intel/common/vbt.h> #include <soc/pci_devs.h> @@ -142,6 +144,9 @@ params->Usb3OverCurrentPin[i] = 0; } + if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) + params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); + mainboard_silicon_init_params(params); /* Set PsysPmax if it is available from DT */ diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index ffdcee4..4545f52 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -68,7 +68,10 @@ m_cfg->VmxEnable = config->VmxEnable; #if CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE) - m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; + if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) + m_cfg->SkipMpInit = 0; + else + m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; #endif /* Set CpuRatio to match existing MSR value */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32301 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I530d50e5aacc3cb9b625df14a50d4c5923e3fb4d Gerrit-Change-Number: 32301 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: board/kukui: Print ADC values on failure in getting board IDs
by Hung-Te Lin (Code Review) 22 Apr '19

22 Apr '19

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32353 Change subject: board/kukui: Print ADC values on failure in getting board IDs ...................................................................... board/kukui: Print ADC values on failure in getting board IDs WIP: Need a better way to report ADC failures. BUG=None TEST=None BRANCH=None Change-Id: I8d00956e0e3b48ddbcaa505dd3ade24720c3b4ad Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/google/kukui/boardid.c 1 file changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/32353/1 diff --git a/src/mainboard/google/kukui/boardid.c b/src/mainboard/google/kukui/boardid.c index b9f1ba2..953ae33 100644 --- a/src/mainboard/google/kukui/boardid.c +++ b/src/mainboard/google/kukui/boardid.c @@ -15,6 +15,7 @@ #include <assert.h> #include <boardid.h> +#include <console/console.h> #include <soc/auxadc.h> #include <ec/google/chromeec/ec.h> #include <stddef.h> @@ -83,7 +84,11 @@ break; const int tolerance = 10000; /* 10,000 uV */ - assert(ABS(value - voltages[id]) < tolerance); + if (ABS(value - voltages[id]) < tolerance) { + printk(BIOS_ERR, "ADC channel %u value out of range: %d\n" + channel, value); + die("Invalid ADC value"); + } return id; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8d00956e0e3b48ddbcaa505dd3ade24720c3b4ad Gerrit-Change-Number: 32353 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien: Configure both GPP_A13 and GPP_15 for SSD on Arcada
by Roy Mingi Park (Code Review) 22 Apr '19

22 Apr '19

Roy Mingi Park has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32361 Change subject: mb/google/sarien: Configure both GPP_A13 and GPP_15 for SSD on Arcada ...................................................................... mb/google/sarien: Configure both GPP_A13 and GPP_15 for SSD on Arcada Currently, Arcada only supports D3hot during S0iX and there is a power leakage around 5~10mW depending on SSD vendors. To support D3cold for SSD during S0iX, one MOSFET(U6310) will be added on DVT2 and two GPIOs are required to be configured. GPP_A13 is to control SSD_SCP_PWR_EN(power enable) and GPP_A13 is to control SSD reset. BUG=b:130741066 TEST=Measure both SSD power and platform power during S0iX from Arcada Change-Id: I868590e9e85d5df07930a3681884e3fc3a5c4d50 Signed-off-by: Roy Mingi Park <roy.mingi.park(a)intel.com> --- M src/mainboard/google/sarien/variants/arcada/gpio.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/32361/1 diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index b66e1dd..7583b51 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -32,9 +32,9 @@ /* PME# */ PAD_NC(GPP_A11, NONE), /* ISH_LID_CL#_TAB */ /* BM_BUSY# */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), -/* SUSWARN# */ PAD_NC(GPP_A13, NONE), +/* SUSWARN# */ PAD_CFG_GPO(GPP_A13, 1, DEEP), /* ESPI_RESET# */ -/* SUSACK# */ PAD_NC(GPP_A15, NONE), +/* SUSACK# */ PAD_CFG_GPO(GPP_A15, 1, DEEP), /* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), /* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), /* ISH_ACC1_INT# */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I868590e9e85d5df07930a3681884e3fc3a5c4d50 Gerrit-Change-Number: 32361 Gerrit-PatchSet: 1 Gerrit-Owner: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien: Add SMBIOS type 9 fields
by Lijian Zhao (Code Review) 22 Apr '19

22 Apr '19

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32389 ) Change subject: mb/google/sarien: Add SMBIOS type 9 fields ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/32389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I47a697131b7aeeb64e0c4b4c0556842f1cb1b02e Gerrit-Change-Number: 32389 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 22 Apr 2019 17:26:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: TEMP: NOT FOR REVIEW: qcs405: Add bl31 stage and elf
by build bot (Jenkins) (Code Review) 22 Apr '19

22 Apr '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29981 ) Change subject: TEMP: NOT FOR REVIEW: qcs405: Add bl31 stage and elf ...................................................................... Patch Set 21: (1 comment) https://review.coreboot.org/#/c/29981/21/src/soc/qualcomm/qcs405/soc.c File src/soc/qualcomm/qcs405/soc.c: https://review.coreboot.org/#/c/29981/21/src/soc/qualcomm/qcs405/soc.c@26 PS21, Line 26: bootmem_add_range((uintptr_t)_dram_reserved, _dram_reserved_size, BM_MEM_BL31); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I967c0b78a3561574609bf8332a22838c85e43429 Gerrit-Change-Number: 29981 Gerrit-PatchSet: 21 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 22 Apr 2019 15:01:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: qcs405: memlayout: Make bootblock 64k aligned
by Nitheesh Sekar (Code Review) 22 Apr '19

22 Apr '19

Hello Julius Werner, build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29969 to look at the new patch set (#22). Change subject: qcs405: memlayout: Make bootblock 64k aligned ...................................................................... qcs405: memlayout: Make bootblock 64k aligned The qc_sec in qcs405 expects the bootblock to be 64k aligned. So adjust the memlayout accordingly. Change-Id: I1599242bb5158477318867508c72dc14f1244b00 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/include/soc/memlayout.ld 1 file changed, 9 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/29969/22 -- To view, visit https://review.coreboot.org/c/coreboot/+/29969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1599242bb5158477318867508c72dc14f1244b00 Gerrit-Change-Number: 29969 Gerrit-PatchSet: 22 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: qcs405: Add UART support
by Nitheesh Sekar (Code Review) 22 Apr '19

22 Apr '19

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29964 to look at the new patch set (#20). Change subject: qcs405: Add UART support ...................................................................... qcs405: Add UART support Add support for UART driver in coreboot. TEST=build & run Change-Id: Id9626c68eadead8b8ec5ffbc08cab7b0ec36478f Signed-off-by: Prudhvi Yarlagadda<pyarlaga(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Kconfig M src/soc/qualcomm/qcs405/Makefile.inc A src/soc/qualcomm/qcs405/include/soc/blsp.h A src/soc/qualcomm/qcs405/include/soc/cdp.h A src/soc/qualcomm/qcs405/include/soc/iomap.h A src/soc/qualcomm/qcs405/include/soc/uart.h A src/soc/qualcomm/qcs405/uart.c 7 files changed, 941 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/29964/20 -- To view, visit https://review.coreboot.org/c/coreboot/+/29964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9626c68eadead8b8ec5ffbc08cab7b0ec36478f Gerrit-Change-Number: 29964 Gerrit-PatchSet: 20 Gerrit-Owner: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nitheesh Sekar <nsekar(a)codeaurora.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: nb/i945: Refactor sdram_rcomp_buffer_strength_and_slew for i945GC
by HAOUAS Elyes (Code Review) 22 Apr '19

22 Apr '19

Hello Patrick Rudolph, Arthur Heymans, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/27590 to look at the new patch set (#9). Change subject: nb/i945: Refactor sdram_rcomp_buffer_strength_and_slew for i945GC ...................................................................... nb/i945: Refactor sdram_rcomp_buffer_strength_and_slew for i945GC Those vales are used by vendorbios. 945G-M4 board boots fine when DIMM0 is not populated. Still not boot: - When channel0 is not populated at all. This is probably linked to "rcven.c". This file seems to be designed for only 2 DIMMS. - When 533MHz RAM is used. Probably clocking at 533MHz for i945GC is broken. Could you check if this breaks some thing for i945 laptop version? Change-Id: Iff1705788fdffeacd94fe5e50507733ff7c0f96b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/i945/raminit.c 1 file changed, 116 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/27590/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/27590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iff1705788fdffeacd94fe5e50507733ff7c0f96b Gerrit-Change-Number: 27590 Gerrit-PatchSet: 9 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit April 2019