Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32182
Change subject: hifive-unleashed: update documentation to match current state
......................................................................
hifive-unleashed: update documentation to match current state
Signed-off-by: Philipp Hug <philipp(a)hug.cx>
Change-Id: I3f1b7dd4ef52a64c9a222f2d5cffe2b73806fe4e
---
M Documentation/mainboard/sifive/hifive-unleashed.md
1 file changed, 3 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/32182/1
diff --git a/Documentation/mainboard/sifive/hifive-unleashed.md b/Documentation/mainboard/sifive/hifive-unleashed.md
index cd7c93c..495dade 100644
--- a/Documentation/mainboard/sifive/hifive-unleashed.md
+++ b/Documentation/mainboard/sifive/hifive-unleashed.md
@@ -12,15 +12,13 @@
The following things are still missing from this coreboot port:
- Support running romstage from flash (fix stack) to support boot mode 1
-- CBMEM support
-- FU540 clock configuration
-- FU540 RAM init
-- Placing the ramstage in DRAM
- Starting the U54 cores
- FU540 PIN configuration and GPIO access macros
- Provide serial number to payload (e.g. in device tree)
+- Implement instruction emulation
- Support for booting Linux on RISC-V
-
+- Add support to run OpenSBI payload in m-mode
+- SMP support in trap handler
## Configuration
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Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28464 )
Change subject: drivers/intel/fsp1_1: Configure UART after memory init
......................................................................
Patch Set 4:
> Patch Set 4:
>
> https://github.com/IntelFsp/FSP/commit/1d2b7e1a94c6a7c25a6fed1ac37caebf500f…
Thanks for pointing out. The .fd itself is not changed. I assume bug will still exist.
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28464 )
Change subject: drivers/intel/fsp1_1: Configure UART after memory init
......................................................................
Patch Set 4:
https://github.com/IntelFsp/FSP/commit/1d2b7e1a94c6a7c25a6fed1ac37caebf500f…
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Change subject: drivers/intel/fsp1_1: Configure UART after memory init
......................................................................
Patch Set 4:
> Patch Set 4:
>
> A "new" version of the FSP was released. Please test if it fixes your issue.
Where can I find the 'new' FSP?
I can find MR2 release as latest version only. (MR2 = version with bug)
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Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29414 )
Change subject: soc/intel/braswell: Include LPE ACPI code in mainboard
......................................................................
Patch Set 10:
> Patch Set 10:
>
> (1 comment)
I agree with you on this patchset.
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27360 )
Change subject: sdm845: Add interface between CB & QCLib
......................................................................
Patch Set 35:
(2 comments)
> One comment from PS31 on 9.Nov.2018 is not addressed yet, regarding CONFIG_CBFS_PREFIX being part of #define for name, e.g. "/pmic". Please confirm, after reviewing latest patch that this is still desired change.
Yes, I still think that would be a bit cleaner.
https://review.coreboot.org/#/c/27360/26/src/soc/qualcomm/sdm845/qclib_exec…
File src/soc/qualcomm/sdm845/qclib_execute.c:
https://review.coreboot.org/#/c/27360/26/src/soc/qualcomm/sdm845/qclib_exec…
PS26, Line 203: ddr_mmu->size = ddr_size * MiB;
> QCLib is still passing back block size and this multiply is still occurring, please confirm you are […]
I think we should change it for clarity, for all the other TE blobs the 'size' value is in bytes. It's going to be a bit nasty because it needs to change on both ends at once, but that will be easier now than later when we have another couple of SoCs using this interface.
https://review.coreboot.org/#/c/27360/32/src/soc/qualcomm/sdm845/qclib_exec…
File src/soc/qualcomm/sdm845/qclib_execute.c:
https://review.coreboot.org/#/c/27360/32/src/soc/qualcomm/sdm845/qclib_exec…
PS32, Line 223: dump_te_table();
> Need it, probably not, I find it good diagnostic data to have in the log output. […]
I'm okay with leaving it in.
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25213 )
Change subject: sdm845: Add USB support on cheza platform
......................................................................
Patch Set 68: -Code-Review
(1 comment)
https://review.coreboot.org/#/c/25213/68/src/soc/qualcomm/sdm845/usb.c
File src/soc/qualcomm/sdm845/usb.c:
https://review.coreboot.org/#/c/25213/68/src/soc/qualcomm/sdm845/usb.c@791
PS68, Line 791: /*
> trailing whitespace
Need to fix this one to get the Verified+1
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Change subject: sdm845: Add USB support on cheza platform
......................................................................
Patch Set 68: Code-Review+2
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